mirror of https://github.com/PCSX2/pcsx2.git
Adjusted VSync to work more like the PS2 does it, also involves a small change which "might" sold some half screen issues. Fixed a couple of counter log bugs too (caused it to crash when EE Counter logs were enabled)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@4624 96395faa-99c1-11dd-bbfe-3dabce05a288
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@ -193,7 +193,14 @@ static void vSyncInfoCalc( vSyncTimingInfo* info, Fixed100 framesPerSecond, u32
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u64 Frame = ((u64)PS2CLK * 1000000ULL) / (framesPerSecond*100).ToIntRounded();
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u64 HalfFrame = Frame / 2;
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u64 Blank = HalfFrame / 2; // two blanks and renders per frame
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u64 Blank = (Frame / scansPerFrame) * 22; // PAL VBlank Period is roughly 22 HSyncs
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if(scansPerFrame == SCANLINES_TOTAL_NTSC)
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Blank = (Frame / scansPerFrame) * 26; // NTSC VBlank Period is roughly 26 HSyncs, so we update
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//I would have suspected this to be Frame - Blank, but that seems to completely freak it out
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//and the test results are completely wrong. It seems 100% the same as the PS2 test on this,
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//So let's roll with it :P
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u64 Render = HalfFrame - Blank; // so use the half-frame value for these...
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// Important! The hRender/hBlank timers should be 50/50 for best results.
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@ -237,9 +244,7 @@ u32 UpdateVSyncRate()
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// The PS2's vsync timer is an *independent* crystal that is fixed to either 59.94 (NTSC)
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// or 50.0 (PAL) Hz. It has *nothing* to do with real TV timings or the real vsync of
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// the GS's output circuit. It is the same regardless if the GS is outputting interlace
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// or progressive scan content. Indications are that it is also a simple 50/50 timer and
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// that it does not actually measure Vblank/Vdraw zones accurately (which would be like
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// 1/5 and 4/5 ratios).
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// or progressive scan content.
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Fixed100 framerate;
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u32 scanlines;
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@ -264,11 +269,6 @@ u32 UpdateVSyncRate()
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Console.WriteLn( Color_Green, "(UpdateVSyncRate) Mode Changed to %s.", ( gsRegionMode == Region_PAL ) ? "PAL" : "NTSC" );
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if( isCustom )
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Console.Indent().WriteLn( Color_StrongGreen, "... with user configured refresh rate: %.02f Hz", framerate.ToFloat() );
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hsyncCounter.CycleT = vSyncInfo.hRender; // Amount of cycles before the counter will be updated
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vsyncCounter.CycleT = vSyncInfo.Render; // Amount of cycles before the counter will be updated
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cpuRcntSet();
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}
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Fixed100 fpslimit = framerate *
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@ -369,7 +369,7 @@ static __fi void VSyncStart(u32 sCycle)
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hwIntcIrq(INTC_VBLANK_S);
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psxVBlankStart();
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gsPostVsyncStart();
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if (gates) rcntStartGate(true, sCycle); // Counters Start Gate code
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// INTC - VB Blank Start Hack --
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@ -399,7 +399,7 @@ static __fi void VSyncEnd(u32 sCycle)
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g_FrameCount++;
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gsPostVsyncEnd();
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hwIntcIrq(INTC_VBLANK_E); // HW Irq
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psxVBlankEnd(); // psxCounters vBlank End
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@ -463,16 +463,16 @@ __fi void rcntUpdate_vSync()
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{
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VSyncEnd(vsyncCounter.sCycle);
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vsyncCounter.sCycle += vSyncInfo.Blank;
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vsyncCounter.CycleT = vSyncInfo.Render;
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vsyncCounter.sCycle += vSyncInfo.Render;
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vsyncCounter.CycleT = 0;
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vsyncCounter.Mode = MODE_VRENDER;
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}
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else // VSYNC end / VRENDER begin
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{
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VSyncStart(vsyncCounter.sCycle);
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vsyncCounter.sCycle += vSyncInfo.Render;
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vsyncCounter.CycleT = vSyncInfo.Blank;
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vsyncCounter.sCycle += vSyncInfo.Blank;
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vsyncCounter.CycleT = 0;
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vsyncCounter.Mode = MODE_VSYNC;
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// Accumulate hsync rounding errors:
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@ -620,8 +620,8 @@ static __fi void rcntStartGate(bool isVblank, u32 sCycle)
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counters[i].mode.IsCounting = 1;
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counters[i].sCycleT = sCycle;
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EECNT_LOG("EE Counter[%d] %s StartGate Type0, count = %x",
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isVblank ? "vblank" : "hblank", i, counters[i].count );
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EECNT_LOG("EE Counter[%d] %s StartGate Type0, count = %x", i,
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isVblank ? "vblank" : "hblank", counters[i].count );
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break;
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case 0x2: // reset and start counting on vsync end
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@ -634,8 +634,8 @@ static __fi void rcntStartGate(bool isVblank, u32 sCycle)
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counters[i].count = 0;
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counters[i].target &= 0xffff;
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counters[i].sCycleT = sCycle;
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EECNT_LOG("EE Counter[%d] %s StartGate Type%d, count = %x",
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isVblank ? "vblank" : "hblank", i, counters[i].mode.GateMode, counters[i].count );
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EECNT_LOG("EE Counter[%d] %s StartGate Type%d, count = %x", i,
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isVblank ? "vblank" : "hblank", counters[i].mode.GateMode, counters[i].count );
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break;
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}
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}
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@ -667,8 +667,8 @@ static __fi void rcntEndGate(bool isVblank , u32 sCycle)
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counters[i].count = rcntRcount(i);
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counters[i].mode.IsCounting = 0;
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counters[i].sCycleT = sCycle;
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EECNT_LOG("EE Counter[%d] %s EndGate Type0, count = %x",
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isVblank ? "vblank" : "hblank", i, counters[i].count );
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EECNT_LOG("EE Counter[%d] %s EndGate Type0, count = %x", i,
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isVblank ? "vblank" : "hblank", counters[i].count );
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break;
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case 0x1: // Reset and start counting on Vsync start
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@ -681,8 +681,8 @@ static __fi void rcntEndGate(bool isVblank , u32 sCycle)
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counters[i].count = 0;
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counters[i].target &= 0xffff;
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counters[i].sCycleT = sCycle;
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EECNT_LOG("EE Counter[%d] %s EndGate Type%d, count = %x",
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isVblank ? "vblank" : "hblank", i, counters[i].mode.GateMode, counters[i].count );
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EECNT_LOG("EE Counter[%d] %s EndGate Type%d, count = %x", i,
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isVblank ? "vblank" : "hblank", counters[i].mode.GateMode, counters[i].count );
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break;
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}
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}
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@ -438,10 +438,13 @@ __fi void gsFrameSkip()
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}
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}
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void gsPostVsyncEnd()
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//These are done at VSync Start. Drawing is done when VSync is off, then output the screen when Vsync is on
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//The GS needs to be told at the start of a vsync else it loses half of its picture (could be responsible for some halfscreen issues)
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//We got away with it before i think due to our awful GS timing, but now we have it right (ish)
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void gsPostVsyncStart()
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{
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CSRreg.SwapField();
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GetMTGS().PostVsyncEnd();
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GetMTGS().PostVsyncStart();
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}
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void _gs_ResetFrameskip()
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@ -331,7 +331,7 @@ public:
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u8* GetDataPacketPtr() const;
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void SetEvent();
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void PostVsyncEnd();
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void PostVsyncStart();
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bool IsPluginOpened() const { return m_PluginOpened; }
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@ -371,7 +371,7 @@ extern void gsReset();
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extern void gsOnModeChanged( Fixed100 framerate, u32 newTickrate );
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extern void gsSetRegionMode( GS_RegionMode isPal );
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extern void gsResetFrameSkip();
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extern void gsPostVsyncEnd();
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extern void gsPostVsyncStart();
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extern void gsFrameSkip();
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// Some functions shared by both the GS and MTGS
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@ -125,7 +125,7 @@ struct RingCmdPacket_Vsync
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GSRegSIGBLID siglblid;
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};
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void SysMtgsThread::PostVsyncEnd()
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void SysMtgsThread::PostVsyncStart()
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{
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// Optimization note: Typically regset1 isn't needed. The regs in that area are typically
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// changed infrequently, usually during video mode changes. However, on modern systems the
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