mirror of https://github.com/PCSX2/pcsx2.git
SPU2-X: Some bugfixes to reverb that were introduced in my last commit. Still some minor problems in this build. I'll fix them soon.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@527 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine
parent
058ec7db30
commit
d97cde6583
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@ -113,13 +113,18 @@ struct StereoOut32
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StereoOut16 DownSample() const;
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StereoOut32 operator+( const StereoOut32& right )
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StereoOut32 operator+( const StereoOut32& right ) const
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{
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return StereoOut32(
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Left + right.Left,
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Right + right.Right
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);
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}
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StereoOut32 operator/( int src ) const
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{
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return StereoOut32( Left / src, Right / src );
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}
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};
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#endif
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@ -50,7 +50,11 @@ void Reverb_AdvanceBuffer( V_Core& thiscore )
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{
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if( (Cycles & 1) && (thiscore.EffectsBufferSize > 0) )
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{
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thiscore.ReverbX = RevbGetIndexer( thiscore, 1 );
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//thiscore.ReverbX = RevbGetIndexer( thiscore, 1 );
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thiscore.ReverbX += 1;
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if( thiscore.ReverbX >= thiscore.EffectsBufferSize ) thiscore.ReverbX = 0;
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//thiscore.ReverbX += 1;
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//if(thiscore.ReverbX >= (u32)thiscore.EffectsBufferSize )
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// thiscore.ReverbX %= (u32)thiscore.EffectsBufferSize;
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@ -64,17 +68,10 @@ StereoOut32 DoReverb( V_Core& thiscore, const StereoOut32& Input )
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// Reverb processing occurs at 24khz, so we skip processing every other sample,
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// and use the previous calculation for this core instead.
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if( thiscore.EffectsBufferSize <= 0 )
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{
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// StartA is past EndA, so effects are disabled.
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//ConLog( " * SPU2: Effects disabled due to leapfrogged EffectsStart." );
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return Input;
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}
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if( (Cycles&1)==0 )
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{
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StereoOut32 retval( thiscore.LastEffect );
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thiscore.LastEffect = Input;
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thiscore.LastEffect = Input/2;
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return retval;
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}
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else
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@ -82,6 +79,13 @@ StereoOut32 DoReverb( V_Core& thiscore, const StereoOut32& Input )
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if( thiscore.RevBuffers.NeedsUpdated )
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thiscore.UpdateEffectsBufferSize();
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if( thiscore.EffectsBufferSize <= 0 )
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{
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// StartA is past EndA, so effects are disabled.
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//ConLog( " * SPU2: Effects disabled due to leapfrogged EffectsStart." );
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return Input;
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}
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// Advance the current reverb buffer pointer, and cache the read/write addresses we'll be
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// needing for this session of reverb.
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@ -131,21 +135,20 @@ StereoOut32 DoReverb( V_Core& thiscore, const StereoOut32& Input )
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const s32 IIR_INPUT_B0 = ((_spu2mem[src_b0] * thiscore.Revb.IIR_COEF) + (INPUT_SAMPLE.Left * thiscore.Revb.IN_COEF_L))>>16;
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const s32 IIR_INPUT_B1 = ((_spu2mem[src_b1] * thiscore.Revb.IIR_COEF) + (INPUT_SAMPLE.Right * thiscore.Revb.IN_COEF_R))>>16;
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//const s32 IIR_A0 = (IIR_INPUT_A0 * thiscore.Revb.IIR_ALPHA) + (_spu2mem[dest_a0] * (0x7fff - thiscore.Revb.IIR_ALPHA));
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//const s32 IIR_A1 = (IIR_INPUT_A1 * thiscore.Revb.IIR_ALPHA) + (_spu2mem[dest_a1] * (0x7fff - thiscore.Revb.IIR_ALPHA));
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//const s32 IIR_B0 = (IIR_INPUT_B0 * thiscore.Revb.IIR_ALPHA) + (_spu2mem[dest_b0] * (0x7fff - thiscore.Revb.IIR_ALPHA));
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//const s32 IIR_B1 = (IIR_INPUT_B1 * thiscore.Revb.IIR_ALPHA) + (_spu2mem[dest_b1] * (0x7fff - thiscore.Revb.IIR_ALPHA));
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//_spu2mem[dest2_a0] = clamp_mix( IIR_A0 >> 16 );
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//_spu2mem[dest2_a1] = clamp_mix( IIR_A1 >> 16 );
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//_spu2mem[dest2_b0] = clamp_mix( IIR_B0 >> 16 );
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//_spu2mem[dest2_b1] = clamp_mix( IIR_B1 >> 16 );
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/*const s32 IIR_A0 = (IIR_INPUT_A0 * thiscore.Revb.IIR_ALPHA) + (_spu2mem[dest_a0] * (0x7fff - thiscore.Revb.IIR_ALPHA));
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const s32 IIR_A1 = (IIR_INPUT_A1 * thiscore.Revb.IIR_ALPHA) + (_spu2mem[dest_a1] * (0x7fff - thiscore.Revb.IIR_ALPHA));
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const s32 IIR_B0 = (IIR_INPUT_B0 * thiscore.Revb.IIR_ALPHA) + (_spu2mem[dest_b0] * (0x7fff - thiscore.Revb.IIR_ALPHA));
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const s32 IIR_B1 = (IIR_INPUT_B1 * thiscore.Revb.IIR_ALPHA) + (_spu2mem[dest_b1] * (0x7fff - thiscore.Revb.IIR_ALPHA));
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_spu2mem[dest2_a0] = clamp_mix( IIR_A0 >> 16 );
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_spu2mem[dest2_a1] = clamp_mix( IIR_A1 >> 16 );
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_spu2mem[dest2_b0] = clamp_mix( IIR_B0 >> 16 );
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_spu2mem[dest2_b1] = clamp_mix( IIR_B1 >> 16 );*/
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// Faster single-mul approach to interpolation:
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const s32 IIR_A0 = IIR_INPUT_A0 + ((_spu2mem[dest_a0]-IIR_INPUT_A0) * thiscore.Revb.IIR_ALPHA)>>16;
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const s32 IIR_A1 = IIR_INPUT_A1 + ((_spu2mem[dest_a1]-IIR_INPUT_A1) * thiscore.Revb.IIR_ALPHA)>>16;
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const s32 IIR_B0 = IIR_INPUT_B0 + ((_spu2mem[dest_b0]-IIR_INPUT_B0) * thiscore.Revb.IIR_ALPHA)>>16;
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const s32 IIR_B1 = IIR_INPUT_B1 + ((_spu2mem[dest_b1]-IIR_INPUT_B1) * thiscore.Revb.IIR_ALPHA)>>16;
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const s32 IIR_A0 = IIR_INPUT_A0 + (((_spu2mem[dest_a0]-IIR_INPUT_A0) * thiscore.Revb.IIR_ALPHA)>>16);
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const s32 IIR_A1 = IIR_INPUT_A1 + (((_spu2mem[dest_a1]-IIR_INPUT_A1) * thiscore.Revb.IIR_ALPHA)>>16);
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const s32 IIR_B0 = IIR_INPUT_B0 + (((_spu2mem[dest_b0]-IIR_INPUT_B0) * thiscore.Revb.IIR_ALPHA)>>16);
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const s32 IIR_B1 = IIR_INPUT_B1 + (((_spu2mem[dest_b1]-IIR_INPUT_B1) * thiscore.Revb.IIR_ALPHA)>>16);
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_spu2mem[dest2_a0] = clamp_mix( IIR_A0 );
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_spu2mem[dest2_a1] = clamp_mix( IIR_A1 );
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@ -200,18 +200,18 @@ void V_Core::Reset()
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s32 V_Core::EffectsBufferIndexer( s32 offset ) const
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{
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u32 pos = EffectsStartA + ReverbX + offset;
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u32 pos = EffectsStartA + offset;
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// Need to use modulus here, because games can and will drop the buffer size
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// without notice, and it leads to offsets several times past the end of the buffer.
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if( pos > EffectsEndA )
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{
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pos = EffectsStartA + ((ReverbX + offset) % (u32)EffectsBufferSize);
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pos = EffectsStartA + (offset % EffectsBufferSize);
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}
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else if( pos < EffectsStartA )
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{
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pos = EffectsEndA+1 - ((ReverbX + offset) % (u32)EffectsBufferSize );
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pos = EffectsEndA+1 - (offset % EffectsBufferSize );
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}
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return pos;
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}
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@ -230,12 +230,11 @@ void V_Core::UpdateFeedbackBuffersB()
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void V_Core::UpdateEffectsBufferSize()
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{
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ReverbX = 0;
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const s32 newbufsize = EffectsEndA - EffectsStartA + 1;
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if( !RevBuffers.NeedsUpdated && newbufsize == EffectsBufferSize ) return;
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RevBuffers.NeedsUpdated = false;
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EffectsBufferSize = newbufsize;
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if( EffectsBufferSize == 0 ) return;
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@ -675,6 +674,7 @@ u16 SPU_ps1_read(u32 mem)
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{
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value = Cores[0].EffectsStartA>>3;
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Cores[0].UpdateEffectsBufferSize();
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Cores[0].ReverbX = 0;
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}
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break;
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case 0x1da4: value = Cores[0].IRQA>>3; break;
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@ -862,52 +862,53 @@ __forceinline void SPU2_FastWrite( u32 rmem, u16 value )
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}
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else
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{
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V_Core& thiscore = Cores[core];
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switch(omem)
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{
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case REG_C_ATTR:
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{
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int irqe = Cores[core].IRQEnable;
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int bit0 = Cores[core].AttrBit0;
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int bit4 = Cores[core].AttrBit4;
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int irqe = thiscore.IRQEnable;
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int bit0 = thiscore.AttrBit0;
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int bit4 = thiscore.AttrBit4;
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if( ((value>>15)&1) && (!Cores[core].CoreEnabled) && (Cores[core].InitDelay==0) ) // on init/reset
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if( ((value>>15)&1) && (!thiscore.CoreEnabled) && (thiscore.InitDelay==0) ) // on init/reset
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{
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if(hasPtr)
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{
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Cores[core].InitDelay=1;
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Cores[core].Regs.STATX=0;
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thiscore.InitDelay=1;
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thiscore.Regs.STATX=0;
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}
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else
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{
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Cores[core].Reset();
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thiscore.Reset();
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}
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}
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Cores[core].AttrBit0 =(value>> 0) & 0x01; //1 bit
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Cores[core].DMABits =(value>> 1) & 0x07; //3 bits
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Cores[core].AttrBit4 =(value>> 4) & 0x01; //1 bit
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Cores[core].AttrBit5 =(value>> 5) & 0x01; //1 bit
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Cores[core].IRQEnable =(value>> 6) & 0x01; //1 bit
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Cores[core].FxEnable =(value>> 7) & 0x01; //1 bit
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Cores[core].NoiseClk =(value>> 8) & 0x3f; //6 bits
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//Cores[core].Mute =(value>>14) & 0x01; //1 bit
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Cores[core].Mute=0;
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Cores[core].CoreEnabled=(value>>15) & 0x01; //1 bit
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Cores[core].Regs.ATTR =value&0x7fff;
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thiscore.AttrBit0 =(value>> 0) & 0x01; //1 bit
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thiscore.DMABits =(value>> 1) & 0x07; //3 bits
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thiscore.AttrBit4 =(value>> 4) & 0x01; //1 bit
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thiscore.AttrBit5 =(value>> 5) & 0x01; //1 bit
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thiscore.IRQEnable =(value>> 6) & 0x01; //1 bit
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thiscore.FxEnable =(value>> 7) & 0x01; //1 bit
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thiscore.NoiseClk =(value>> 8) & 0x3f; //6 bits
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//thiscore.Mute =(value>>14) & 0x01; //1 bit
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thiscore.Mute=0;
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thiscore.CoreEnabled=(value>>15) & 0x01; //1 bit
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thiscore.Regs.ATTR =value&0x7fff;
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if(value&0x000E)
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{
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ConLog(" * SPU2: Core %d ATTR unknown bits SET! value=%04x\n",core,value);
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}
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if(Cores[core].AttrBit0!=bit0)
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if(thiscore.AttrBit0!=bit0)
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{
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ConLog(" * SPU2: ATTR bit 0 set to %d\n",Cores[core].AttrBit0);
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ConLog(" * SPU2: ATTR bit 0 set to %d\n",thiscore.AttrBit0);
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}
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if(Cores[core].IRQEnable!=irqe)
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if(thiscore.IRQEnable!=irqe)
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{
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ConLog(" * SPU2: IRQ %s\n",((Cores[core].IRQEnable==0)?"disabled":"enabled"));
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if(!Cores[core].IRQEnable)
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ConLog(" * SPU2: IRQ %s\n",((thiscore.IRQEnable==0)?"disabled":"enabled"));
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if(!thiscore.IRQEnable)
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Spdif.Info=0;
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}
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@ -915,23 +916,23 @@ __forceinline void SPU2_FastWrite( u32 rmem, u16 value )
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break;
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case REG_S_PMON:
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vx=2; for (vc=1;vc<16;vc++) { Cores[core].Voices[vc].Modulated=(s8)((value & vx)/vx); vx<<=1; }
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SetLoWord( Cores[core].Regs.PMON, value );
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vx=2; for (vc=1;vc<16;vc++) { thiscore.Voices[vc].Modulated=(s8)((value & vx)/vx); vx<<=1; }
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SetLoWord( thiscore.Regs.PMON, value );
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break;
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case (REG_S_PMON + 2):
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vx=1; for (vc=16;vc<24;vc++) { Cores[core].Voices[vc].Modulated=(s8)((value & vx)/vx); vx<<=1; }
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SetHiWord( Cores[core].Regs.PMON, value );
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vx=1; for (vc=16;vc<24;vc++) { thiscore.Voices[vc].Modulated=(s8)((value & vx)/vx); vx<<=1; }
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SetHiWord( thiscore.Regs.PMON, value );
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break;
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case REG_S_NON:
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vx=1; for (vc=0;vc<16;vc++) { Cores[core].Voices[vc].Noise=(s8)((value & vx)/vx); vx<<=1; }
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SetLoWord( Cores[core].Regs.NON, value );
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vx=1; for (vc=0;vc<16;vc++) { thiscore.Voices[vc].Noise=(s8)((value & vx)/vx); vx<<=1; }
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SetLoWord( thiscore.Regs.NON, value );
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break;
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case (REG_S_NON + 2):
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vx=1; for (vc=16;vc<24;vc++) { Cores[core].Voices[vc].Noise=(s8)((value & vx)/vx); vx<<=1; }
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SetHiWord( Cores[core].Regs.NON, value );
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vx=1; for (vc=16;vc<24;vc++) { thiscore.Voices[vc].Noise=(s8)((value & vx)/vx); vx<<=1; }
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SetHiWord( thiscore.Regs.NON, value );
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break;
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// Games like to repeatedly write these regs over and over with the same value, hence
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@ -940,12 +941,12 @@ __forceinline void SPU2_FastWrite( u32 rmem, u16 value )
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{ \
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const uint start_bit = hiword ? 16 : 0; \
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const uint end_bit = hiword ? 24 : 16; \
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const u32 result = hiword ? SetHiWord( Cores[core].Regs.reg_out, value ) : SetLoWord( Cores[core].Regs.reg_out, value ); \
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if( result == Cores[core].Regs.reg_out ) return; \
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const u32 result = hiword ? SetHiWord( thiscore.Regs.reg_out, value ) : SetLoWord( thiscore.Regs.reg_out, value ); \
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if( result == thiscore.Regs.reg_out ) return; \
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\
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Cores[core].Regs.reg_out = result; \
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thiscore.Regs.reg_out = result; \
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for (uint vc=start_bit, vx=1; vc<end_bit; vc++, vx<<=1) \
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Cores[core].Voices[vc].mask_out = (value & vx) ? -1 : 0; \
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thiscore.Voices[vc].mask_out = (value & vx) ? -1 : 0; \
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}
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case REG_S_VMIXL:
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@ -987,19 +988,19 @@ __forceinline void SPU2_FastWrite( u32 rmem, u16 value )
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vx = value;
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if (core == 0) vx&=0xFF0;
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Cores[core].ExtWetR = (vx & 0x001) ? -1 : 0;
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Cores[core].ExtWetL = (vx & 0x002) ? -1 : 0;
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Cores[core].ExtDryR = (vx & 0x004) ? -1 : 0;
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Cores[core].ExtDryL = (vx & 0x008) ? -1 : 0;
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Cores[core].InpWetR = (vx & 0x010) ? -1 : 0;
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Cores[core].InpWetL = (vx & 0x020) ? -1 : 0;
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Cores[core].InpDryR = (vx & 0x040) ? -1 : 0;
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Cores[core].InpDryL = (vx & 0x080) ? -1 : 0;
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Cores[core].SndWetR = (vx & 0x100) ? -1 : 0;
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Cores[core].SndWetL = (vx & 0x200) ? -1 : 0;
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Cores[core].SndDryR = (vx & 0x400) ? -1 : 0;
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Cores[core].SndDryL = (vx & 0x800) ? -1 : 0;
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Cores[core].Regs.MMIX = value;
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thiscore.ExtWetR = (vx & 0x001) ? -1 : 0;
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thiscore.ExtWetL = (vx & 0x002) ? -1 : 0;
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thiscore.ExtDryR = (vx & 0x004) ? -1 : 0;
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thiscore.ExtDryL = (vx & 0x008) ? -1 : 0;
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thiscore.InpWetR = (vx & 0x010) ? -1 : 0;
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thiscore.InpWetL = (vx & 0x020) ? -1 : 0;
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thiscore.InpDryR = (vx & 0x040) ? -1 : 0;
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thiscore.InpDryL = (vx & 0x080) ? -1 : 0;
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thiscore.SndWetR = (vx & 0x100) ? -1 : 0;
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thiscore.SndWetL = (vx & 0x200) ? -1 : 0;
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thiscore.SndDryR = (vx & 0x400) ? -1 : 0;
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thiscore.SndDryL = (vx & 0x800) ? -1 : 0;
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thiscore.Regs.MMIX = value;
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break;
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case (REG_S_KON + 2):
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@ -1019,11 +1020,11 @@ __forceinline void SPU2_FastWrite( u32 rmem, u16 value )
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break;
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case REG_S_ENDX:
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Cores[core].Regs.ENDX&=0x00FF0000;
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thiscore.Regs.ENDX&=0x00FF0000;
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break;
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case (REG_S_ENDX + 2):
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Cores[core].Regs.ENDX&=0xFFFF;
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thiscore.Regs.ENDX&=0xFFFF;
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break;
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// Reverb Start and End Address Writes!
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@ -1034,18 +1035,21 @@ __forceinline void SPU2_FastWrite( u32 rmem, u16 value )
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// change the end address anyway.
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case REG_A_ESA:
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SetHiWord( Cores[core].EffectsStartA, value );
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Cores[core].UpdateEffectsBufferSize();
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SetHiWord( thiscore.EffectsStartA, value );
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thiscore.UpdateEffectsBufferSize();
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thiscore.ReverbX = 0;
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break;
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case (REG_A_ESA + 2):
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SetLoWord( Cores[core].EffectsStartA, value );
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Cores[core].UpdateEffectsBufferSize();
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SetLoWord( thiscore.EffectsStartA, value );
|
||||
thiscore.UpdateEffectsBufferSize();
|
||||
thiscore.ReverbX = 0;
|
||||
break;
|
||||
|
||||
case REG_A_EEA:
|
||||
Cores[core].EffectsEndA = ((u32)value<<16) | 0xFFFF;
|
||||
Cores[core].UpdateEffectsBufferSize();
|
||||
thiscore.EffectsEndA = ((u32)value<<16) | 0xFFFF;
|
||||
thiscore.UpdateEffectsBufferSize();
|
||||
thiscore.ReverbX = 0;
|
||||
break;
|
||||
|
||||
// Master Volume Address Write!
|
||||
|
|
@ -1053,7 +1057,7 @@ __forceinline void SPU2_FastWrite( u32 rmem, u16 value )
|
|||
case REG_P_MVOLL:
|
||||
case REG_P_MVOLR:
|
||||
{
|
||||
V_VolumeSlide& thisvol = (omem==REG_P_MVOLL) ? Cores[core].MasterVol.Left : Cores[core].MasterVol.Right;
|
||||
V_VolumeSlide& thisvol = (omem==REG_P_MVOLL) ? thiscore.MasterVol.Left : thiscore.MasterVol.Right;
|
||||
|
||||
if( value & 0x8000 ) // +Lin/-Lin/+Exp/-Exp
|
||||
{
|
||||
|
|
@ -1075,36 +1079,36 @@ __forceinline void SPU2_FastWrite( u32 rmem, u16 value )
|
|||
break;
|
||||
|
||||
case REG_P_EVOLL:
|
||||
Cores[core].FxVol.Left = GetVol32( value );
|
||||
thiscore.FxVol.Left = GetVol32( value );
|
||||
break;
|
||||
|
||||
case REG_P_EVOLR:
|
||||
Cores[core].FxVol.Right = GetVol32( value );
|
||||
thiscore.FxVol.Right = GetVol32( value );
|
||||
break;
|
||||
|
||||
case REG_P_AVOLL:
|
||||
Cores[core].ExtVol.Left = GetVol32( value );
|
||||
thiscore.ExtVol.Left = GetVol32( value );
|
||||
break;
|
||||
|
||||
case REG_P_AVOLR:
|
||||
Cores[core].ExtVol.Right = GetVol32( value );
|
||||
thiscore.ExtVol.Right = GetVol32( value );
|
||||
break;
|
||||
|
||||
case REG_P_BVOLL:
|
||||
Cores[core].InpVol.Left = GetVol32( value );
|
||||
thiscore.InpVol.Left = GetVol32( value );
|
||||
break;
|
||||
|
||||
case REG_P_BVOLR:
|
||||
Cores[core].InpVol.Right = GetVol32( value );
|
||||
thiscore.InpVol.Right = GetVol32( value );
|
||||
break;
|
||||
|
||||
case REG_S_ADMAS:
|
||||
//ConLog(" * SPU2: Core %d AutoDMAControl set to %d (%d)\n",core,value, Cycles);
|
||||
Cores[core].AutoDMACtrl=value;
|
||||
thiscore.AutoDMACtrl=value;
|
||||
|
||||
if(value==0)
|
||||
{
|
||||
Cores[core].AdmaInProgress=0;
|
||||
thiscore.AdmaInProgress=0;
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
|
|||
|
|
@ -144,9 +144,9 @@ public:
|
|||
memset(&wfx, 0, sizeof(WAVEFORMATEX));
|
||||
wfx.wFormatTag = WAVE_FORMAT_PCM;
|
||||
wfx.nSamplesPerSec = SampleRate;
|
||||
wfx.nChannels = speakerConfig;
|
||||
wfx.nChannels = (WORD)speakerConfig;
|
||||
wfx.wBitsPerSample = 16;
|
||||
wfx.nBlockAlign = 2*speakerConfig;
|
||||
wfx.nBlockAlign = 2*(WORD)speakerConfig;
|
||||
wfx.nAvgBytesPerSec = SampleRate * wfx.nBlockAlign;
|
||||
wfx.cbSize = 0;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue