mirror of https://github.com/PCSX2/pcsx2.git
microVU:
- Minor Changes/Cleanup Super VU: - Used the Linux SysMmapEx address for windows as well. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1308 96395faa-99c1-11dd-bbfe-3dabce05a288
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@ -343,12 +343,7 @@ void SuperVUAlloc(int vuindex)
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{
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// upper 4 bits must be zero!
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// Changed "first try base" to 0xb800000, since 0x0c000000 liked to fail a lot. (air)
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// With microVU as optional now, Linux fails with 0x0e000000, and prefers 0x0c000000. --arcum42
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#ifdef __LINUX__
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s_recVUMem = SysMmapEx(0x0c000000, VU_EXESIZE, 0x10000000, "SuperVUAlloc");
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#else
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s_recVUMem = SysMmapEx(0x0e000000, VU_EXESIZE, 0x10000000, "SuperVUAlloc");
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#endif
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if (s_recVUMem == NULL)
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{
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@ -116,7 +116,7 @@ struct microVU {
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u8* exitFunct; // Ptr Function to the Exit code for recompiled programs
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u32 code; // Contains the current Instruction
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u32 divFlag; // 1 instance of I/D flags
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u32 VIbackup[2]; // Holds a backup of a VI reg if modified before a branch
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u32 VIbackup; // Holds a backup of a VI reg if modified before a branch
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u32 VIxgkick; // Holds a backup of a VI reg used for xgkick-delays
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u32 branch; // Holds branch compare result (IBxx) OR Holds address to Jump to (JALR/JR)
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u32 p; // Holds current P instance index
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@ -687,10 +687,9 @@ microVUt(void) mVUallocVIa(mV, int GPRreg, int _reg_) {
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microVUt(void) mVUallocVIb(mV, int GPRreg, int _reg_) {
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if (mVUlow.backupVI) { // Backs up reg to memory (used when VI is modified b4 a branch)
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MOV32RtoM((uptr)&mVU->VIbackup[1], GPRreg);
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mVUallocVIa(mVU, GPRreg, _reg_);
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MOV32RtoM((uptr)&mVU->VIbackup[0], GPRreg);
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MOV32MtoR(GPRreg, (uptr)&mVU->VIbackup[1]);
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MOVZX32M16toR(gprR, (uptr)&mVU->regs->VI[_reg_].UL);
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MOV32RtoM((uptr)&mVU->VIbackup, gprR);
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MOV32ItoR(gprR, Roffset);
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}
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if (_reg_ == 0) { return; }
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else if (isMMX(_reg_)) { MOVD32RtoMMX(mmVI(_reg_), GPRreg); }
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@ -372,12 +372,12 @@ microVUt(void) mVUanalyzeXGkick(mV, int Fs, int xCycles) {
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#define analyzeBranchVI(xReg, infoVar) { \
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if (xReg) { \
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int i; \
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int iEnd = aMin(4, mVUcount); \
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int iEnd = aMin(5, mVUcount); \
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int bPC = iPC; \
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for (i = 0; i < iEnd; i++) { \
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incPC2(-2) \
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if ((mVUlow.VI_write.reg == xReg) && mVUlow.VI_write.used) { \
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if (mVUlow.readFlags) break; \
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if (mVUlow.readFlags || i == 5) break; \
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if (i == 0) continue; \
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if (((mVUlow.VI_read[0].reg == xReg) && (mVUlow.VI_read[0].used)) \
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|| ((mVUlow.VI_read[1].reg == xReg) && (mVUlow.VI_read[1].used))) \
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@ -402,6 +402,12 @@ microVUt(void) mVUanalyzeBranch1(mV, int Is) {
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}
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microVUt(void) mVUanalyzeBranch2(mV, int Is, int It) {
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if (mVUregs.VI[Is] || mVUregs.VI[It] || mVUstall) { analyzeVIreg1(Is, mVUlow.VI_read[0]); analyzeVIreg1(It, mVUlow.VI_read[1]); }
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else { analyzeBranchVI(Is, mVUlow.memReadIs); analyzeBranchVI(It, mVUlow.memReadIt);}
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if (mVUregs.VI[Is] || mVUregs.VI[It] || mVUstall) {
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analyzeVIreg1(Is, mVUlow.VI_read[0]);
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analyzeVIreg1(It, mVUlow.VI_read[1]);
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}
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else {
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analyzeBranchVI(Is, mVUlow.memReadIs);
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analyzeBranchVI(It, mVUlow.memReadIt);
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}
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}
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@ -98,7 +98,6 @@ struct microLowerOp {
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bool backupVI; // Backup VI reg to memory if modified before branch (branch uses old VI value unless opcode is ILW or ILWR)
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bool memReadIs; // Read Is (VI reg) from memory (used by branches)
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bool memReadIt; // Read If (VI reg) from memory (used by branches)
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bool writesVI; // Current Instruction writes to VI (used by branches; note that flag-modifying opcodes shouldn't set this)
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bool readFlags; // Current Instruction reads Status, Mac, or Clip flags
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};
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@ -1112,9 +1112,9 @@ mVUop(mVU_IBEQ) {
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setBranchA(3, 0);
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pass1 { mVUanalyzeBranch2(mVU, _Is_, _It_); }
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pass2 {
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if (mVUlow.memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup[0]);
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if (mVUlow.memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup);
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else mVUallocVIa(mVU, gprT1, _Is_);
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if (mVUlow.memReadIt) XOR32MtoR(gprT1, (uptr)&mVU->VIbackup[0]);
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if (mVUlow.memReadIt) XOR32MtoR(gprT1, (uptr)&mVU->VIbackup);
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else { mVUallocVIa(mVU, gprT2, _It_); XOR32RtoR(gprT1, gprT2); }
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MOV32RtoM((uptr)&mVU->branch, gprT1);
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}
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@ -1125,7 +1125,7 @@ mVUop(mVU_IBGEZ) {
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setBranchA(4, 0);
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pass1 { mVUanalyzeBranch1(mVU, _Is_); }
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pass2 {
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if (mVUlow.memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup[0]);
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if (mVUlow.memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup);
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else mVUallocVIa(mVU, gprT1, _Is_);
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MOV32RtoM((uptr)&mVU->branch, gprT1);
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}
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@ -1136,7 +1136,7 @@ mVUop(mVU_IBGTZ) {
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setBranchA(5, 0);
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pass1 { mVUanalyzeBranch1(mVU, _Is_); }
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pass2 {
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if (mVUlow.memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup[0]);
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if (mVUlow.memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup);
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else mVUallocVIa(mVU, gprT1, _Is_);
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MOV32RtoM((uptr)&mVU->branch, gprT1);
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}
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@ -1147,7 +1147,7 @@ mVUop(mVU_IBLEZ) {
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setBranchA(6, 0);
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pass1 { mVUanalyzeBranch1(mVU, _Is_); }
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pass2 {
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if (mVUlow.memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup[0]);
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if (mVUlow.memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup);
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else mVUallocVIa(mVU, gprT1, _Is_);
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MOV32RtoM((uptr)&mVU->branch, gprT1);
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}
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@ -1158,7 +1158,7 @@ mVUop(mVU_IBLTZ) {
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setBranchA(7, 0);
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pass1 { mVUanalyzeBranch1(mVU, _Is_); }
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pass2 {
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if (mVUlow.memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup[0]);
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if (mVUlow.memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup);
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else mVUallocVIa(mVU, gprT1, _Is_);
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MOV32RtoM((uptr)&mVU->branch, gprT1);
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}
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@ -1169,9 +1169,9 @@ mVUop(mVU_IBNE) {
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setBranchA(8, 0);
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pass1 { mVUanalyzeBranch2(mVU, _Is_, _It_); }
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pass2 {
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if (mVUlow.memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup[0]);
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if (mVUlow.memReadIs) MOV32MtoR(gprT1, (uptr)&mVU->VIbackup);
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else mVUallocVIa(mVU, gprT1, _Is_);
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if (mVUlow.memReadIt) XOR32MtoR(gprT1, (uptr)&mVU->VIbackup[0]);
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if (mVUlow.memReadIt) XOR32MtoR(gprT1, (uptr)&mVU->VIbackup);
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else { mVUallocVIa(mVU, gprT2, _It_); XOR32RtoR(gprT1, gprT2); }
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MOV32RtoM((uptr)&mVU->branch, gprT1);
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}
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