mirror of https://github.com/PCSX2/pcsx2.git
Debugger: Implement BC0XY branches & their condition evaluation
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@ -598,6 +598,12 @@ u32 R5900DebugInterface::getPC()
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return cpuRegs.pc;
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}
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// Taken from COP0.cpp
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bool R5900DebugInterface::getCPCOND0()
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{
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return (((dmacRegs.stat.CIS | ~dmacRegs.pcr.CPC) & 0x3FF) == 0x3ff);
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}
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void R5900DebugInterface::setPc(u32 newPc)
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{
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cpuRegs.pc = newPc;
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@ -945,6 +951,11 @@ u32 R3000DebugInterface::getPC()
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return psxRegs.pc;
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}
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bool R3000DebugInterface::getCPCOND0()
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{
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return false;
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}
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void R3000DebugInterface::setPc(u32 newPc)
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{
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psxRegs.pc = newPc;
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@ -77,6 +77,7 @@ public:
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virtual u128 getHI() = 0;
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virtual u128 getLO() = 0;
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virtual u32 getPC() = 0;
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virtual bool getCPCOND0() = 0;
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virtual void setPc(u32 newPc) = 0;
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virtual void setRegister(int cat, int num, u128 newValue) = 0;
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@ -129,6 +130,7 @@ public:
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u128 getHI() override;
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u128 getLO() override;
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u32 getPC() override;
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bool getCPCOND0() override;
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void setPc(u32 newPc) override;
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void setRegister(int cat, int num, u128 newValue) override;
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[[nodiscard]] SymbolMap& GetSymbolMap() const override;
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@ -168,6 +170,7 @@ public:
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u128 getHI() override;
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u128 getLO() override;
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u32 getPC() override;
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bool getCPCOND0() override;
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void setPc(u32 newPc) override;
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void setRegister(int cat, int num, u128 newValue) override;
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[[nodiscard]] SymbolMap& GetSymbolMap() const override;
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@ -59,7 +59,7 @@ namespace MIPSAnalyst
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const R5900::OPCODE& opcode = R5900::GetInstruction(op);
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int branchType = (opcode.flags & BRANCHTYPE_MASK);
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if ((opcode.flags & IS_BRANCH) && (branchType == BRANCHTYPE_BRANCH || branchType == BRANCHTYPE_BC1))
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if ((opcode.flags & IS_BRANCH) && (branchType == BRANCHTYPE_BRANCH || branchType == BRANCHTYPE_BC1 || branchType == BRANCHTYPE_BC0))
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return addr + 4 + ((signed short)(op&0xFFFF)<<2);
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else
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return INVALIDTARGET;
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@ -71,7 +71,7 @@ namespace MIPSAnalyst
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const R5900::OPCODE& opcode = R5900::GetInstruction(op);
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int branchType = (opcode.flags & BRANCHTYPE_MASK);
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if ((opcode.flags & IS_BRANCH) && (branchType == BRANCHTYPE_BRANCH || branchType == BRANCHTYPE_BC1))
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if ((opcode.flags & IS_BRANCH) && (branchType == BRANCHTYPE_BRANCH || branchType == BRANCHTYPE_BC1 || branchType == BRANCHTYPE_BC0))
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{
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if (!(opcode.flags & IS_LINKED))
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return addr + 4 + ((signed short)(op&0xFFFF)<<2);
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@ -409,6 +409,20 @@ namespace MIPSAnalyst
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value = info.cpu->getRegister(EECAT_FCR,31)._u32[0] & 0x00800000;
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info.branchTarget = info.opcodeAddress + 4 + ((s16)(op&0xFFFF)<<2);
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switch (opcode.flags & CONDTYPE_MASK)
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{
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case CONDTYPE_EQ:
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info.conditionMet = value == 0;
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break;
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case CONDTYPE_NE:
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info.conditionMet = value != 0;
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break;
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}
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break;
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case BRANCHTYPE_BC0:
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info.isConditional = true;
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value = info.cpu->getCPCOND0();
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info.branchTarget = info.opcodeAddress + 4 + ((s16)(op&0xFFFF)<<2);
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switch (opcode.flags & CONDTYPE_MASK)
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{
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case CONDTYPE_EQ:
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@ -394,10 +394,10 @@ namespace R5900
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MakeOpcode0( MFC0, CopDefault, 0 );
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MakeOpcode0( MTC0, CopDefault, 0 );
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MakeOpcode0( BC0F, Branch, 0 );
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MakeOpcode0( BC0T, Branch, 0 );
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MakeOpcode0( BC0FL, Branch, 0 );
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MakeOpcode0( BC0TL, Branch, 0 );
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MakeOpcode0(BC0F, Branch, IS_BRANCH | BRANCHTYPE_BC0 | CONDTYPE_EQ);
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MakeOpcode0(BC0T, Branch, IS_BRANCH | BRANCHTYPE_BC0 | CONDTYPE_NE);
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MakeOpcode0(BC0FL, Branch, IS_BRANCH | BRANCHTYPE_BC0 | CONDTYPE_EQ | IS_LIKELY);
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MakeOpcode0(BC0TL, Branch, IS_BRANCH | BRANCHTYPE_BC0 | CONDTYPE_NE | IS_LIKELY);
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MakeOpcode0( TLBR, CopDefault, 0 );
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MakeOpcode0( TLBWI, CopDefault, 0 );
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@ -61,13 +61,14 @@ void COP2_Unknown();
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#define CONDTYPE_LTZ (0x05 << 0)
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#define CONDTYPE_GEZ (0x06 << 0)
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#define BRANCHTYPE_MASK (0x07 << 3)
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#define BRANCHTYPE_MASK (0x0F << 3)
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#define BRANCHTYPE_JUMP (0x01 << 3)
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#define BRANCHTYPE_BRANCH (0x02 << 3)
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#define BRANCHTYPE_SYSCALL (0x03 << 3)
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#define BRANCHTYPE_ERET (0x04 << 3)
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#define BRANCHTYPE_REGISTER (0x05 << 3)
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#define BRANCHTYPE_BC1 (0x06 << 3)
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#define BRANCHTYPE_BC0 (0x08 << 3)
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#define ALUTYPE_MASK (0x07 << 3)
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#define ALUTYPE_ADD (0x01 << 3)
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