mirror of https://github.com/PCSX2/pcsx2.git
x86emitter: remove the never called SIMD_ExceptionTest function
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a026a1979f
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@ -114,7 +114,6 @@ public:
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u32 CalculateMHz() const;
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void SIMD_ExceptionTest();
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void SIMD_EstablishMXCSRmask();
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protected:
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@ -35,18 +35,6 @@ bool CanEmitShit()
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return true;
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}
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bool CanTestInstructionSets()
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{
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// Not implemented yet for linux. (see cpudetect_internal.h for details)
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return false;
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}
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bool _test_instruction( void* pfnCall )
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{
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// Not implemented yet for linux. (see cpudetect_internal.h for details)
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return false;
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}
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// Not implemented yet for linux (see cpudetect_internal.h for details)
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SingleCoreAffinity::SingleCoreAffinity() {}
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SingleCoreAffinity::~SingleCoreAffinity() throw() {}
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@ -39,17 +39,6 @@ void x86capabilities::CountLogicalCores()
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LogicalCores = CPUs;
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}
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bool _test_instruction( void* pfnCall )
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{
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__try {
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u128 regsave;
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((void (__fastcall *)(void*))pfnCall)( ®save );
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}
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__except(EXCEPTION_EXECUTE_HANDLER) { return false; }
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return true;
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}
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bool CanEmitShit()
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{
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// Under Windows, pre 0.9.6 versions of PCSX2 may not initialize the TLS
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@ -65,11 +54,6 @@ bool CanEmitShit()
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return true;
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}
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bool CanTestInstructionSets()
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{
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return CanEmitShit();
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}
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SingleCoreAffinity::SingleCoreAffinity()
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{
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s_threadId = NULL;
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@ -25,11 +25,6 @@ __aligned16 x86capabilities x86caps;
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static __pagealigned u8 recSSE[__pagesize];
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static __pagealigned u8 targetFXSAVE[512];
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#ifdef __linux__
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# include <sys/time.h>
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# include <errno.h>
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#endif
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static const char* bool_to_char( bool testcond )
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{
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return testcond ? "true" : "false";
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@ -322,77 +317,3 @@ u32 x86capabilities::CalculateMHz() const
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else
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return (u32)( _CPUSpeedHz( span / 500 ) / 2000 );
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}
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// Special extended version of SIMD testning, which uses exceptions to double-check the presence
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// of SSE2/3/4 instructions. Useful if you don't trust cpuid (at least one report of an invalid
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// cpuid has been reported on a Core2 Quad -- the user fixed it by clearing his CMOS).
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//
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// Results of CPU
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void x86capabilities::SIMD_ExceptionTest()
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{
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HostSys::MemProtectStatic( recSSE, PageAccess_ReadWrite() );
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//////////////////////////////////////////////////////////////////////////////////////////
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// SIMD Instruction Support Detection (Second Pass)
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//
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if( CanTestInstructionSets() )
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{
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xSetPtr( recSSE );
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xMOVDQU( ptr[ecx], xmm1 );
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xMOVSLDUP( xmm1, xmm0 );
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xMOVDQU( xmm1, ptr[ecx] );
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xRET();
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u8* funcSSSE3 = xGetPtr();
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xMOVDQU( ptr[ecx], xmm1 );
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xPABS.W( xmm1, xmm0 );
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xMOVDQU( xmm1, ptr[ecx] );
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xRET();
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u8* funcSSE41 = xGetPtr();
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xMOVDQU( ptr[ecx], xmm1 );
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xBLEND.VPD( xmm1, xmm0 );
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xMOVDQU( xmm1, ptr[ecx] );
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xRET();
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HostSys::MemProtectStatic( recSSE, PageAccess_ExecOnly() );
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bool sse3_result = _test_instruction( recSSE ); // sse3
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bool ssse3_result = _test_instruction( funcSSSE3 );
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bool sse41_result = _test_instruction( funcSSE41 );
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// Test for and log any irregularities here.
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// We take the instruction test result over cpuid since (in theory) it should be a
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// more reliable gauge of the cpu's actual ability. But since a difference in bit
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// and actual ability may represent a cmos/bios problem, we report it to the user.
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if( sse3_result != !!hasStreamingSIMD3Extensions )
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{
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Console.Warning( "SSE3 Detection Inconsistency: cpuid=%s, test_result=%s",
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bool_to_char( !!hasStreamingSIMD3Extensions ), bool_to_char( sse3_result ) );
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hasStreamingSIMD3Extensions = sse3_result;
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}
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if( ssse3_result != !!hasSupplementalStreamingSIMD3Extensions )
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{
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Console.Warning( "SSSE3 Detection Inconsistency: cpuid=%s, test_result=%s",
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bool_to_char( !!hasSupplementalStreamingSIMD3Extensions ), bool_to_char( ssse3_result ) );
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hasSupplementalStreamingSIMD3Extensions = ssse3_result;
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}
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if( sse41_result != !!hasStreamingSIMD4Extensions )
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{
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Console.Warning( "SSE4 Detection Inconsistency: cpuid=%s, test_result=%s",
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bool_to_char( !!hasStreamingSIMD4Extensions ), bool_to_char( sse41_result ) );
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hasStreamingSIMD4Extensions = sse41_result;
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}
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}
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SIMD_EstablishMXCSRmask();
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}
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@ -52,5 +52,3 @@ public:
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//
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extern bool CanEmitShit();
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extern bool CanTestInstructionSets();
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extern bool _test_instruction( void* pfnCall );
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