diff --git a/pcsx2/x86/microVU.cpp b/pcsx2/x86/microVU.cpp index cd96ba9259..2c4911bfd1 100644 --- a/pcsx2/x86/microVU.cpp +++ b/pcsx2/x86/microVU.cpp @@ -169,8 +169,9 @@ __forceinline int mVUfindLeastUsedProg(microVU* mVU) { __forceinline int mVUsearchProg(microVU* mVU) { if (mVU->prog.cleared) { // If cleared, we need to search for new program for (int i = 0; i <= mVU->prog.total; i++) { - if (i == mVU->prog.cur) continue; // We can skip the current program. (ToDo: Verify that games don't clear, and send the same microprogram :/) + //if (i == mVU->prog.cur) continue; // We can skip the current program. (ToDo: Verify that games don't clear, and send the same microprogram :/) if (!memcmp_mmx(mVU->prog.prog[i].data, mVU->regs->Micro, mVU->microSize)) { + if (i == mVU->prog.cur) SysPrintf("microVU: Same micro program sent!\n"); mVU->prog.cur = i; mVU->prog.cleared = 0; mVU->prog.prog[i].used++; diff --git a/pcsx2/x86/microVU_Alloc.inl b/pcsx2/x86/microVU_Alloc.inl index ccd8a9221c..590a6429f1 100644 --- a/pcsx2/x86/microVU_Alloc.inl +++ b/pcsx2/x86/microVU_Alloc.inl @@ -23,6 +23,76 @@ // Micro VU - recPass 0 Functions //------------------------------------------------------------------ +//------------------------------------------------------------------ +// FMAC1 - Normal FMAC Opcodes +//------------------------------------------------------------------ + +#define aReg(x) mVUallocInfo.regs.VF[x] +#define aMax(x, y) ((x > y) ? x : y) + +#define analyzeReg1(reg) { \ + if (reg) { \ + if (_X) { mVal = aMax(mVal, aReg(reg).x); } \ + if (_Y) { mVal = aMax(mVal, aReg(reg).y); } \ + if (_Z) { mVal = aMax(mVal, aReg(reg).z); } \ + if (_W) { mVal = aMax(mVal, aReg(reg).w); } \ + } \ +} + +#define analyzeReg2(reg) { \ + if (reg) { \ + if (_X) { aReg(reg).x = 4; } \ + if (_Y) { aReg(reg).y = 4; } \ + if (_Z) { aReg(reg).z = 4; } \ + if (_W) { aReg(reg).w = 4; } \ + } \ +} + +microVUt(void) mVUanalyzeFMAC1(int Fd, int Fs, int Ft) { + microVU* mVU = mVUx; + int mVal = 0; + mVUinfo |= _doStatus; + analyzeReg1(Fs); + analyzeReg1(Ft); + incCycles(mVal); + analyzeReg2(Fd); +} + +//------------------------------------------------------------------ +// FMAC2 - ABS/FTOI/ITOF Opcodes +//------------------------------------------------------------------ + +microVUt(void) mVUanalyzeFMAC2(int Fs, int Ft) { + microVU* mVU = mVUx; + int mVal = 0; + analyzeReg1(Fs); + incCycles(mVal); + analyzeReg2(Ft); +} + +//------------------------------------------------------------------ +// FMAC3 - BC(xyzw) FMAC Opcodes +//------------------------------------------------------------------ + +#define analyzeReg3(reg) { \ + if (reg) { \ + if (_bc_x) { mVal = aMax(mVal, aReg(reg).x); } \ + else if (_bc_y) { mVal = aMax(mVal, aReg(reg).y); } \ + else if (_bc_z) { mVal = aMax(mVal, aReg(reg).z); } \ + else { mVal = aMax(mVal, aReg(reg).w); } \ + } \ +} + +microVUt(void) mVUanalyzeFMAC3(int Fd, int Fs, int Ft) { + microVU* mVU = mVUx; + int mVal = 0; + mVUinfo |= _doStatus; + analyzeReg1(Fs); + analyzeReg3(Ft); + incCycles(mVal); + analyzeReg2(Fd); +} + //------------------------------------------------------------------ // Micro VU - recPass 1 Functions //------------------------------------------------------------------ @@ -146,12 +216,7 @@ microVUt(void) mVUallocFMAC3b(int& Fd) { if (_W) { mVUloadReg(reg, (uptr)&mVU->regs->VF[0].UL[0], _xyzw_ACC); } \ else { SSE_XORPS_XMM_to_XMM(reg, reg); } \ } -/* -#define getACC(reg) { \ - reg = xmmACC0 + writeACC; \ - if (_X_Y_Z_W != 15) { SSE_MOVAPS_XMM_to_XMM(reg, (xmmACC0 + prevACC)); } \ -} -*/ + microVUt(void) mVUallocFMAC4a(int& ACC, int& Fs, int& Ft) { microVU* mVU = mVUx; ACC = xmmACC; diff --git a/pcsx2/x86/microVU_Misc.h b/pcsx2/x86/microVU_Misc.h index 47558d2d3c..65d8054d67 100644 --- a/pcsx2/x86/microVU_Misc.h +++ b/pcsx2/x86/microVU_Misc.h @@ -79,11 +79,11 @@ declareAllVariables #define _X_Y_Z_W (((mVU->code >> 21 ) & 0xF )) #define _xyzw_ACC ((_XYZW_SS && !_X) ? 15 : _X_Y_Z_W) -#define _bc_ (mVU->code & 0x03) -#define _bc_x ((mVU->code & 0x03) == 0) -#define _bc_y ((mVU->code & 0x03) == 1) -#define _bc_z ((mVU->code & 0x03) == 2) -#define _bc_w ((mVU->code & 0x03) == 3) +#define _bc_ (mVU->code & 0x3) +#define _bc_x ((mVU->code & 0x3) == 0) +#define _bc_y ((mVU->code & 0x3) == 1) +#define _bc_z ((mVU->code & 0x3) == 2) +#define _bc_w ((mVU->code & 0x3) == 3) #define _Fsf_ ((mVU->code >> 21) & 0x03) #define _Ftf_ ((mVU->code >> 23) & 0x03) @@ -142,9 +142,11 @@ declareAllVariables #define mVUblock mVU->prog.prog[mVU->prog.cur].block #define mVUallocInfo mVU->prog.prog[mVU->prog.cur].allocInfo #define mVUbranch mVUallocInfo.branch +#define mVUcycles mVUallocInfo.cycles #define mVUinfo mVUallocInfo.info[mVUallocInfo.curPC / 2] #define iPC mVUallocInfo.curPC #define xPC ((iPC / 2) * 8) +#define incCycles(x) { mVUcycles += x; } #define _isNOP (1<<0) // Skip Lower Instruction #define _isBranch (1<<1) // Cur Instruction is a Branch diff --git a/pcsx2/x86/microVU_Upper.inl b/pcsx2/x86/microVU_Upper.inl index df8e7aa406..f1939370ff 100644 --- a/pcsx2/x86/microVU_Upper.inl +++ b/pcsx2/x86/microVU_Upper.inl @@ -81,7 +81,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC1 - Normal FMAC Opcodes #define mVU_FMAC1(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC1(_Fd_, _Fs_, _Ft_); } \ else { \ int Fd, Fs, Ft; \ mVUallocFMAC1a(Fd, Fs, Ft); \ @@ -94,7 +94,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC3 - BC(xyzw) FMAC Opcodes #define mVU_FMAC3(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC3(_Fd_, _Fs_, _Ft_); } \ else { \ int Fd, Fs, Ft; \ mVUallocFMAC3a(Fd, Fs, Ft); \ @@ -107,7 +107,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC4 - FMAC Opcodes Storing Result to ACC #define mVU_FMAC4(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC1(0, _Fs_, _Ft_); } \ else { \ int ACC, Fs, Ft; \ mVUallocFMAC4a(ACC, Fs, Ft); \ @@ -120,11 +120,11 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC5 - FMAC BC(xyzw) Opcodes Storing Result to ACC #define mVU_FMAC5(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC3(0, _Fs_, _Ft_); } \ else { \ int ACC, Fs, Ft; \ mVUallocFMAC5a(ACC, Fs, Ft); \ - if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ + if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ mVUupdateFlags(Fs, xmmT1, Ft, _X_Y_Z_W, 0); \ mVUallocFMAC5b(ACC, Fs); \ @@ -133,7 +133,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC6 - Normal FMAC Opcodes (I Reg) #define mVU_FMAC6(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC1(_Fd_, _Fs_, 0); } \ else { \ int Fd, Fs, Ft; \ mVUallocFMAC6a(Fd, Fs, Ft); \ @@ -146,11 +146,11 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC7 - FMAC Opcodes Storing Result to ACC (I Reg) #define mVU_FMAC7(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC1(0, _Fs_, 0); } \ else { \ int ACC, Fs, Ft; \ mVUallocFMAC7a(ACC, Fs, Ft); \ - if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ + if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ mVUupdateFlags(Fs, xmmT1, Ft, _X_Y_Z_W, 0); \ mVUallocFMAC7b(ACC, Fs); \ @@ -159,7 +159,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC8 - MADD FMAC Opcode Storing Result to Fd #define mVU_FMAC8(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC1(_Fd_, _Fs_, _Ft_); } \ else { \ int Fd, ACC, Fs, Ft; \ mVUallocFMAC8a(Fd, ACC, Fs, Ft); \ @@ -178,7 +178,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC9 - MSUB FMAC Opcode Storing Result to Fd #define mVU_FMAC9(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC1(_Fd_, _Fs_, _Ft_); } \ else { \ int Fd, ACC, Fs, Ft; \ mVUallocFMAC9a(Fd, ACC, Fs, Ft); \ @@ -197,7 +197,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC10 - MADD FMAC BC(xyzw) Opcode Storing Result to Fd #define mVU_FMAC10(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC3(_Fd_, _Fs_, _Ft_); } \ else { \ int Fd, ACC, Fs, Ft; \ mVUallocFMAC10a(Fd, ACC, Fs, Ft); \ @@ -216,7 +216,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC11 - MSUB FMAC BC(xyzw) Opcode Storing Result to Fd #define mVU_FMAC11(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC3(_Fd_, _Fs_, _Ft_); } \ else { \ int Fd, ACC, Fs, Ft; \ mVUallocFMAC11a(Fd, ACC, Fs, Ft); \ @@ -235,7 +235,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC12 - MADD FMAC Opcode Storing Result to Fd (I Reg) #define mVU_FMAC12(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC1(_Fd_, _Fs_, 0); } \ else { \ int Fd, ACC, Fs, Ft; \ mVUallocFMAC12a(Fd, ACC, Fs, Ft); \ @@ -254,7 +254,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC13 - MSUB FMAC Opcode Storing Result to Fd (I Reg) #define mVU_FMAC13(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC1(_Fd_, _Fs_, 0); } \ else { \ int Fd, ACC, Fs, Ft; \ mVUallocFMAC13a(Fd, ACC, Fs, Ft); \ @@ -273,7 +273,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC14 - MADDA/MSUBA FMAC Opcode #define mVU_FMAC14(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC1(0, _Fs_, _Ft_); } \ else { \ int ACCw, ACCr, Fs, Ft; \ mVUallocFMAC14a(ACCw, ACCr, Fs, Ft); \ @@ -292,7 +292,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC15 - MADDA/MSUBA BC(xyzw) FMAC Opcode #define mVU_FMAC15(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC3(0, _Fs_, _Ft_); } \ else { \ int ACCw, ACCr, Fs, Ft; \ mVUallocFMAC15a(ACCw, ACCr, Fs, Ft); \ @@ -311,7 +311,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC16 - MADDA/MSUBA FMAC Opcode (I Reg) #define mVU_FMAC16(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC1(0, _Fs_, 0); } \ else { \ int ACCw, ACCr, Fs, Ft; \ mVUallocFMAC16a(ACCw, ACCr, Fs, Ft); \ @@ -330,7 +330,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC18 - OPMULA FMAC Opcode #define mVU_FMAC18(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC1(0, _Fs_, _Ft_); } \ else { \ int ACC, Fs, Ft; \ mVUallocFMAC18a(ACC, Fs, Ft); \ @@ -342,7 +342,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC19 - OPMULA FMAC Opcode #define mVU_FMAC19(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC1(_Fd_, _Fs_, _Ft_); } \ else { \ int Fd, ACC, Fs, Ft; \ mVUallocFMAC19a(Fd, ACC, Fs, Ft); \ @@ -355,7 +355,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC22 - Normal FMAC Opcodes (Q Reg) #define mVU_FMAC22(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC1(_Fd_, _Fs_, 0); } \ else { \ int Fd, Fs, Ft; \ mVUallocFMAC22a(Fd, Fs, Ft); \ @@ -368,7 +368,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC23 - FMAC Opcodes Storing Result to ACC (Q Reg) #define mVU_FMAC23(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC1(0, _Fs_, 0); } \ else { \ int ACC, Fs, Ft; \ mVUallocFMAC23a(ACC, Fs, Ft); \ @@ -381,7 +381,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC24 - MADD FMAC Opcode Storing Result to Fd (Q Reg) #define mVU_FMAC24(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC1(_Fd_, _Fs_, 0); } \ else { \ int Fd, ACC, Fs, Ft; \ mVUallocFMAC24a(Fd, ACC, Fs, Ft); \ @@ -400,7 +400,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC25 - MSUB FMAC Opcode Storing Result to Fd (Q Reg) #define mVU_FMAC25(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC1(_Fd_, _Fs_, 0); } \ else { \ int Fd, ACC, Fs, Ft; \ mVUallocFMAC25a(Fd, ACC, Fs, Ft); \ @@ -419,7 +419,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX // FMAC26 - MADDA/MSUBA FMAC Opcode (Q Reg) #define mVU_FMAC26(operation) { \ microVU* mVU = mVUx; \ - if (recPass == 0) {} \ + if (!recPass) { mVUanalyzeFMAC1(0, _Fs_, 0); } \ else { \ int ACCw, ACCr, Fs, Ft; \ mVUallocFMAC26a(ACCw, ACCr, Fs, Ft); \ @@ -442,7 +442,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX microVUf(void) mVU_ABS() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) { mVUanalyzeFMAC2(_Fs_, _Ft_); } else { int Fs, Ft; mVUallocFMAC2a(Fs, Ft); @@ -536,12 +536,12 @@ microVUf(void) mVU_OPMULA() { mVU_FMAC18(MUL); } microVUf(void) mVU_OPMSUB() { mVU_FMAC19(SUB); } microVUf(void) mVU_NOP() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else {} } microVUq(void) mVU_FTOIx(uptr addr) { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) { mVUanalyzeFMAC2(_Fs_, _Ft_); } else { int Fs, Ft; mVUallocFMAC2a(Fs, Ft); @@ -557,7 +557,7 @@ microVUq(void) mVU_FTOIx(uptr addr) { SSE_ANDPS_XMM_to_XMM(xmmT1, xmmFt); SSE2_PADDD_XMM_to_XMM(Fs, xmmT1); - mVUallocFMAC1b(Ft); + mVUallocFMAC2b(Ft); } } microVUf(void) mVU_FTOI0() { mVU_FTOIx(0); } @@ -566,16 +566,16 @@ microVUf(void) mVU_FTOI12() { mVU_FTOIx((uptr)mVU_FTOI_12); } microVUf(void) mVU_FTOI15() { mVU_FTOIx((uptr)mVU_FTOI_15); } microVUq(void) mVU_ITOFx(uptr addr) { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) { mVUanalyzeFMAC2(_Fs_, _Ft_); } else { int Fs, Ft; mVUallocFMAC2a(Fs, Ft); SSE2_CVTDQ2PS_XMM_to_XMM(Ft, Fs); if (addr) { SSE_MULPS_M128_to_XMM(Ft, addr); } - //mVUclamp2(Ft, xmmT1, 15); // Clamp infinities (not sure if this is needed) + //mVUclamp2(Ft, xmmT1, 15); // Clamp (not sure if this is needed) - mVUallocFMAC1b(Ft); + mVUallocFMAC2b(Ft); } } microVUf(void) mVU_ITOF0() { mVU_ITOFx(0); }