microVU:

* Removed a DevCon from one of the mVU dispatchers and replaced it with an assertion (minor speedup for Release builds).
 * minor refactoring, encouraging mVU toward using class members and away from using quite so many macros.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3648 96395faa-99c1-11dd-bbfe-3dabce05a288

pcsx2/x86/microVU.h

@@ -176,9 +176,9 @@ struct microVU {
 	u32 cacheSize;		// VU Cache Size
 
 	microProgManager prog;		// Micro Program Data
-	microRegAlloc*	 regAlloc;	// Reg Alloc Class
+	ScopedPtr<microRegAlloc>	regAlloc;	// Reg Alloc Class
+	ScopedPtr<AsciiFile>		logFile;	// Log File Pointer
 
-	AsciiFile* logFile;	 // Log File Pointer
 	VURegs*	regs;		 // VU Regs Struct
 	u8*		cache;		 // Dynarec Cache Start (where we will start writing the recompiled code to)
 	u8*		dispCache;	 // Dispatchers Cache (where startFunct and exitFunct are written to)
@@ -195,6 +195,33 @@ struct microVU {
 	u32		q;			 // Holds current Q instance index
 	u32		totalCycles; // Total Cycles that mVU is expected to run for
 	u32		cycles;		 // Cycles Counter
+
+	__fi s16 Imm5() const	{ return ((code & 0x400) ? 0xfff0 : 0) | ((code >> 6) & 0xf); }
+	__fi s32 Imm11() const	{ return (code & 0x400) ? (0xfffffc00 | (code & 0x3ff)) : (code & 0x3ff); }
+	__fi u32 Imm12() const	{ return (((code >> 21) & 0x1) << 11) | (code & 0x7ff); }
+	__fi u32 Imm15() const	{ return ((code >> 10) & 0x7800) | (code & 0x7ff); }
+	__fi u32 Imm24() const	{ return code & 0xffffff; }
+
+	// Fetches the PC and instruction opcode relative to the current PC.  Used to rewind and
+	// fast-forward the IR state while calculating VU pipeline conditions (branches, writebacks, etc)
+	__fi void advancePC( int x )
+	{
+		prog.IRinfo.curPC += x;
+		prog.IRinfo.curPC &= progMemMask;
+		code = ((u32*)regs->Micro)[prog.IRinfo.curPC];
+	}
+	
+	__ri uint getBranchAddr() const
+	{
+		pxAssumeDev((prog.IRinfo.curPC & 1) == 0, "microVU recompiler: Upper instructions cannot have valid branch addresses.");
+		return (((prog.IRinfo.curPC + 2)  + (Imm11() * 2)) & progMemMask) * 4;
+	}
+
+	__ri uint getBranchAddrN() const
+	{
+		pxAssumeDev((prog.IRinfo.curPC & 1) == 0, "microVU recompiler: Upper instructions cannot have valid branch addresses.");
+		return (((prog.IRinfo.curPC + 4)  + (Imm11() * 2)) & progMemMask) * 4;
+	}
 };
 
 // microVU rec structs

pcsx2/x86/microVU_Branch.inl

@@ -177,7 +177,7 @@ void condBranch(mV, microFlagCycles& mFC, int JMPcc) {
 void normJump(mV, microFlagCycles& mFC) {
 	if (mVUlow.constJump.isValid) { // Jump Address is Constant
 		if (mVUup.eBit) { // E-bit Jump
-			iPC = (mVUlow.constJump.regValue*2)&(mVU->progSize-1);
+			iPC = (mVUlow.constJump.regValue*2) & (mVU->progMemMask);
 			mVUendProgram(mVU, &mFC, 1);
 			return;
 		}

pcsx2/x86/microVU_Compile.inl

@@ -475,7 +475,8 @@ static __fi void* mVUentryGet(microVU* mVU, microBlockManager* block, u32 startP
  // Search for Existing Compiled Block (if found, return x86ptr; else, compile and return x86ptr)
 static __fi void* mVUblockFetch(microVU* mVU, u32 startPC, uptr pState) {
 
-	if (startPC > mVU->microMemSize-8) { DevCon.Error("microVU%d: invalid startPC [%04x]", mVU->index, startPC); }
+	pxAssumeDev( (startPC & 7) == 0,			pxsFmt("microVU%d: unaligned startPC=0x%04x", mVU->index, startPC) );
+	pxAssumeDev( startPC < mVU->microMemSize-8,	pxsFmt("microVU%d: invalid startPC=0x%04x", mVU->index, startPC) );
 	startPC    &= mVU->microMemSize-8;
 
 	blockCreate(startPC/8);

pcsx2/x86/microVU_Log.inl

@@ -118,10 +118,11 @@ _mVUt void __mVUdumpProgram(microProgram& prog) {
 	mVUlog("</body>\n");
 	mVUlog("</html>\n");
 
-	safe_delete( mVU->logFile );
-
 	mVUbranch = bBranch;
 	mVU->code = bCode;
 	iPC		  = bPC;
 	setCode();
+
+	mVU->logFile.Delete();
 }
+

pcsx2/x86/microVU_Misc.h

@@ -71,11 +71,19 @@ extern const __aligned(32) mVU_Globals mVUglob;
 #define _Fsf_	((mVU->code >> 21) & 0x03)
 #define _Ftf_	((mVU->code >> 23) & 0x03)
 
+#if 0
 #define _Imm5_	(s16)(((mVU->code & 0x400) ? 0xfff0 : 0) | ((mVU->code >> 6) & 0xf))
 #define _Imm11_	(s32)((mVU->code & 0x400) ? (0xfffffc00 | (mVU->code & 0x3ff)) : (mVU->code & 0x3ff))
 #define _Imm12_	(((mVU->code >> 21) & 0x1) << 11) | (mVU->code & 0x7ff)
 #define _Imm15_	(((mVU->code >> 10) & 0x7800) | (mVU->code & 0x7ff))
 #define _Imm24_	(u32)(mVU->code & 0xffffff)
+#else
+#define _Imm5_	(mVU->Imm5())
+#define _Imm11_	(mVU->Imm11())
+#define _Imm12_	(mVU->Imm12())
+#define _Imm15_	(mVU->Imm15())
+#define _Imm24_	(mVU->Imm24())
+#endif
 
 #define _Ibit_ (1<<31)
 #define _Ebit_ (1<<30)
@@ -199,11 +207,19 @@ typedef u32 (__fastcall *mVUCall)(void*, void*);
 #define xPC			 ((iPC / 2) * 8)
 #define curI		 ((u32*)mVU->regs->Micro)[iPC] //mVUcurProg.data[iPC]
 #define setCode()	 { mVU->code = curI; }
+
+#if 0
 #define incPC(x)	 { iPC = ((iPC + (x)) & (mVU->progSize-1)); setCode(); }
-#define incPC2(x)	 { iPC = ((iPC + (x)) & (mVU->progSize-1)); }
-#define bSaveAddr	 (((xPC + 16) & (mVU->microMemSize-8)) / 8)
 #define branchAddr	 ((xPC + 8  + (_Imm11_ * 8)) & (mVU->microMemSize-8))
 #define branchAddrN	 ((xPC + 16 + (_Imm11_ * 8)) & (mVU->microMemSize-8))
+#else
+#define incPC(x)	 (mVU->advancePC(x))
+#define branchAddr	 mVU->getBranchAddr()
+#define branchAddrN	 mVU->getBranchAddrN()
+#endif
+
+#define incPC2(x)	 { iPC = ((iPC + (x)) & mVU->progMemMask); }
+#define bSaveAddr	 (((xPC + 16) & (mVU->microMemSize-8)) / 8)
 #define shufflePQ	 (((mVU->p) ? 0xb0 : 0xe0) | ((mVU->q) ? 0x01 : 0x04))
 #define cmpOffset(x) ((u8*)&(((u8*)x)[it[0].start]))
 #define Rmem		 &mVU->regs->VI[REG_R].UL