diff --git a/pcsx2/IPU/IPU_Fifo.cpp b/pcsx2/IPU/IPU_Fifo.cpp
index 3a4af9192e..fad0d3e266 100644
--- a/pcsx2/IPU/IPU_Fifo.cpp
+++ b/pcsx2/IPU/IPU_Fifo.cpp
@@ -86,13 +86,16 @@ int IPU_Fifo_Input::write(u32* pMem, int size)
 int IPU_Fifo_Input::read(void *value)
 {
 	// wait until enough data to ensure proper streaming.
-	if (g_BP.IFC < 1)
+	if (g_BP.IFC < 4)
 	{
 		// IPU FIFO is empty and DMA is waiting so lets tell the DMA we are ready to put data in the FIFO
 		if(cpuRegs.eCycle[4] == 0x9999)
-			IPU1dma();
-
+		{
+			CPU_INT( DMAC_TO_IPU, 32 );
+		}
+		
 		if (g_BP.IFC == 0) return 0;
+		pxAssert(g_BP.IFC > 0);
 	}
 
 	CopyQWC(value, &data[readpos]);
diff --git a/pcsx2/IPU/IPUdma.cpp b/pcsx2/IPU/IPUdma.cpp
index 70ca857171..26e9e80a6a 100644
--- a/pcsx2/IPU/IPUdma.cpp
+++ b/pcsx2/IPU/IPUdma.cpp
@@ -189,7 +189,7 @@ int IPU1dma()
 			{
 				if(!WaitGSPaths())
 				{ // legacy WaitGSPaths() for now
-					IPU_INT_TO(4); //Give it a short wait.
+					IPU_INT_TO(32); //Give it a short wait.
 					return totalqwc;
 				}
 				IPU_LOG("Processing Normal QWC left %x Finished %d In Progress %d", ipu1dma.qwc, IPU1Status.DMAFinished, IPU1Status.InProgress);
@@ -203,7 +203,7 @@ int IPU1dma()
 				{
 					if(!WaitGSPaths())
 					{ // legacy WaitGSPaths() for now
-						IPU_INT_TO(4); //Give it a short wait.
+						IPU_INT_TO(32); //Give it a short wait.
 						return totalqwc;
 					}
 					IPU_LOG("Processing Chain QWC left %x Finished %d In Progress %d", ipu1dma.qwc, IPU1Status.DMAFinished, IPU1Status.InProgress);
@@ -283,7 +283,7 @@ int IPU1dma()
 
 					if(!WaitGSPaths() && ipu1dma.qwc > 0)
 					{ // legacy WaitGSPaths() for now
-						IPU_INT_TO(4); //Give it a short wait.
+						IPU_INT_TO(32); //Give it a short wait.
 						return totalqwc;
 					}
 					IPU_LOG("Processing Start Chain QWC left %x Finished %d In Progress %d", ipu1dma.qwc, IPU1Status.DMAFinished, IPU1Status.InProgress);