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pcsx2
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Fixed pretty bad bug of us counting cycles only for one VIF when the system has 2. 

Also added a couple important global variables to be savestated (breaks old state compat).

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@4941 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
ramapcsx2 2011-10-15 10:45:31 +00:00
parent 5488e082f5
commit d3f286e120
8 changed files with 68 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
pcsx2/SaveState.h
View File

@ -24,7 +24,7 @@
// the lower 16 bit value. IF the change is breaking of all compatibility with old
// states, increment the upper 16 bit value, and clear the lower 16 bits to 0.
static const u32 g_SaveVersion = (0x9A03 << 16) | 0x0000;
static const u32 g_SaveVersion = (0x9A04 << 16) | 0x0000;
// this function is meant to be used in the place of GSfreeze, and provides a safe layer
// between the GS saving function and the MTGS's needs. :)

18
pcsx2/Vif.cpp
View File

@ -44,8 +44,12 @@ void vif1Reset()
void SaveStateBase::vif0Freeze()
{
FreezeTag("VIFdma");
Freeze(g_vifCycles); // Dunno if this one is needed, but whatever, it's small. :)
FreezeTag("VIF0dma");
Freeze(g_vif0Cycles);
Freeze(g_vu0Cycles);
Freeze(g_packetsizeonvu0);
Freeze(vif0);
Freeze(nVif[0].bSize);
@ -54,6 +58,12 @@ void SaveStateBase::vif0Freeze()
void SaveStateBase::vif1Freeze()
{
FreezeTag("VIF1dma");
Freeze(g_vif1Cycles);
Freeze(g_vu1Cycles);
Freeze(g_packetsizeonvu1);
Freeze(vif1);
Freeze(nVif[1].bSize);
@ -134,7 +144,7 @@ __fi void vif0FBRST(u32 value) {
{
if (vif0.vifstalled)
{
g_vifCycles = 0;
g_vif0Cycles = 0;
// loop necessary for spiderman
//vif0ch.chcr.STR = true;
@ -230,7 +240,7 @@ __fi void vif1FBRST(u32 value) {
{
if (vif1.vifstalled)
{
g_vifCycles = 0;
g_vif1Cycles = 0;
// loop necessary for spiderman
switch(dmacRegs.ctrl.MFD)
{

28
pcsx2/Vif0_Dma.cpp
View File

@ -19,21 +19,23 @@
#include "VUmicro.h"
#include "newVif.h"
u32 g_vif0Cycles = 0;
// Run VU0 until finish, don't add cycles to EE
// because its vif stalling not the EE core...
__fi void vif0FLUSH()
{
if(g_packetsizeonvu > vif0.vifpacketsize && g_vu0Cycles > 0)
if(g_packetsizeonvu0 > vif0.vifpacketsize && g_vu0Cycles > 0)
{
//DevCon.Warning("Adding on same packet");
if( ((g_packetsizeonvu - vif0.vifpacketsize) >> 1) > g_vu0Cycles)
g_vu0Cycles -= (g_packetsizeonvu - vif0.vifpacketsize) >> 1;
if( ((g_packetsizeonvu0 - vif0.vifpacketsize) >> 1) > g_vu0Cycles)
g_vu0Cycles -= (g_packetsizeonvu0 - vif0.vifpacketsize) >> 1;
else g_vu0Cycles = 0;
}
if(g_vu0Cycles > 0)
{
//DevCon.Warning("Adding %x cycles to VIF0", g_vu1Cycles * BIAS);
g_vifCycles += g_vu0Cycles;
//DevCon.Warning("Adding %x cycles to VIF0", g_vu0Cycles * BIAS);
g_vif0Cycles += g_vu0Cycles;
g_vu0Cycles = 0;
}
g_vu0Cycles = 0;
@ -46,7 +48,7 @@ __fi void vif0FLUSH()
int _cycles = VU0.cycle;
vu0Finish();
//DevCon.Warning("VIF0 adding %x cycles", (VU0.cycle - _cycles) * BIAS);
g_vifCycles += (VU0.cycle - _cycles) * BIAS;
g_vif0Cycles += (VU0.cycle - _cycles) * BIAS;
return;
}
@ -87,7 +89,7 @@ __fi void vif0SetupTransfer()
case VIF_NORMAL_TO_MEM_MODE:
vif0.inprogress = 1;
vif0.done = true;
g_vifCycles = 2;
g_vif0Cycles = 2;
break;
case VIF_CHAIN_MODE:
@ -96,7 +98,7 @@ __fi void vif0SetupTransfer()
if (!(vif0ch.transfer("vif0 Tag", ptag))) return;
vif0ch.madr = ptag[1]._u32; //MADR = ADDR field + SPR
g_vifCycles += 1; // Add 1 g_vifCycles from the QW read for the tag
g_vif0Cycles += 1; // Add 1 g_vifCycles from the QW read for the tag
// Transfer dma tag if tte is set
@ -161,7 +163,7 @@ __fi void vif0Interrupt()
{
VIF_LOG("vif0Interrupt: %8.8x", cpuRegs.cycle);
g_vifCycles = 0;
g_vif0Cycles = 0;
vif0Regs.stat.FQC = min(vif0ch.qwc, (u16)8);
@ -201,7 +203,7 @@ __fi void vif0Interrupt()
{
_VIF0chain();
vif0Regs.stat.FQC = min(vif0ch.qwc, (u16)8);
CPU_INT(DMAC_VIF0, g_vifCycles);
CPU_INT(DMAC_VIF0, g_vif0Cycles);
return;
}
@ -216,7 +218,7 @@ __fi void vif0Interrupt()
if ((vif0.inprogress & 0x1) == 0) vif0SetupTransfer();
vif0Regs.stat.FQC = min(vif0ch.qwc, (u16)8);
CPU_INT(DMAC_VIF0, g_vifCycles);
CPU_INT(DMAC_VIF0, g_vif0Cycles);
return;
}
@ -233,7 +235,7 @@ __fi void vif0Interrupt()
vif0ch.chcr.STR = false;
vif0Regs.stat.FQC = min((u16)0x8, vif0ch.qwc);
g_vifCycles = 0;
g_vif0Cycles = 0;
hwDmacIrq(DMAC_VIF0);
vif0Regs.stat.FQC = 0;
DMA_LOG("VIF0 DMA End");
@ -246,7 +248,7 @@ void dmaVIF0()
vif0ch.chcr._u32, vif0ch.madr, vif0ch.qwc,
vif0ch.tadr, vif0ch.asr0, vif0ch.asr1);
g_vifCycles = 0;
g_vif0Cycles = 0;
g_vu0Cycles = 0;
//if(vif0.irqoffset != 0 && vif0.vifstalled == true) DevCon.Warning("Offset on VIF0 start! offset %x, Progress %x", vif0.irqoffset, vif0.vifstalled);
/*vif0.irqoffset = 0;

25
pcsx2/Vif1_Dma.cpp
View File

@ -21,20 +21,21 @@
#include "VUmicro.h"
#include "newVif.h"
u32 g_vif1Cycles = 0;
__fi void vif1FLUSH()
{
if(g_packetsizeonvu > vif1.vifpacketsize && g_vu1Cycles > 0)
if(g_packetsizeonvu1 > vif1.vifpacketsize && g_vu1Cycles > 0)
{
//DevCon.Warning("Adding on same packet");
if( ((g_packetsizeonvu - vif1.vifpacketsize) >> 1) > g_vu1Cycles)
g_vu1Cycles -= (g_packetsizeonvu - vif1.vifpacketsize) >> 1;
if( ((g_packetsizeonvu1 - vif1.vifpacketsize) >> 1) > g_vu1Cycles)
g_vu1Cycles -= (g_packetsizeonvu1 - vif1.vifpacketsize) >> 1;
else g_vu1Cycles = 0;
}
if(g_vu1Cycles > 0)
{
//DevCon.Warning("Adding %x cycles to VIF1", g_vu1Cycles * BIAS);
g_vifCycles += g_vu1Cycles;
g_vif1Cycles += g_vu1Cycles;
g_vu1Cycles = 0;
}
@ -44,7 +45,7 @@ __fi void vif1FLUSH()
int _cycles = VU1.cycle;
vu1Finish();
//DevCon.Warning("VIF1 adding %x cycles", (VU1.cycle - _cycles) * BIAS);
g_vifCycles += (VU1.cycle - _cycles) * BIAS;
g_vif1Cycles += (VU1.cycle - _cycles) * BIAS;
}
}
@ -95,7 +96,7 @@ void vif1TransferToMemory()
} while (++pMem < pMemEnd);
}
g_vifCycles += vif1ch.qwc * 2;
g_vif1Cycles += vif1ch.qwc * 2;
vif1ch.madr += vif1ch.qwc * 16; // mgs3 scene changes
if (vif1.GSLastDownloadSize >= vif1ch.qwc) {
vif1.GSLastDownloadSize -= vif1ch.qwc;
@ -158,7 +159,7 @@ __fi void vif1SetupTransfer()
if (!(vif1ch.transfer("Vif1 Tag", ptag))) return;
vif1ch.madr = ptag[1]._u32; //MADR = ADDR field + SPR
g_vifCycles += 1; // Add 1 g_vifCycles from the QW read for the tag
g_vif1Cycles += 1; // Add 1 g_vifCycles from the QW read for the tag
VIF_LOG("VIF1 Tag %8.8x_%8.8x size=%d, id=%d, madr=%lx, tadr=%lx",
ptag[1]._u32, ptag[0]._u32, vif1ch.qwc, ptag->ID, vif1ch.madr, vif1ch.tadr);
@ -233,7 +234,7 @@ __fi void vif1Interrupt()
{
VIF_LOG("vif1Interrupt: %8.8x", cpuRegs.cycle);
g_vifCycles = 0;
g_vif1Cycles = 0;
//Some games (Fahrenheit being one) start vif first, let it loop through blankness while it sets MFIFO mode, so we need to check it here.
if (dmacRegs.ctrl.MFD == MFD_VIF1) {
@ -302,7 +303,7 @@ __fi void vif1Interrupt()
if (vif1ch.chcr.DIR) vif1Regs.stat.FQC = min(vif1ch.qwc, (u16)16);
// Refraction - Removing voodoo timings for now, completely messes a lot of Path3 masked games.
/*if (vif1.dmamode == VIF_NORMAL_FROM_MEM_MODE ) CPU_INT(DMAC_VIF1, 1024);
else */CPU_INT(DMAC_VIF1, g_vifCycles /*VifCycleVoodoo*/);
else */CPU_INT(DMAC_VIF1, g_vif1Cycles /*VifCycleVoodoo*/);
return;
}
@ -317,7 +318,7 @@ __fi void vif1Interrupt()
if ((vif1.inprogress & 0x1) == 0) vif1SetupTransfer();
if (vif1ch.chcr.DIR) vif1Regs.stat.FQC = min(vif1ch.qwc, (u16)16);
CPU_INT(DMAC_VIF1, g_vifCycles);
CPU_INT(DMAC_VIF1, g_vif1Cycles);
return;
}
@ -342,7 +343,7 @@ __fi void vif1Interrupt()
vif1ch.chcr.STR = false;
vif1.vifstalled = false;
g_vifCycles = 0;
g_vif1Cycles = 0;
g_vu1Cycles = 0;
DMA_LOG("VIF1 DMA End");
hwDmacIrq(DMAC_VIF1);
@ -362,7 +363,7 @@ void dmaVIF1()
/*vif1.irqoffset = 0;
vif1.vifstalled = false;
vif1.inprogress = 0;*/
g_vifCycles = 0;
g_vif1Cycles = 0;
g_vu1Cycles = 0;
#ifdef PCSX2_DEVBUILD

15
pcsx2/Vif1_MFIFO.cpp
View File

@ -20,12 +20,11 @@
#include "Vif_Dma.h"
u16 vifqwc = 0;
u32 g_vifCycles = 0;
u32 g_vu0Cycles = 0;
u32 g_vu1Cycles = 0;
u32 g_packetsizeonvu = 0;
u32 g_packetsizeonvu0 = 0;
u32 g_packetsizeonvu1 = 0;
extern u32 g_vifCycles;
static u32 qwctag(u32 mask)
{
@ -155,7 +154,7 @@ void mfifoVIF1transfer(int qwc)
{
tDMA_TAG *ptag;
g_vifCycles = 0;
g_vif1Cycles = 0;
if (qwc > 0)
{
@ -211,7 +210,7 @@ void mfifoVIF1transfer(int qwc)
return; //IRQ set by VIFTransfer
} //else vif1.vifstalled = false;
g_vifCycles += 2;
g_vif1Cycles += 2;
}
vif1.irqoffset = 0;
@ -251,7 +250,7 @@ void mfifoVIF1transfer(int qwc)
void vifMFIFOInterrupt()
{
g_vifCycles = 0;
g_vif1Cycles = 0;
VIF_LOG("vif mfifo interrupt");
if (dmacRegs.ctrl.MFD != MFD_VIF1) {
@ -320,7 +319,7 @@ void vifMFIFOInterrupt()
case 1: //Transfer data
mfifo_VIF1chain();
//Sanity check! making sure we always have non-zero values
CPU_INT(DMAC_MFIFO_VIF, (g_vifCycles == 0 ? 4 : g_vifCycles) );
CPU_INT(DMAC_MFIFO_VIF, (g_vif1Cycles == 0 ? 4 : g_vif1Cycles) );
vif1Regs.stat.FQC = min((u16)0x10, vif1ch.qwc);
return;
}
@ -329,7 +328,7 @@ void vifMFIFOInterrupt()
vif1.vifstalled = false;
vif1.done = 1;
g_vifCycles = 0;
g_vif1Cycles = 0;
vif1Regs.stat.FQC = min((u16)0x10, vif1ch.qwc);
vif1ch.chcr.STR = false;
hwDmacIrq(DMAC_VIF1);

4
pcsx2/Vif_Codes.cpp
View File

@ -77,8 +77,8 @@ static __fi void vuExecMicro(int idx, u32 addr) {
else vu1ExecMicro(addr);
if (!idx || !THREAD_VU1) {
if (!idx) { g_vu0Cycles += (VU0.cycle-startcycles); g_packetsizeonvu = vif0.vifpacketsize; }
else { g_vu1Cycles += (VU1.cycle-startcycles); g_packetsizeonvu = vif1.vifpacketsize; }
if (!idx) { g_vu0Cycles += (VU0.cycle-startcycles); g_packetsizeonvu0 = vif0.vifpacketsize; }
else { g_vu1Cycles += (VU1.cycle-startcycles); g_packetsizeonvu1 = vif1.vifpacketsize; }
}
//DevCon.Warning("Ran VU%x, VU0 Cycles %x, VU1 Cycles %x, start %x cycle %x", idx, g_vu0Cycles, g_vu1Cycles, startcycles, VU1.cycle);
GetVifX.vifstalled = true;

6
pcsx2/Vif_Dma.h
View File

@ -117,9 +117,11 @@ enum VifModes
static const unsigned int VIF0intc = 4;
static const unsigned int VIF1intc = 5;
extern u32 g_vifCycles;
extern u32 g_vif0Cycles;
extern u32 g_vif1Cycles;
extern u32 g_vu0Cycles;
extern u32 g_vu1Cycles;
extern u32 g_packetsizeonvu;
extern u32 g_packetsizeonvu0;
extern u32 g_packetsizeonvu1;
extern void vif0FLUSH();
extern void vif1FLUSH();

18
pcsx2/Vif_Transfer.cpp
View File

@ -118,19 +118,25 @@ _vifT static __fi bool vifTransfer(u32 *data, int size, bool TTE) {
vifX.vifstalled = false;
vifX.stallontag = false;
vifX.vifpacketsize = size;
g_packetsizeonvu = size;
vifTransferLoop<idx>(data);
transferred += size - vifX.vifpacketsize;
g_vifCycles +=((transferred * BIAS) >> 2) ; /* guessing */
if (!idx) {
g_packetsizeonvu0 = size;
g_vif0Cycles +=((transferred * BIAS) >> 2) ; /* guessing */
}
else {
g_packetsizeonvu1 = size;
g_vif1Cycles +=((transferred * BIAS) >> 2) ; /* guessing */
}
if(!idx && g_vu0Cycles > 0) {
if (g_vifCycles < g_vu0Cycles) g_vu0Cycles -= g_vifCycles;
elif(g_vifCycles >= g_vu0Cycles) g_vu0Cycles = 0;
if (g_vif0Cycles < g_vu0Cycles) g_vu0Cycles -= g_vif0Cycles;
elif(g_vif0Cycles >= g_vu0Cycles) g_vu0Cycles = 0;
}
if (idx && g_vu1Cycles > 0) {
if (g_vifCycles < g_vu1Cycles) g_vu1Cycles -= g_vifCycles;
elif(g_vifCycles >= g_vu1Cycles) g_vu1Cycles = 0;
if (g_vif1Cycles < g_vu1Cycles) g_vu1Cycles -= g_vif1Cycles;
elif(g_vif1Cycles >= g_vu1Cycles) g_vu1Cycles = 0;
}
vifX.irqoffset = transferred % 4; // cannot lose the offset