mirror of https://github.com/PCSX2/pcsx2.git
Fixed a foopah in the LWL fix from earlier. >_<
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@602 96395faa-99c1-11dd-bbfe-3dabce05a288
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@ -322,15 +322,14 @@ static const u8 LWL_SHIFT[4] = { 24, 16, 8, 0 };
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static const u8 LWR_SHIFT[4] = { 0, 8, 16, 24 };
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static const u8 LWR_SHIFT[4] = { 0, 8, 16, 24 };
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void LWL() {
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void LWL() {
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if (!_Rt_) return;
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s32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
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s32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
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u32 shift = addr & 3;
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u32 shift = addr & 3;
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u32 mem;
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s32 mem; // ensure the compiler does correct sign extension into 64 bits by using s32
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memRead32(addr & ~3, (u32*)&mem);
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if (!_Rt_) return;
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cpuRegs.GPR.r[_Rt_].SD[0] = (cpuRegs.GPR.r[_Rt_].SL[0] & LWL_MASK[shift]) |
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memRead32(addr & ~3, &mem);
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// Reassignment note: ensure the compiler does sign extension into 64 bits, by using (s32).
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cpuRegs.GPR.r[_Rt_].UD[0] = (s32)(cpuRegs.GPR.r[_Rt_].SL[0] & LWL_MASK[shift]) |
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(mem << LWL_SHIFT[shift]);
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(mem << LWL_SHIFT[shift]);
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/*
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/*
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@ -346,13 +345,13 @@ void LWL() {
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void LWR() {
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void LWR() {
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s32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
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u32 shift = addr & 3;
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if (!_Rt_) return;
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if (!_Rt_) return;
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u32 mem;
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s32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
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memRead32(addr & ~3, &mem);
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u32 shift = addr & 3;
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s32 mem; // ensure the compiler does correct sign extension into 64 bits by using s32
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memRead32(addr & ~3, (u32*)&mem);
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mem = (cpuRegs.GPR.r[_Rt_].SL[0] & LWR_MASK[shift]) |
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mem = (cpuRegs.GPR.r[_Rt_].SL[0] & LWR_MASK[shift]) |
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(mem >> LWR_SHIFT[shift]);
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(mem >> LWR_SHIFT[shift]);
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@ -360,7 +359,7 @@ void LWR() {
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if( shift == 0 )
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if( shift == 0 )
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{
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{
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// This special case requires sign extension into the full 64 bit dest.
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// This special case requires sign extension into the full 64 bit dest.
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cpuRegs.GPR.r[_Rt_].SD[0] = (s32)mem;
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cpuRegs.GPR.r[_Rt_].SD[0] = mem;
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}
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}
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else
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else
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{
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{
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