mirror of https://github.com/PCSX2/pcsx2.git
DMAC: Remove some old defines, optimize case statements
This commit is contained in:
Christian Kenny
refractionpcsx2
parent
e7d1477a7e
commit
d13c7b6b3e
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@ -1061,24 +1061,24 @@ __fi u16 rcntRead32( u32 mem )
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// are all fixed to 0, so we always truncate everything in these two pages using a u16
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// return value! --air
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iswitch( mem ) {
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icase(RCNT0_COUNT) return (u16)rcntRcount(0);
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icase(RCNT0_MODE) return (u16)counters[0].modeval;
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icase(RCNT0_TARGET) return (u16)counters[0].target;
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icase(RCNT0_HOLD) return (u16)counters[0].hold;
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switch( mem ) {
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case(RCNT0_COUNT): return (u16)rcntRcount(0);
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case(RCNT0_MODE): return (u16)counters[0].modeval;
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case(RCNT0_TARGET): return (u16)counters[0].target;
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case(RCNT0_HOLD): return (u16)counters[0].hold;
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icase(RCNT1_COUNT) return (u16)rcntRcount(1);
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icase(RCNT1_MODE) return (u16)counters[1].modeval;
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icase(RCNT1_TARGET) return (u16)counters[1].target;
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icase(RCNT1_HOLD) return (u16)counters[1].hold;
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case(RCNT1_COUNT): return (u16)rcntRcount(1);
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case(RCNT1_MODE): return (u16)counters[1].modeval;
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case(RCNT1_TARGET): return (u16)counters[1].target;
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case(RCNT1_HOLD): return (u16)counters[1].hold;
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icase(RCNT2_COUNT) return (u16)rcntRcount(2);
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icase(RCNT2_MODE) return (u16)counters[2].modeval;
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icase(RCNT2_TARGET) return (u16)counters[2].target;
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case(RCNT2_COUNT): return (u16)rcntRcount(2);
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case(RCNT2_MODE): return (u16)counters[2].modeval;
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case(RCNT2_TARGET): return (u16)counters[2].target;
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icase(RCNT3_COUNT) return (u16)rcntRcount(3);
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icase(RCNT3_MODE) return (u16)counters[3].modeval;
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icase(RCNT3_TARGET) return (u16)counters[3].target;
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case(RCNT3_COUNT): return (u16)rcntRcount(3);
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case(RCNT3_MODE): return (u16)counters[3].modeval;
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case(RCNT3_TARGET): return (u16)counters[3].target;
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}
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return psHu16(mem);
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@ -1093,24 +1093,24 @@ __fi bool rcntWrite32( u32 mem, mem32_t& value )
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// count, mode, target, and hold. This will allow for a simplified handler for register
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// reads.
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iswitch( mem ) {
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icase(RCNT0_COUNT) return rcntWcount(0, value), false;
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icase(RCNT0_MODE) return rcntWmode(0, value), false;
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icase(RCNT0_TARGET) return rcntWtarget(0, value), false;
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icase(RCNT0_HOLD) return rcntWhold(0, value), false;
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switch( mem ) {
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case(RCNT0_COUNT): return rcntWcount(0, value), false;
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case(RCNT0_MODE): return rcntWmode(0, value), false;
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case(RCNT0_TARGET): return rcntWtarget(0, value), false;
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case(RCNT0_HOLD): return rcntWhold(0, value), false;
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icase(RCNT1_COUNT) return rcntWcount(1, value), false;
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icase(RCNT1_MODE) return rcntWmode(1, value), false;
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icase(RCNT1_TARGET) return rcntWtarget(1, value), false;
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icase(RCNT1_HOLD) return rcntWhold(1, value), false;
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case(RCNT1_COUNT): return rcntWcount(1, value), false;
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case(RCNT1_MODE): return rcntWmode(1, value), false;
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case(RCNT1_TARGET): return rcntWtarget(1, value), false;
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case(RCNT1_HOLD): return rcntWhold(1, value), false;
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icase(RCNT2_COUNT) return rcntWcount(2, value), false;
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icase(RCNT2_MODE) return rcntWmode(2, value), false;
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icase(RCNT2_TARGET) return rcntWtarget(2, value), false;
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case(RCNT2_COUNT): return rcntWcount(2, value), false;
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case(RCNT2_MODE): return rcntWmode(2, value), false;
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case(RCNT2_TARGET): return rcntWtarget(2, value), false;
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icase(RCNT3_COUNT) return rcntWcount(3, value), false;
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icase(RCNT3_MODE) return rcntWmode(3, value), false;
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icase(RCNT3_TARGET) return rcntWtarget(3, value), false;
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case(RCNT3_COUNT): return rcntWcount(3, value), false;
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case(RCNT3_MODE): return rcntWmode(3, value), false;
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case(RCNT3_TARGET): return rcntWtarget(3, value), false;
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}
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// unhandled .. do memory writeback.
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166
pcsx2/Dmac.cpp
166
pcsx2/Dmac.cpp
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@ -299,7 +299,7 @@ template< uint page >
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__fi u32 dmacRead32( u32 mem )
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{
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// Fixme: OPH hack. Toggle the flag on GIF_STAT access. (rama)
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if (IsPageFor(mem) && (mem == GIF_STAT) && CHECK_OPHFLAGHACK)
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if ((CHECK_OPHFLAGHACK) && (page << 12) == (mem & (0xf << 12)) && (mem == GIF_STAT))
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{
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static unsigned counter = 1;
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if (++counter == 8)
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@ -374,166 +374,110 @@ __fi bool dmacWrite32( u32 mem, mem32_t& value )
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allow_write:;
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}
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iswitch(mem) {
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icase(D0_CHCR) // dma0 - vif0
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switch(mem) {
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case (D0_QWC): // dma0 - vif0
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case (D1_QWC): // dma1 - vif1
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case (D2_QWC): // dma2 - gif
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case (D3_QWC): // dma3 - fromIPU
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case (D4_QWC): // dma4 - toIPU
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case (D5_QWC): // dma5 - sif0
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case (D6_QWC): // dma6 - sif1
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case (D7_QWC): // dma7 - sif2
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case (D8_QWC): // dma8 - fromSPR
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case (D9_QWC): // dma9 - toSPR
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{
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psHu32(mem) = (u16)value;
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return false;
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}
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case (D0_CHCR): // dma0 - vif0
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{
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DMA_LOG("VIF0dma EXECUTE, value=0x%x", value);
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DmaExec(dmaVIF0, mem, value);
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return false;
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}
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icase(D0_QWC) // dma0 - vif0
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{
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psHu32(mem) = (u16)value;
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return false;
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}
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icase(D1_CHCR) // dma1 - vif1 - chcr
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case (D1_CHCR): // dma1 - vif1 - chcr
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{
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DMA_LOG("VIF1dma EXECUTE, value=0x%x", value);
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DmaExec(dmaVIF1, mem, value);
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return false;
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}
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icase(D1_QWC) // dma1 - vif1
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{
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psHu32(mem) = (u16)value;
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return false;
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}
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icase(D2_CHCR) // dma2 - gif
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case (D2_CHCR): // dma2 - gif
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{
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DMA_LOG("GIFdma EXECUTE, value=0x%x", value);
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DmaExec(dmaGIF, mem, value);
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return false;
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}
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icase(D2_QWC) // dma2 - gif
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{
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psHu32(mem) = (u16)value;
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return false;
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}
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icase(D3_CHCR) // dma3 - fromIPU
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case (D3_CHCR): // dma3 - fromIPU
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{
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DMA_LOG("IPU0dma EXECUTE, value=0x%x\n", value);
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DmaExec(dmaIPU0, mem, value);
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return false;
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}
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icase(D3_QWC) // dma3 - fromIPU
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{
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psHu32(mem) = (u16)value;
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return false;
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}
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icase(D4_CHCR) // dma4 - toIPU
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case (D4_CHCR): // dma4 - toIPU
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{
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DMA_LOG("IPU1dma EXECUTE, value=0x%x\n", value);
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DmaExec(dmaIPU1, mem, value);
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return false;
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}
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icase(D4_QWC) // dma4 - toIPU
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{
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psHu32(mem) = (u16)value;
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return false;
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}
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icase(D5_CHCR) // dma5 - sif0
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case (D5_CHCR): // dma5 - sif0
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{
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DMA_LOG("SIF0dma EXECUTE, value=0x%x", value);
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DmaExec(dmaSIF0, mem, value);
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return false;
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}
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icase(D5_QWC) // dma5 - sif0
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{
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psHu32(mem) = (u16)value;
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return false;
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}
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icase(D6_CHCR) // dma6 - sif1
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case (D6_CHCR): // dma6 - sif1
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{
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DMA_LOG("SIF1dma EXECUTE, value=0x%x", value);
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DmaExec(dmaSIF1, mem, value);
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return false;
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}
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icase(D6_QWC) // dma6 - sif1
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{
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psHu32(mem) = (u16)value;
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return false;
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}
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icase(D7_CHCR) // dma7 - sif2
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case (D7_CHCR): // dma7 - sif2
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{
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DMA_LOG("SIF2dma EXECUTE, value=0x%x", value);
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DmaExec(dmaSIF2, mem, value);
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return false;
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}
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icase(D7_QWC) // dma7 - sif2
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{
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psHu32(mem) = (u16)value;
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return false;
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}
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icase(D8_CHCR) // dma8 - fromSPR
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case (D8_CHCR): // dma8 - fromSPR
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{
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DMA_LOG("SPR0dma EXECUTE (fromSPR), value=0x%x", value);
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DmaExec(dmaSPR0, mem, value);
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return false;
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}
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icase(D8_QWC) // dma8 - fromSPR
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{
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psHu32(mem) = (u16)value;
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return false;
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}
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icase(fromSPR_MADR)
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{
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// SPR bit is fixed at 0 for this channel
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psHu32(mem) = value & 0x7FFFFFFF;
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return false;
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}
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icase(toSPR_MADR)
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{
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// SPR bit is fixed at 0 for this channel
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psHu32(mem) = value & 0x7FFFFFFF;
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return false;
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}
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icase(fromSPR_SADR)
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{
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// Address must be QW aligned and fit in the 16K range of SPR
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psHu32(mem) = value & 0x3FF0;
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return false;
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}
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icase(toSPR_SADR)
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{
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// Address must be QW aligned and fit in the 16K range of SPR
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psHu32(mem) = value & 0x3FF0;
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return false;
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}
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icase(D9_CHCR) // dma9 - toSPR
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case (D9_CHCR): // dma9 - toSPR
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{
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DMA_LOG("SPR1dma EXECUTE (toSPR), value=0x%x", value);
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DmaExec(dmaSPR1, mem, value);
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return false;
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}
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icase(D9_QWC) // dma9 - toSPR
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case (fromSPR_MADR):
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case (toSPR_MADR):
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{
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psHu32(mem) = (u16)value;
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// SPR bit is fixed at 0 for this channel
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psHu32(mem) = value & 0x7FFFFFFF;
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return false;
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}
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icase(DMAC_CTRL)
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case (fromSPR_SADR):
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case (toSPR_SADR):
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{
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// Address must be QW aligned and fit in the 16K range of SPR
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psHu32(mem) = value & 0x3FF0;
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return false;
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}
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case (DMAC_CTRL):
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{
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u32 oldvalue = psHu32(mem);
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@ -594,10 +538,14 @@ __fi bool dmacWrite32( u32 mem, mem32_t& value )
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//Midway are a bunch of idiots, writing to E100 (reserved) instead of E010
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//Which causes a CPCOND0 to fail.
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icase(DMAC_FAKESTAT)
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case (DMAC_FAKESTAT):
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case (DMAC_STAT):
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{
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//DevCon.Warning("Midway fixup addr=%x writing %x for DMA_STAT", mem, value);
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HW_LOG("Midways own DMAC_STAT Write 32bit %x", value);
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if (DMAC_FAKESTAT)
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{
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HW_LOG("Midways own DMAC_STAT Write 32bit %x", value);
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}
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else HW_LOG("DMAC_STAT Write 32bit %x", value);
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// lower 16 bits: clear on 1
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// upper 16 bits: reverse on 1
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@ -609,21 +557,7 @@ __fi bool dmacWrite32( u32 mem, mem32_t& value )
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return false;
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}
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icase(DMAC_STAT)
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{
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HW_LOG("DMAC_STAT Write 32bit %x", value);
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// lower 16 bits: clear on 1
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// upper 16 bits: reverse on 1
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psHu16(0xe010) &= ~(value & 0xffff);
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psHu16(0xe012) ^= (u16)(value >> 16);
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cpuTestDMACInts();
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return false;
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}
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icase(DMAC_ENABLEW)
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case (DMAC_ENABLEW):
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{
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HW_LOG("DMAC_ENABLEW Write 32bit %lx", value);
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oldvalue = psHu8(DMAC_ENABLEW + 2);
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@ -635,6 +569,8 @@ __fi bool dmacWrite32( u32 mem, mem32_t& value )
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}
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return false;
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}
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default:
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return true;
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}
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// fall-through: use the default writeback provided by caller.
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@ -96,9 +96,9 @@ void _hwWrite32( u32 mem, u32 value )
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if (!vifWrite32<0>(mem, value)) return;
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}
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}
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else iswitch(mem)
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else switch(mem)
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{
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icase(GIF_CTRL)
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case (GIF_CTRL):
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{
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// Not exactly sure what RST needs to do
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gifRegs.ctrl.write(value & 9);
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@ -111,7 +111,7 @@ void _hwWrite32( u32 mem, u32 value )
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return;
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}
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icase(GIF_MODE)
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case (GIF_MODE):
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{
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gifRegs.mode.write(value);
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//Need to kickstart the GIF if the M3R mask comes off
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@ -291,8 +291,7 @@ void _hwWrite8(u32 mem, u8 value)
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#if PSX_EXTRALOGS
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if ((mem & 0x1000ff00) == 0x1000f300) DevCon.Warning("8bit Write to SIF Register %x value %x wibble", mem, value);
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#endif
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iswitch (mem)
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icase(SIO_TXFIFO)
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if (mem == SIO_TXFIFO)
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{
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static bool iggy_newline = false;
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static char sio_buffer[1024];
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@ -17,25 +17,6 @@
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#include "Hw.h"
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// --------------------------------------------------------------------------------------
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// IsPageFor() / iswitch() / icase() [macros!]
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// --------------------------------------------------------------------------------------
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// Page-granulated switch helpers: In order for the compiler to optimize hardware register
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// handlers, which dispatch registers along a series of switches, the compiler needs to know
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// that the case entry applies to the current page only. Under MSVC, I tried all manners of
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// bitmasks against the templated page value, and this was the only one that worked:
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//
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// Note: MSVC 2008 actually fails to optimize "switch" properly due to being overly aggressive
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// about trying to use its clever BSP-tree logic for long switches. It adds the BSP tree logic,
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// even though most of the "tree" is empty (resulting in several compare/jumps that do nothing).
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// Explained: Even though only one or two of the switch entires are valid, MSVC will still
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// compile in its BSP tree check (which divides the switch into 2 or 4 ranges of values). Three
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// of the ranges just link to "RET", while the fourth range contains the handler for the one
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// register operation contained in the templated page.
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#define IsPageFor(_mem) ((page<<12) == (_mem&(0xf<<12)))
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#define icase(ugh) if(IsPageFor(ugh) && (mem==ugh))
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#define iswitch(mem)
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// hw read functions
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template< uint page > extern mem8_t hwRead8 (u32 mem);
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