mirror of https://github.com/PCSX2/pcsx2.git
ReorderingMTGS: Change the location of the Linux version of memcpy_amd_qwc for the moment, so it compiles.
git-svn-id: http://pcsx2.googlecode.com/svn/branches/ReorderingMTGS@3501 96395faa-99c1-11dd-bbfe-3dabce05a288
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@ -22,95 +22,8 @@
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extern "C" void __fastcall memcpy_amd_(void *dest, const void *src, size_t bytes);
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extern "C" u8 memcmp_mmx(const void* src1, const void* src2, int cmpsize);
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extern "C" void memxor_mmx(void* dst, const void* src1, int cmpsize);
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extern void memcpy_amd_qwc(void *dest, const void *src, size_t bytes);
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// This can be moved later, but Linux doesn't even compile memcpyFast.cpp, so I figured I'd stick it here for now.
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// Quadword Copy! Count is in QWCs (128 bits). Neither source nor dest need to be aligned.
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static __forceinline void memcpy_amd_qwc(void *dest, const void *src, size_t qwc)
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{
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// Optimization Analysis: This code is *nearly* optimal. Do not think that using XMM
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// registers will improve copy performance, because they won't. Use of XMMs is only
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// warranted in situations where both source and dest are guaranteed aligned to 16 bytes,
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// and even then the benefits are typically minimal (sometimes slower depending on the
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// amount of data being copied).
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//
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// Thus: MMX are alignment safe, fast, and widely available. Lets just stick with them.
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// --air
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// Linux Conversion note:
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// This code would benefit nicely from having inline-able GAS syntax, since it should
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// allow GCC to optimize the first 3 instructions out of existence in many scenarios.
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// And its called enough times to probably merit the extra effort to ensure proper
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// optimization. --air
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__asm__
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(
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".intel_syntax noprefix\n"
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//"mov ecx, [%[dest]]\n"
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//"mov edx, [%[src]]\n"
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//"mov eax, [%[qwc]]\n" // keep a copy of count
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"mov eax, %[qwc]\n"
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"shr eax, 1\n"
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"jz memcpy_qwc_1\n" // only one 16 byte block to copy?
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"cmp %[qwc], 64\n" // "IN_CACHE_COPY/32"
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"jb memcpy_qwc_loop1\n" // small copies should be cached (definite speedup --air)
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"memcpy_qwc_loop2:\n" // 32-byte blocks, uncached copy
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"prefetchnta [%[src] + 568]\n" // start reading ahead (tested: it helps! --air)
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"movq mm0,[%[src]+0]\n" // read 64 bits
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"movq mm1,[%[src]+8]\n"
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"movq mm2,[%[src]+16]\n"
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"movntq [%[dest]+0], mm0\n" // write 64 bits, bypassing the cache
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"movntq [%[dest]+8], mm1\n"
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"movq mm3,[%[src]+24]\n"
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"movntq [%[dest]+16], mm2\n"
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"movntq [%[dest]+24], mm3\n"
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"add %[src],32\n" // update source pointer
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"add %[dest],32\n" // update destination pointer
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"sub eax,1\n"
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"jnz memcpy_qwc_loop2\n" // last 64-byte block?
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"sfence\n" // flush the write buffer
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"jmp memcpy_qwc_1\n"
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// 32-byte blocks, cached!
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// This *is* important. Removing this and using exclusively non-temporal stores
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// results in noticeable speed loss!
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"memcpy_qwc_loop1:\n"
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"prefetchnta [%[src] + 568]\n" // start reading ahead (tested: it helps! --air)
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"movq mm0,[%[src]+0]\n" // read 64 bits
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"movq mm1,[%[src]+8]\n"
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"movq mm2,[%[src]+16]\n"
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"movq [%[dest]+0], mm0\n" // write 64 bits, bypassing the cache
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"movq [%[dest]+8], mm1\n"
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"movq mm3,[%[src]+24]\n"
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"movq [%[dest]+16], mm2\n"
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"movq [%[dest]+24], mm3\n"
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"add %[src],32\n" // update source pointer
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"add %[dest],32\n" // update destination pointer
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"sub eax,1\n"
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"jnz memcpy_qwc_loop1\n" // last 64-byte block?
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"memcpy_qwc_1:\n"
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"test [%qwc],1\n"
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"jz memcpy_qwc_final\n"
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"movq mm0,[%[src]]\n"
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"movq mm1,[%[src]+8]\n"
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"movq [%[dest]], mm0\n"
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"movq [%[dest]+8], mm1\n"
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"memcpy_qwc_final:\n"
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"emms\n" // clean up the MMX state
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".att_syntax\n"
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: "=&r"(dest), "=&r"(src), "=&r"(qwc)
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: [dest]"0"(dest), [src]"1"(src), [qwc]"2"(qwc)
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: "memory", "eax", "mm0", "mm1", "mm2", "mm3"
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);
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}
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#else
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# include "win_memzero.h"
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@ -156,3 +156,98 @@ __forceinline void memcpy_vibes(void * dest, const void * src, int size) {
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#endif
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#endif
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// Since MemcpyVibes is already in the project, I'll just tuck the Linux version of memcpy_amd_qwc here for the moment,
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// to get around compilation issues with having it in the headers.
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#ifdef __LINUX__
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// This can be moved later, but Linux doesn't even compile memcpyFast.cpp, so I figured I'd stick it here for now.
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// Quadword Copy! Count is in QWCs (128 bits). Neither source nor dest need to be aligned.
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__forceinline void memcpy_amd_qwc(void *dest, const void *src, size_t qwc)
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{
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// Optimization Analysis: This code is *nearly* optimal. Do not think that using XMM
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// registers will improve copy performance, because they won't. Use of XMMs is only
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// warranted in situations where both source and dest are guaranteed aligned to 16 bytes,
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// and even then the benefits are typically minimal (sometimes slower depending on the
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// amount of data being copied).
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//
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// Thus: MMX are alignment safe, fast, and widely available. Lets just stick with them.
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// --air
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// Linux Conversion note:
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// This code would benefit nicely from having inline-able GAS syntax, since it should
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// allow GCC to optimize the first 3 instructions out of existence in many scenarios.
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// And its called enough times to probably merit the extra effort to ensure proper
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// optimization. --air
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__asm__
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(
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".intel_syntax noprefix\n"
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//"mov ecx, [%[dest]]\n"
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//"mov edx, [%[src]]\n"
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//"mov eax, [%[qwc]]\n" // keep a copy of count
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"mov eax, %[qwc]\n"
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"shr eax, 1\n"
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"jz memcpy_qwc_1\n" // only one 16 byte block to copy?
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"cmp %[qwc], 64\n" // "IN_CACHE_COPY/32"
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"jb memcpy_qwc_loop1\n" // small copies should be cached (definite speedup --air)
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"memcpy_qwc_loop2:\n" // 32-byte blocks, uncached copy
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"prefetchnta [%[src] + 568]\n" // start reading ahead (tested: it helps! --air)
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"movq mm0,[%[src]+0]\n" // read 64 bits
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"movq mm1,[%[src]+8]\n"
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"movq mm2,[%[src]+16]\n"
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"movntq [%[dest]+0], mm0\n" // write 64 bits, bypassing the cache
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"movntq [%[dest]+8], mm1\n"
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"movq mm3,[%[src]+24]\n"
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"movntq [%[dest]+16], mm2\n"
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"movntq [%[dest]+24], mm3\n"
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"add %[src],32\n" // update source pointer
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"add %[dest],32\n" // update destination pointer
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"sub eax,1\n"
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"jnz memcpy_qwc_loop2\n" // last 64-byte block?
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"sfence\n" // flush the write buffer
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"jmp memcpy_qwc_1\n"
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// 32-byte blocks, cached!
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// This *is* important. Removing this and using exclusively non-temporal stores
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// results in noticeable speed loss!
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"memcpy_qwc_loop1:\n"
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"prefetchnta [%[src] + 568]\n" // start reading ahead (tested: it helps! --air)
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"movq mm0,[%[src]+0]\n" // read 64 bits
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"movq mm1,[%[src]+8]\n"
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"movq mm2,[%[src]+16]\n"
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"movq [%[dest]+0], mm0\n" // write 64 bits, bypassing the cache
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"movq [%[dest]+8], mm1\n"
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"movq mm3,[%[src]+24]\n"
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"movq [%[dest]+16], mm2\n"
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"movq [%[dest]+24], mm3\n"
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"add %[src],32\n" // update source pointer
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"add %[dest],32\n" // update destination pointer
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"sub eax,1\n"
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"jnz memcpy_qwc_loop1\n" // last 64-byte block?
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"memcpy_qwc_1:\n"
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"test %[qwc],1\n"
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"jz memcpy_qwc_final\n"
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"movq mm0,[%[src]]\n"
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"movq mm1,[%[src]+8]\n"
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"movq [%[dest]], mm0\n"
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"movq [%[dest]+8], mm1\n"
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"memcpy_qwc_final:\n"
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"emms\n" // clean up the MMX state
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".att_syntax\n"
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: "=&r"(dest), "=&r"(src), "=&r"(qwc)
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: [dest]"0"(dest), [src]"1"(src), [qwc]"2"(qwc)
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: "memory", "eax", "mm0", "mm1", "mm2", "mm3"
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);
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}
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#endif
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