mirror of https://github.com/PCSX2/pcsx2.git
Remove gigaherz old wip 'new' iopdma code. (#2703)
* Remove gigaherz old wip new iopdma code. * Second pass removing dma code I missed last time.
This commit is contained in:
arcum42
GitHub
parent
ecbd8d9f2f
commit
d05163a26f
|
|
@ -16,18 +16,6 @@
|
|||
#ifndef __PS2EDEFS_H__
|
||||
#define __PS2EDEFS_H__
|
||||
|
||||
// Global enable/disable flag, disables all the parts if off
|
||||
//#define ENABLE_NEW_IOPDMA
|
||||
|
||||
// Parts of the dmac, each one can be turned on independently
|
||||
#ifdef ENABLE_NEW_IOPDMA
|
||||
//#define ENABLE_NEW_IOPDMA_SPU2 /* working */
|
||||
//#define ENABLE_NEW_IOPDMA_SIO /* working */
|
||||
//#define ENABLE_NEW_IOPDMA_CDVD /* NOT IMPLEMENTED */
|
||||
//#define ENABLE_NEW_IOPDMA_SIF /* NOT IMPLEMENTED */
|
||||
//#define ENABLE_NEW_IOPDMA_DEV9 /* untested (no plugins) */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* PS2E Definitions v0.6.2 (beta)
|
||||
*
|
||||
|
|
@ -104,17 +92,9 @@ typedef struct _keyEvent
|
|||
// PS2EgetLibVersion2 (high 16 bits)
|
||||
#define PS2E_GS_VERSION 0x0006
|
||||
#define PS2E_PAD_VERSION 0x0002 // -=[ OBSOLETE ]=-
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
#define PS2E_SPU2_VERSION 0x0006
|
||||
#else
|
||||
#define PS2E_SPU2_VERSION 0x0005
|
||||
#endif
|
||||
#define PS2E_CDVD_VERSION 0x0005
|
||||
#ifdef ENABLE_NEW_IOPDMA_DEV9
|
||||
#define PS2E_DEV9_VERSION 0x0004
|
||||
#else
|
||||
#define PS2E_DEV9_VERSION 0x0003
|
||||
#endif
|
||||
#define PS2E_USB_VERSION 0x0003
|
||||
#define PS2E_FW_VERSION 0x0002
|
||||
#define PS2E_SIO_VERSION 0x0001
|
||||
|
|
@ -354,14 +334,6 @@ void CALLBACK SPU2reset();
|
|||
void CALLBACK SPU2write(u32 mem, u16 value);
|
||||
u16 CALLBACK SPU2read(u32 mem);
|
||||
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
s32 CALLBACK SPU2dmaRead(s32 channel, u32 *data, u32 bytesLeft, u32 *bytesProcessed);
|
||||
s32 CALLBACK SPU2dmaWrite(s32 channel, u32 *data, u32 bytesLeft, u32 *bytesProcessed);
|
||||
void CALLBACK SPU2dmaInterrupt(s32 channel);
|
||||
|
||||
// dma irq callbacks not needed anymore, they are handled by the dmac
|
||||
void CALLBACK SPU2irqCallback(void (*SPU2callback)());
|
||||
#else
|
||||
void CALLBACK SPU2readDMA4Mem(u16 *pMem, int size);
|
||||
void CALLBACK SPU2writeDMA4Mem(u16 *pMem, int size);
|
||||
void CALLBACK SPU2interruptDMA4();
|
||||
|
|
@ -378,7 +350,6 @@ u32 CALLBACK SPU2ReadMemAddr(int core);
|
|||
void CALLBACK SPU2WriteMemAddr(int core, u32 value);
|
||||
|
||||
void CALLBACK SPU2irqCallback(void (*SPU2callback)(), void (*DMA4callback)(), void (*DMA7callback)());
|
||||
#endif
|
||||
|
||||
// extended funcs
|
||||
// if start is 1, starts recording spu2 data, else stops
|
||||
|
|
@ -468,14 +439,9 @@ u32 CALLBACK DEV9read32(u32 addr);
|
|||
void CALLBACK DEV9write8(u32 addr, u8 value);
|
||||
void CALLBACK DEV9write16(u32 addr, u16 value);
|
||||
void CALLBACK DEV9write32(u32 addr, u32 value);
|
||||
#ifdef ENABLE_NEW_IOPDMA_DEV9
|
||||
s32 CALLBACK DEV9dmaRead(s32 channel, u32 *data, u32 bytesLeft, u32 *bytesProcessed);
|
||||
s32 CALLBACK DEV9dmaWrite(s32 channel, u32 *data, u32 bytesLeft, u32 *bytesProcessed);
|
||||
void CALLBACK DEV9dmaInterrupt(s32 channel);
|
||||
#else
|
||||
void CALLBACK DEV9readDMA8Mem(u32 *pMem, int size);
|
||||
void CALLBACK DEV9writeDMA8Mem(u32 *pMem, int size);
|
||||
#endif
|
||||
|
||||
// cycles = IOP cycles before calling callback,
|
||||
// if callback returns 1 the irq is triggered, else not
|
||||
void CALLBACK DEV9irqCallback(DEV9callback callback);
|
||||
|
|
@ -615,15 +581,6 @@ typedef s32(CALLBACK *_SPU2open)(void *pDsp);
|
|||
typedef void(CALLBACK *_SPU2reset)();
|
||||
typedef void(CALLBACK *_SPU2write)(u32 mem, u16 value);
|
||||
typedef u16(CALLBACK *_SPU2read)(u32 mem);
|
||||
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
typedef s32(CALLBACK *_SPU2dmaRead)(s32 channel, u32 *data, u32 bytesLeft, u32 *bytesProcessed);
|
||||
typedef s32(CALLBACK *_SPU2dmaWrite)(s32 channel, u32 *data, u32 bytesLeft, u32 *bytesProcessed);
|
||||
typedef void(CALLBACK *_SPU2dmaInterrupt)(s32 channel);
|
||||
|
||||
// dma irq callbacks not needed anymore, they are handled by the dmac
|
||||
typedef void(CALLBACK *_SPU2irqCallback)(void (*SPU2callback)());
|
||||
#else
|
||||
typedef void(CALLBACK *_SPU2readDMA4Mem)(u16 *pMem, int size);
|
||||
typedef void(CALLBACK *_SPU2writeDMA4Mem)(u16 *pMem, int size);
|
||||
typedef void(CALLBACK *_SPU2interruptDMA4)();
|
||||
|
|
@ -634,7 +591,6 @@ typedef void(CALLBACK *_SPU2interruptDMA7)();
|
|||
typedef void(CALLBACK *_SPU2irqCallback)(void (*SPU2callback)(), void (*DMA4callback)(), void (*DMA7callback)());
|
||||
typedef u32(CALLBACK *_SPU2ReadMemAddr)(int core);
|
||||
typedef void(CALLBACK *_SPU2WriteMemAddr)(int core, u32 value);
|
||||
#endif
|
||||
|
||||
typedef int(CALLBACK *_SPU2setupRecording)(int, void *);
|
||||
|
||||
|
|
@ -688,14 +644,8 @@ typedef u32(CALLBACK *_DEV9read32)(u32 mem);
|
|||
typedef void(CALLBACK *_DEV9write8)(u32 mem, u8 value);
|
||||
typedef void(CALLBACK *_DEV9write16)(u32 mem, u16 value);
|
||||
typedef void(CALLBACK *_DEV9write32)(u32 mem, u32 value);
|
||||
#ifdef ENABLE_NEW_IOPDMA_DEV9
|
||||
typedef s32(CALLBACK *_DEV9dmaRead)(s32 channel, u32 *data, u32 bytesLeft, u32 *bytesProcessed);
|
||||
typedef s32(CALLBACK *_DEV9dmaWrite)(s32 channel, u32 *data, u32 bytesLeft, u32 *bytesProcessed);
|
||||
typedef void(CALLBACK *_DEV9dmaInterrupt)(s32 channel);
|
||||
#else
|
||||
typedef void(CALLBACK *_DEV9readDMA8Mem)(u32 *pMem, int size);
|
||||
typedef void(CALLBACK *_DEV9writeDMA8Mem)(u32 *pMem, int size);
|
||||
#endif
|
||||
typedef void(CALLBACK *_DEV9irqCallback)(DEV9callback callback);
|
||||
typedef DEV9handler(CALLBACK *_DEV9irqHandler)(void);
|
||||
typedef void(CALLBACK *_DEV9async)(u32 cycles);
|
||||
|
|
@ -777,11 +727,6 @@ extern _SPU2reset SPU2reset;
|
|||
extern _SPU2write SPU2write;
|
||||
extern _SPU2read SPU2read;
|
||||
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
extern _SPU2dmaRead SPU2dmaRead;
|
||||
extern _SPU2dmaWrite SPU2dmaWrite;
|
||||
extern _SPU2dmaInterrupt SPU2dmaInterrupt;
|
||||
#else
|
||||
extern _SPU2readDMA4Mem SPU2readDMA4Mem;
|
||||
extern _SPU2writeDMA4Mem SPU2writeDMA4Mem;
|
||||
extern _SPU2interruptDMA4 SPU2interruptDMA4;
|
||||
|
|
@ -793,7 +738,6 @@ extern _SPU2ReadMemAddr SPU2ReadMemAddr;
|
|||
extern _SPU2setupRecording SPU2setupRecording;
|
||||
extern _SPU2WriteMemAddr SPU2WriteMemAddr;
|
||||
extern _SPU2irqCallback SPU2irqCallback;
|
||||
#endif
|
||||
|
||||
extern _SPU2irqCallback SPU2irqCallback;
|
||||
|
||||
|
|
@ -814,14 +758,8 @@ extern _DEV9read32 DEV9read32;
|
|||
extern _DEV9write8 DEV9write8;
|
||||
extern _DEV9write16 DEV9write16;
|
||||
extern _DEV9write32 DEV9write32;
|
||||
#ifdef ENABLE_NEW_IOPDMA_DEV9
|
||||
extern _DEV9dmaRead DEV9dmaRead;
|
||||
extern _DEV9dmaWrite DEV9dmaWrite;
|
||||
extern _DEV9dmaInterrupt DEV9dmaInterrupt;
|
||||
#else
|
||||
extern _DEV9readDMA8Mem DEV9readDMA8Mem;
|
||||
extern _DEV9writeDMA8Mem DEV9writeDMA8Mem;
|
||||
#endif
|
||||
extern _DEV9irqCallback DEV9irqCallback;
|
||||
extern _DEV9irqHandler DEV9irqHandler;
|
||||
extern _DEV9async DEV9async;
|
||||
|
|
|
|||
|
|
@ -994,38 +994,6 @@ void psxDma3(u32 madr, u32 bcr, u32 chcr) {
|
|||
psxDmaInterrupt(3);
|
||||
}
|
||||
|
||||
#ifdef ENABLE_NEW_IOPDMA
|
||||
s32 CALLBACK cdvdDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
|
||||
{
|
||||
#ifdef ENABLE_NEW_IOPDMA_CDVD
|
||||
// hacked up from the code above
|
||||
|
||||
if (cdr.Readed == 0)
|
||||
{
|
||||
//CDVD_LOG("*** DMA 3 *** NOT READY");
|
||||
wordsProcessed = 0;
|
||||
return 10000;
|
||||
}
|
||||
|
||||
memcpy(data, cdr.pTransfer, wordsLeft);
|
||||
//psxCpu->Clear(madr, cdsize/4);
|
||||
cdr.pTransfer+=wordsLeft;
|
||||
*wordsProcessed = wordsLeft;
|
||||
|
||||
Console.WriteLn(Color_Black,"New IOP DMA handled CDVD DMA: channel %d, data %p, remaining %08x, processed %08x.", channel,data,wordsLeft, *wordsProcessed);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
void CALLBACK cdvdDmaInterrupt(s32 channel)
|
||||
{
|
||||
#ifdef ENABLE_NEW_IOPDMA_CDVD
|
||||
cdrInterrupt();
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
void cdrReset() {
|
||||
memzero(cdr);
|
||||
cdr.CurTrack=1;
|
||||
|
|
|
|||
|
|
@ -152,12 +152,6 @@ void psxRcntInit() {
|
|||
psxCounters[7].mode = 0x8;
|
||||
}
|
||||
|
||||
#ifdef ENABLE_NEW_IOPDMA
|
||||
psxCounters[8].rate = 2000;
|
||||
psxCounters[8].CycleT = psxCounters[7].rate;
|
||||
psxCounters[8].mode = 0x8;
|
||||
#endif
|
||||
|
||||
for (i=0; i<8; i++)
|
||||
psxCounters[i].sCycleT = psxRegs.cycle;
|
||||
|
||||
|
|
@ -519,24 +513,6 @@ void psxRcntUpdate()
|
|||
if (c < psxNextCounter) psxNextCounter = c;
|
||||
}
|
||||
|
||||
#ifdef ENABLE_NEW_IOPDMA
|
||||
|
||||
// New Iop DMA handler WIP
|
||||
{
|
||||
const s32 difference = psxRegs.cycle - psxCounters[8].sCycleT;
|
||||
s32 c = psxCounters[8].CycleT;
|
||||
|
||||
if(difference >= psxCounters[8].CycleT)
|
||||
{
|
||||
psxCounters[8].sCycleT = psxRegs.cycle;
|
||||
psxCounters[8].CycleT = psxCounters[8].rate;
|
||||
IopDmaUpdate(difference);
|
||||
}
|
||||
else c -= difference;
|
||||
if (c < psxNextCounter) psxNextCounter = c;
|
||||
}
|
||||
#endif
|
||||
|
||||
for (i=0; i<6; i++) _rcntSet( i );
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -24,11 +24,7 @@ struct psxCounter {
|
|||
s32 CycleT;
|
||||
};
|
||||
|
||||
#ifdef ENABLE_NEW_IOPDMA
|
||||
# define NUM_COUNTERS 9
|
||||
#else
|
||||
# define NUM_COUNTERS 8
|
||||
#endif
|
||||
#define NUM_COUNTERS 8
|
||||
|
||||
extern psxCounter psxCounters[NUM_COUNTERS];
|
||||
|
||||
|
|
|
|||
388
pcsx2/IopDma.cpp
388
pcsx2/IopDma.cpp
|
|
@ -25,7 +25,6 @@ using namespace R3000A;
|
|||
// Dma8 in PsxSpd.c
|
||||
// Dma11/12 in PsxSio2.c
|
||||
|
||||
#ifndef ENABLE_NEW_IOPDMA_SPU2
|
||||
static void __fastcall psxDmaGeneric(u32 madr, u32 bcr, u32 chcr, u32 spuCore, _SPU2writeDMA4Mem spu2WriteFunc, _SPU2readDMA4Mem spu2ReadFunc)
|
||||
{
|
||||
const char dmaNum = spuCore ? '7' : '4';
|
||||
|
|
@ -129,8 +128,6 @@ void spu2DMA7Irq()
|
|||
psxDmaInterrupt2(0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifndef DISABLE_PSX_GPU_DMAS
|
||||
void psxDma2(u32 madr, u32 bcr, u32 chcr) // GPU
|
||||
{
|
||||
|
|
@ -170,7 +167,6 @@ void psxDma6(u32 madr, u32 bcr, u32 chcr)
|
|||
}
|
||||
#endif
|
||||
|
||||
#ifndef ENABLE_NEW_IOPDMA_DEV9
|
||||
void psxDma8(u32 madr, u32 bcr, u32 chcr)
|
||||
{
|
||||
const int size = (bcr >> 16) * (bcr & 0xFFFF) * 8;
|
||||
|
|
@ -194,7 +190,6 @@ void psxDma8(u32 madr, u32 bcr, u32 chcr)
|
|||
HW_DMA8_CHCR &= ~0x01000000;
|
||||
psxDmaInterrupt2(1);
|
||||
}
|
||||
#endif
|
||||
|
||||
void psxDma9(u32 madr, u32 bcr, u32 chcr)
|
||||
{
|
||||
|
|
@ -217,386 +212,3 @@ void psxDma10(u32 madr, u32 bcr, u32 chcr)
|
|||
}
|
||||
|
||||
/* psxDma11 & psxDma 12 are in IopSio2.cpp, along with the appropriate interrupt functions. */
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Gigaherz's "Improved DMA Handling" Engine WIP...
|
||||
//
|
||||
|
||||
#ifdef ENABLE_NEW_IOPDMA
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Local Declarations
|
||||
|
||||
// in IopSio2.cpp
|
||||
extern s32 CALLBACK sio2DmaStart(s32 channel, u32 madr, u32 bcr, u32 chcr);
|
||||
extern s32 CALLBACK sio2DmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
|
||||
extern s32 CALLBACK sio2DmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
|
||||
extern void CALLBACK sio2DmaInterrupt(s32 channel);
|
||||
|
||||
// implemented below
|
||||
s32 CALLBACK errDmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
|
||||
s32 CALLBACK errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
|
||||
|
||||
// pointer types
|
||||
typedef s32 (CALLBACK * DmaHandler)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
|
||||
typedef void (CALLBACK * DmaIHandler)(s32 channel);
|
||||
typedef s32 (CALLBACK * DmaSHandler)(s32 channel, u32 madr, u32 bcr, u32 chcr);
|
||||
|
||||
// constants
|
||||
struct DmaHandlerInfo
|
||||
{
|
||||
const char* Name;
|
||||
|
||||
// doubles as a "disable" flag
|
||||
u32 DirectionFlags;
|
||||
u32 DmacRegisterBase;
|
||||
DmaHandler Read;
|
||||
DmaHandler Write;
|
||||
DmaIHandler Interrupt;
|
||||
DmaSHandler Start;
|
||||
|
||||
__fi u32& REG_MADR(void) const { return psxHu32(DmacRegisterBase + 0x0); }
|
||||
__fi u32& REG_BCR(void) const { return psxHu32(DmacRegisterBase + 0x4); }
|
||||
__fi u32& REG_CHCR(void) const { return psxHu32(DmacRegisterBase + 0x8); }
|
||||
__fi u32& REG_TADR(void) const { return psxHu32(DmacRegisterBase + 0xC); }
|
||||
};
|
||||
|
||||
#define MEM_BASE1 0x1f801080
|
||||
#define MEM_BASE2 0x1f801500
|
||||
|
||||
#define CHANNEL_BASE1(ch) (MEM_BASE1 + ((ch)<<4))
|
||||
#define CHANNEL_BASE2(ch) (MEM_BASE2 + ((ch)<<4))
|
||||
|
||||
// channel disabled
|
||||
#define _D__ 0
|
||||
#define _D_W 1
|
||||
#define _DR_ 2
|
||||
#define _DRW 3
|
||||
// channel enabled
|
||||
#define _E__ 4
|
||||
#define _E_W 5
|
||||
#define _ER_ 6
|
||||
#define _ERW 7
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Plugin interface accessors
|
||||
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
s32 CALLBACK spu2DmaRead (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { return SPU2dmaRead(channel,data,bytesLeft,bytesProcessed); }
|
||||
s32 CALLBACK spu2DmaWrite (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { return SPU2dmaWrite(channel,data,bytesLeft,bytesProcessed); }
|
||||
void CALLBACK spu2DmaInterrupt (s32 channel) { SPU2dmaInterrupt(channel); }
|
||||
#else
|
||||
s32 CALLBACK spu2DmaRead (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { *bytesProcessed=0; return 0; }
|
||||
s32 CALLBACK spu2DmaWrite (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { *bytesProcessed=0; return 0; }
|
||||
void CALLBACK spu2DmaInterrupt (s32 channel) { }
|
||||
#endif
|
||||
#ifdef ENABLE_NEW_IOPDMA_DEV9
|
||||
s32 CALLBACK dev9DmaRead (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { return DEV9dmaRead(channel,data,bytesLeft,bytesProcessed); }
|
||||
s32 CALLBACK dev9DmaWrite (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { return DEV9dmaWrite(channel,data,bytesLeft,bytesProcessed); }
|
||||
void CALLBACK dev9DmaInterrupt (s32 channel) { DEV9dmaInterrupt(channel); }
|
||||
#else
|
||||
s32 CALLBACK dev9DmaRead (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { *bytesProcessed=0; return 0; }
|
||||
s32 CALLBACK dev9DmaWrite (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { *bytesProcessed=0; return 0; }
|
||||
void CALLBACK dev9DmaInterrupt (s32 channel) { }
|
||||
#endif
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Dma channel definitions
|
||||
|
||||
const DmaHandlerInfo IopDmaHandlers[DMA_CHANNEL_MAX] =
|
||||
{
|
||||
// First DMAC, same as PS1
|
||||
{"Ps1 Mdec in", _D__}, //0
|
||||
{"Ps1 Mdec out", _D__}, //1
|
||||
{"Ps1 Gpu", _D__}, //2
|
||||
#ifdef ENABLE_NEW_IOPDMA_CDVD
|
||||
{"CDVD", _ER_, CHANNEL_BASE1(3), cdvdDmaRead, errDmaWrite, cdvdDmaInterrupt}, //3: CDVD
|
||||
#else
|
||||
{"CDVD", _D__}, //3: CDVD
|
||||
#endif
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
{"SPU2 Core0", _ERW, CHANNEL_BASE1(4), spu2DmaRead, spu2DmaWrite, spu2DmaInterrupt}, //4: Spu/Spu2 Core0
|
||||
#else
|
||||
{"SPU2 Core0", _D__}, //4: Spu/Spu2 Core0
|
||||
#endif
|
||||
{"Ps1 PIO", _D__}, //5: PIO
|
||||
{"Ps1 OTC", _D__}, //6: "reverse clear OT" - PSX GPU related
|
||||
|
||||
// Second DMAC, new in PS2 IOP
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
{"SPU2 Core1", _ERW, CHANNEL_BASE2(0), spu2DmaRead, spu2DmaWrite, spu2DmaInterrupt}, //7: Spu2 Core1
|
||||
#else
|
||||
{"SPU2 Core1", _D__}, //7: Spu2 Core1
|
||||
#endif
|
||||
#ifdef ENABLE_NEW_IOPDMA_DEV9
|
||||
{"Dev9", _ERW, CHANNEL_BASE2(1), dev9DmaRead, dev9DmaWrite, dev9DmaInterrupt}, //8: Dev9
|
||||
#else
|
||||
{"Dev9", _D__}, //8: Dev9
|
||||
#endif
|
||||
#ifdef ENABLE_NEW_IOPDMA_SIF
|
||||
{"Sif0", _ERW, CHANNEL_BASE2(2), sif0DmaRead, sif0DmaWrite, sif0DmaInterrupt}, //9: SIF0
|
||||
{"Sif1", _ERW, CHANNEL_BASE2(3), sif1DmaRead, sif1DmaWrite, sif1DmaInterrupt}, //10: SIF1
|
||||
#else
|
||||
{"Sif0", _D__}, //9: SIF0
|
||||
{"Sif1", _D__}, //10: SIF1
|
||||
#endif
|
||||
#ifdef ENABLE_NEW_IOPDMA_SIO
|
||||
{"Sio2 (writes)", _E_W, CHANNEL_BASE2(4), errDmaRead, sio2DmaWrite, sio2DmaInterrupt, sio2DmaStart}, //11: Sio2
|
||||
{"Sio2 (reads)", _ER_, CHANNEL_BASE2(5), sio2DmaRead, errDmaWrite, sio2DmaInterrupt, sio2DmaStart}, //12: Sio2
|
||||
#else
|
||||
{"Sio2 (writes)", _D__}, //11: Sio2
|
||||
{"Sio2 (reads)", _D__}, //12: Sio2
|
||||
#endif
|
||||
{"?", _D__}, //13
|
||||
// if each dmac has 7 channels, the list would end here, but I'm not sure :p
|
||||
};
|
||||
|
||||
// runtime variables
|
||||
struct DmaChannelInfo
|
||||
{
|
||||
s32 ByteCount;
|
||||
s32 NextUpdate;
|
||||
} IopDmaChannels[DMA_CHANNEL_MAX] = {0};
|
||||
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Tool functions
|
||||
void SetDmaUpdateTarget(u32 delay)
|
||||
{
|
||||
psxCounters[8].CycleT = delay;
|
||||
if (delay < psxNextCounter)
|
||||
psxNextCounter = delay;
|
||||
}
|
||||
|
||||
void RaiseDmaIrq(u32 channel)
|
||||
{
|
||||
if(channel<7)
|
||||
psxDmaInterrupt(channel);
|
||||
else
|
||||
psxDmaInterrupt2(channel-7);
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// IopDmaStart: Called from IopHwWrite to test and possibly start a dma transfer
|
||||
|
||||
void IopDmaStart(int channel)
|
||||
{
|
||||
if(!(IopDmaHandlers[channel].DirectionFlags&_E__))
|
||||
return;
|
||||
|
||||
int chcr = IopDmaHandlers[channel].REG_CHCR();
|
||||
|
||||
int pcr = (channel>=7)?(HW_DMA_PCR2 & (8 << ((channel-7) * 4))):(HW_DMA_PCR & (8 << (channel * 4)));
|
||||
|
||||
if ( !(chcr & 0x01000000) || !pcr)
|
||||
return;
|
||||
|
||||
// I dont' really understand this, but it's used above. Is this BYTES OR WHAT?
|
||||
int bcr = IopDmaHandlers[channel].REG_BCR();
|
||||
int bcr_size = (bcr & 0xFFFF);
|
||||
int bcr_count = (bcr >> 16);
|
||||
int size = 4* bcr_count * bcr_size;
|
||||
|
||||
int dirf = IopDmaHandlers[channel].DirectionFlags&3;
|
||||
|
||||
if(dirf != 3)
|
||||
{
|
||||
bool ok = (chcr & DMA_CTRL_DIRECTION)? (dirf==_D_W) : (dirf==_DR_);
|
||||
if(!ok)
|
||||
{
|
||||
// hack?!
|
||||
IopDmaHandlers[channel].REG_CHCR() &= ~DMA_CTRL_ACTIVE;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
if(IopDmaHandlers[channel].Start)
|
||||
{
|
||||
int ret = IopDmaHandlers[channel].Start(channel,
|
||||
IopDmaHandlers[channel].REG_MADR(),
|
||||
IopDmaHandlers[channel].REG_BCR(),
|
||||
IopDmaHandlers[channel].REG_CHCR());
|
||||
if(ret < 0)
|
||||
{
|
||||
IopDmaHandlers[channel].REG_CHCR() &= ~DMA_CTRL_ACTIVE;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
//Console.WriteLn(Color_StrongOrange,"Starting NewDMA ch=%d, size=%d(0x%08x), dir=%d", channel, size, bcr, chcr&DMA_CTRL_DIRECTION);
|
||||
|
||||
IopDmaHandlers[channel].REG_CHCR() |= DMA_CTRL_ACTIVE;
|
||||
IopDmaChannels[channel].ByteCount = size;
|
||||
IopDmaChannels[channel].NextUpdate = 0;
|
||||
|
||||
//SetDmaUpdateTarget(1);
|
||||
{
|
||||
const s32 difference = psxRegs.cycle - psxCounters[8].sCycleT;
|
||||
|
||||
psxCounters[8].sCycleT = psxRegs.cycle;
|
||||
psxCounters[8].CycleT = psxCounters[8].rate;
|
||||
IopDmaUpdate(difference);
|
||||
|
||||
s32 c = psxCounters[8].CycleT;
|
||||
if (c < psxNextCounter) psxNextCounter = c;
|
||||
}
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// IopDmaProcessChannel: Called from IopDmaUpdate (below) to process a dma channel
|
||||
|
||||
template<int channel>
|
||||
static void __ri IopDmaProcessChannel(int elapsed, int& MinDelay)
|
||||
{
|
||||
// Hopefully the compiler would be able to optimize the whole function away if this doesn't pass.
|
||||
if(!(IopDmaHandlers[channel].DirectionFlags&_E__))
|
||||
return;
|
||||
|
||||
DmaChannelInfo *ch = IopDmaChannels + channel;
|
||||
const DmaHandlerInfo *hh = IopDmaHandlers + channel;
|
||||
|
||||
if (hh->REG_CHCR()&DMA_CTRL_ACTIVE)
|
||||
{
|
||||
ch->NextUpdate -= elapsed;
|
||||
if (ch->NextUpdate <= 0) // Refresh target passed
|
||||
{
|
||||
if (ch->ByteCount <= 0) // No more data left, finish dma
|
||||
{
|
||||
ch->NextUpdate = 0x7fffffff;
|
||||
|
||||
hh->REG_CHCR() &= ~DMA_CTRL_ACTIVE;
|
||||
RaiseDmaIrq(channel);
|
||||
hh->Interrupt(channel);
|
||||
}
|
||||
else // let the handlers transfer more data
|
||||
{
|
||||
int chcr = hh->REG_CHCR();
|
||||
|
||||
DmaHandler handler = (chcr & DMA_CTRL_DIRECTION) ? hh->Write : hh->Read;
|
||||
|
||||
u32 ProcessedBytes = 0;
|
||||
s32 RequestedDelay = (handler) ? handler(channel, (u32*)iopPhysMem(hh->REG_MADR()), ch->ByteCount, &ProcessedBytes) : 0;
|
||||
|
||||
if(ProcessedBytes>0 && (!(chcr & DMA_CTRL_DIRECTION)))
|
||||
{
|
||||
psxCpu->Clear(hh->REG_MADR(), ProcessedBytes/4);
|
||||
}
|
||||
|
||||
int NextUpdateDelay = 100;
|
||||
if (RequestedDelay < 0) // error code
|
||||
{
|
||||
// TODO: ... What to do if the handler gives an error code? :P
|
||||
DevCon.Warning("ERROR on channel %d",channel);
|
||||
hh->REG_CHCR() &= ~DMA_CTRL_ACTIVE;
|
||||
RaiseDmaIrq(channel);
|
||||
hh->Interrupt(channel);
|
||||
}
|
||||
else if (ProcessedBytes > 0) // if not an error, continue transfer
|
||||
{
|
||||
//DevCon.WriteLn("Transfer channel %d, ProcessedBytes = %d",i,ProcessedBytes);
|
||||
hh->REG_MADR()+= ProcessedBytes;
|
||||
ch->ByteCount -= ProcessedBytes;
|
||||
|
||||
NextUpdateDelay = ProcessedBytes/2; // / ch->Width;
|
||||
}
|
||||
else if(RequestedDelay==0)
|
||||
DevCon.Warning("What now? :p"); // its ok as long as there's a delay requeste, autodma requires this.
|
||||
|
||||
if (RequestedDelay != 0) NextUpdateDelay = RequestedDelay;
|
||||
|
||||
// SPU2 adma early interrupts. PCSX2 likes those better currently.
|
||||
if((channel==4 || channel==7) && (ch->ByteCount<=0) && (ProcessedBytes <= 1024))
|
||||
{
|
||||
ch->NextUpdate = 0;
|
||||
}
|
||||
else
|
||||
ch->NextUpdate += NextUpdateDelay;
|
||||
|
||||
//ch->NextUpdate += NextUpdateDelay;
|
||||
}
|
||||
}
|
||||
|
||||
int nTarget = ch->NextUpdate;
|
||||
if(nTarget < 0) nTarget = 0;
|
||||
|
||||
if (nTarget<MinDelay)
|
||||
MinDelay = nTarget;
|
||||
}
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// IopDmaProcessChannel: Called regularly to update the active channels
|
||||
|
||||
void IopDmaUpdate(u32 elapsed)
|
||||
{
|
||||
s32 MinDelay=0;
|
||||
|
||||
do {
|
||||
MinDelay = 0x7FFFFFFF; // max possible value
|
||||
|
||||
// Unrolled
|
||||
//IopDmaProcessChannel<0>(elapsed, MinDelay);
|
||||
//IopDmaProcessChannel<1>(elapsed, MinDelay);
|
||||
//IopDmaProcessChannel<2>(elapsed, MinDelay);
|
||||
IopDmaProcessChannel<3>(elapsed, MinDelay);
|
||||
IopDmaProcessChannel<4>(elapsed, MinDelay);
|
||||
//IopDmaProcessChannel<5>(elapsed, MinDelay);
|
||||
//IopDmaProcessChannel<6>(elapsed, MinDelay);
|
||||
IopDmaProcessChannel<7>(elapsed, MinDelay);
|
||||
IopDmaProcessChannel<8>(elapsed, MinDelay);
|
||||
IopDmaProcessChannel<9>(elapsed, MinDelay);
|
||||
IopDmaProcessChannel<10>(elapsed, MinDelay);
|
||||
IopDmaProcessChannel<11>(elapsed, MinDelay);
|
||||
IopDmaProcessChannel<12>(elapsed, MinDelay);
|
||||
//IopDmaProcessChannel<13>(elapsed, MinDelay);
|
||||
|
||||
// reset elapsed time in case we loop
|
||||
elapsed=0;
|
||||
}
|
||||
while(MinDelay <= 0);
|
||||
|
||||
if(MinDelay<0x7FFFFFFF)
|
||||
{
|
||||
// tell the iop when to call this function again
|
||||
SetDmaUpdateTarget(MinDelay);
|
||||
}
|
||||
else
|
||||
{
|
||||
// bogus value so the function gets called again, not sure if it's necessary anymore
|
||||
SetDmaUpdateTarget(10000);
|
||||
}
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Error functions: dummy functions for unsupported dma "directions"
|
||||
|
||||
s32 CALLBACK errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
|
||||
{
|
||||
Console.Error("ERROR: Tried to read using DMA %d (%s). Ignoring.", channel, IopDmaHandlers[channel]);
|
||||
|
||||
*bytesProcessed = bytesLeft;
|
||||
return 0;
|
||||
}
|
||||
|
||||
s32 CALLBACK errDmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
|
||||
{
|
||||
Console.Error("ERROR: Tried to write using DMA %d (%s). Ignoring.", channel, IopDmaHandlers[channel]);
|
||||
|
||||
*bytesProcessed = bytesLeft;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void SaveStateBase::iopDmacFreeze()
|
||||
{
|
||||
FreezeTag("iopDmac");
|
||||
|
||||
Freeze(IopDmaChannels);
|
||||
|
||||
if( IsLoading() )
|
||||
{
|
||||
SetDmaUpdateTarget(10000); // Might be needed to kickstart the main updater :p
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -20,56 +20,12 @@
|
|||
|
||||
// defined in PS2Edefs.h
|
||||
|
||||
#ifdef ENABLE_NEW_IOPDMA
|
||||
|
||||
// unused for now
|
||||
class DmaBcrReg
|
||||
{
|
||||
public:
|
||||
union {
|
||||
struct {
|
||||
u32 size:16;
|
||||
u32 count:16;
|
||||
};
|
||||
u32 whole;
|
||||
};
|
||||
|
||||
DmaBcrReg(u32& value)
|
||||
{
|
||||
whole=value;
|
||||
}
|
||||
|
||||
u32 Bytes()
|
||||
{
|
||||
return 4*size*count;
|
||||
}
|
||||
};
|
||||
|
||||
#define DMA_CTRL_ACTIVE 0x01000000
|
||||
#define DMA_CTRL_DIRECTION 0x00000001
|
||||
|
||||
#define DMA_CHANNEL_MAX 14 /* ? */
|
||||
|
||||
extern void IopDmaStart(int channel);
|
||||
extern void IopDmaUpdate(u32 elapsed);
|
||||
|
||||
// external dma handlers
|
||||
extern s32 CALLBACK cdvdDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
|
||||
extern void CALLBACK cdvdDmaInterrupt(s32 channel);
|
||||
|
||||
//#else
|
||||
#endif
|
||||
|
||||
extern void psxDma2(u32 madr, u32 bcr, u32 chcr);
|
||||
extern void psxDma3(u32 madr, u32 bcr, u32 chcr);
|
||||
extern void psxDma6(u32 madr, u32 bcr, u32 chcr);
|
||||
#ifndef ENABLE_NEW_IOPDMA_SPU2
|
||||
extern void psxDma4(u32 madr, u32 bcr, u32 chcr);
|
||||
extern void psxDma7(u32 madr, u32 bcr, u32 chcr);
|
||||
#endif
|
||||
#ifndef ENABLE_NEW_IOPDMA_DEV9
|
||||
extern void psxDma8(u32 madr, u32 bcr, u32 chcr);
|
||||
#endif
|
||||
extern void psxDma9(u32 madr, u32 bcr, u32 chcr);
|
||||
extern void psxDma10(u32 madr, u32 bcr, u32 chcr);
|
||||
|
||||
|
|
|
|||
|
|
@ -194,11 +194,6 @@ enum IOPCountRegs
|
|||
} \
|
||||
}
|
||||
|
||||
#ifdef ENABLE_NEW_IOPDMA
|
||||
#define DmaExecNew(n) IopDmaStart(n);
|
||||
#define DmaExecNew2(n) IopDmaStart(n);
|
||||
#endif
|
||||
|
||||
struct dma_mbc
|
||||
{
|
||||
u32 madr;
|
||||
|
|
|
|||
|
|
@ -210,100 +210,6 @@ void SaveStateBase::sio2Freeze()
|
|||
/////////////////////////////////////////////////
|
||||
//////////////////////////////////////////// DMA
|
||||
/////////////////////////////////////////////////
|
||||
#ifdef ENABLE_NEW_IOPDMA
|
||||
|
||||
static int dmaBlockSize = 0x24;
|
||||
s32 CALLBACK sio2DmaStart(s32 channel, u32 madr, u32 bcr, u32 chcr)
|
||||
{
|
||||
dmaBlockSize = bcr & 0xFFFF;
|
||||
return 0; // continue
|
||||
}
|
||||
|
||||
s32 CALLBACK sio2DmaRead(s32 channel, u32* tdata, u32 bytesLeft, u32* bytesProcessed)
|
||||
{
|
||||
#ifdef ENABLE_NEW_IOPDMA_SIO
|
||||
u8* data = (u8*)tdata;
|
||||
|
||||
if(channel!=12)
|
||||
return -1;
|
||||
|
||||
sio2.recvIndex = 0; // Set To start; saqib
|
||||
|
||||
int read = 0;
|
||||
|
||||
// limit the burst length to avoid problems
|
||||
//if(bytesLeft>2048) bytesLeft = 2048;
|
||||
|
||||
while (bytesLeft > 0)
|
||||
{
|
||||
(*(data++)) = sio2_fifoOut();
|
||||
bytesLeft--;
|
||||
read++;
|
||||
if(sio2.recvIndex == sio2.packet.sendSize)
|
||||
{
|
||||
//read = bytesLeft;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
*bytesProcessed = read;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
s32 CALLBACK sio2DmaWrite(s32 channel, u32* tdata, u32 bytesLeft, u32* bytesProcessed)
|
||||
{
|
||||
#ifdef ENABLE_NEW_IOPDMA_SIO
|
||||
u8* data = (u8*)tdata;
|
||||
|
||||
if(channel!=11)
|
||||
return -1;
|
||||
|
||||
//int available = sio2_getFifoInFree();
|
||||
|
||||
// limit the burst length to avoid problems
|
||||
//if(bytesLeft>2048) bytesLeft = 2048;
|
||||
|
||||
int written = 0;
|
||||
|
||||
int bs = dmaBlockSize * 4;
|
||||
int bc = bytesLeft / bs;
|
||||
|
||||
//assert(ts == bytesLeft);
|
||||
|
||||
for(int j=0;j<bc;j++)
|
||||
{
|
||||
sio.count = 1;
|
||||
for(int i=0;i<bs;i++)
|
||||
{
|
||||
sio2_fifoIn(*(data++));
|
||||
written++;
|
||||
if((sio2.packet.sendSize == BUFSIZE))
|
||||
{
|
||||
//written = bytesLeft;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
*bytesProcessed = written;
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
void CALLBACK sio2DmaInterrupt(s32 channel)
|
||||
{
|
||||
#ifdef ENABLE_NEW_IOPDMA_SIO
|
||||
switch(channel) // Interrupts should always occur at the end
|
||||
{
|
||||
case 11: PSX_INT(IopEvt_Dma11,0); break;
|
||||
case 12: PSX_INT(IopEvt_Dma12,0); break;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
//#else
|
||||
#endif
|
||||
|
||||
void psxDma11(u32 madr, u32 bcr, u32 chcr) {
|
||||
unsigned int i, j;
|
||||
|
|
|
|||
|
|
@ -283,11 +283,7 @@ _SPU2open SPU2open;
|
|||
_SPU2write SPU2write;
|
||||
_SPU2reset SPU2reset;
|
||||
_SPU2read SPU2read;
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
_SPU2dmaRead SPU2dmaRead;
|
||||
_SPU2dmaWrite SPU2dmaWrite;
|
||||
_SPU2dmaInterrupt SPU2dmaInterrupt;
|
||||
#else
|
||||
|
||||
_SPU2readDMA4Mem SPU2readDMA4Mem;
|
||||
_SPU2writeDMA4Mem SPU2writeDMA4Mem;
|
||||
_SPU2interruptDMA4 SPU2interruptDMA4;
|
||||
|
|
@ -295,9 +291,9 @@ _SPU2readDMA7Mem SPU2readDMA7Mem;
|
|||
_SPU2writeDMA7Mem SPU2writeDMA7Mem;
|
||||
_SPU2setDMABaseAddr SPU2setDMABaseAddr;
|
||||
_SPU2interruptDMA7 SPU2interruptDMA7;
|
||||
|
||||
_SPU2ReadMemAddr SPU2ReadMemAddr;
|
||||
_SPU2WriteMemAddr SPU2WriteMemAddr;
|
||||
#endif
|
||||
_SPU2setupRecording SPU2setupRecording;
|
||||
_SPU2irqCallback SPU2irqCallback;
|
||||
|
||||
|
|
@ -315,14 +311,10 @@ _DEV9read32 DEV9read32;
|
|||
_DEV9write8 DEV9write8;
|
||||
_DEV9write16 DEV9write16;
|
||||
_DEV9write32 DEV9write32;
|
||||
#ifdef ENABLE_NEW_IOPDMA_DEV9
|
||||
_DEV9dmaRead DEV9dmaRead;
|
||||
_DEV9dmaWrite DEV9dmaWrite;
|
||||
_DEV9dmaInterrupt DEV9dmaInterrupt;
|
||||
#else
|
||||
|
||||
_DEV9readDMA8Mem DEV9readDMA8Mem;
|
||||
_DEV9writeDMA8Mem DEV9writeDMA8Mem;
|
||||
#endif
|
||||
|
||||
_DEV9irqCallback DEV9irqCallback;
|
||||
_DEV9irqHandler DEV9irqHandler;
|
||||
_DEV9async DEV9async;
|
||||
|
|
@ -583,11 +575,6 @@ static const LegacyApi_ReqMethod s_MethMessReq_SPU2[] =
|
|||
{ "SPU2reset", (vMeth**)&SPU2reset, SPU2_Reset },
|
||||
{ "SPU2write", (vMeth**)&SPU2write, NULL },
|
||||
{ "SPU2read", (vMeth**)&SPU2read, NULL },
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
{ "SPU2dmaRead", (vMeth**)&SPU2dmaRead, NULL },
|
||||
{ "SPU2dmaWrite", (vMeth**)&SPU2dmaWrite, NULL },
|
||||
{ "SPU2dmaInterrupt", (vMeth**)&SPU2dmaInterrupt, NULL },
|
||||
#else
|
||||
{ "SPU2readDMA4Mem", (vMeth**)&SPU2readDMA4Mem, NULL },
|
||||
{ "SPU2readDMA7Mem", (vMeth**)&SPU2readDMA7Mem, NULL },
|
||||
{ "SPU2writeDMA4Mem", (vMeth**)&SPU2writeDMA4Mem, NULL },
|
||||
|
|
@ -595,7 +582,6 @@ static const LegacyApi_ReqMethod s_MethMessReq_SPU2[] =
|
|||
{ "SPU2interruptDMA4", (vMeth**)&SPU2interruptDMA4,NULL },
|
||||
{ "SPU2interruptDMA7", (vMeth**)&SPU2interruptDMA7,NULL },
|
||||
{ "SPU2ReadMemAddr", (vMeth**)&SPU2ReadMemAddr, NULL },
|
||||
#endif
|
||||
{ "SPU2irqCallback", (vMeth**)&SPU2irqCallback, NULL },
|
||||
|
||||
{ NULL }
|
||||
|
|
@ -605,10 +591,8 @@ static const LegacyApi_OptMethod s_MethMessOpt_SPU2[] =
|
|||
{
|
||||
{ "SPU2setClockPtr", (vMeth**)&SPU2setClockPtr },
|
||||
{ "SPU2async", (vMeth**)&SPU2async },
|
||||
#ifndef ENABLE_NEW_IOPDMA_SPU2
|
||||
{ "SPU2WriteMemAddr", (vMeth**)&SPU2WriteMemAddr },
|
||||
{ "SPU2setDMABaseAddr", (vMeth**)&SPU2setDMABaseAddr},
|
||||
#endif
|
||||
{ "SPU2setupRecording", (vMeth**)&SPU2setupRecording},
|
||||
|
||||
{ NULL }
|
||||
|
|
@ -626,14 +610,8 @@ static const LegacyApi_ReqMethod s_MethMessReq_DEV9[] =
|
|||
{ "DEV9write8", (vMeth**)&DEV9write8, NULL },
|
||||
{ "DEV9write16", (vMeth**)&DEV9write16, NULL },
|
||||
{ "DEV9write32", (vMeth**)&DEV9write32, NULL },
|
||||
#ifdef ENABLE_NEW_IOPDMA_DEV9
|
||||
{ "DEV9dmaRead", (vMeth**)&DEV9dmaRead, NULL },
|
||||
{ "DEV9dmaWrite", (vMeth**)&DEV9dmaWrite, NULL },
|
||||
{ "DEV9dmaInterrupt", (vMeth**)&DEV9dmaInterrupt, NULL },
|
||||
#else
|
||||
{ "DEV9readDMA8Mem", (vMeth**)&DEV9readDMA8Mem, NULL },
|
||||
{ "DEV9writeDMA8Mem", (vMeth**)&DEV9writeDMA8Mem, NULL },
|
||||
#endif
|
||||
{ "DEV9irqCallback", (vMeth**)&DEV9irqCallback, NULL },
|
||||
{ "DEV9irqHandler", (vMeth**)&DEV9irqHandler, NULL },
|
||||
|
||||
|
|
@ -1242,12 +1220,8 @@ bool SysCorePlugins::OpenPlugin_SPU2()
|
|||
{
|
||||
if( SPU2open((void*)pDsp) ) return false;
|
||||
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
SPU2irqCallback( spu2Irq );
|
||||
#else
|
||||
SPU2irqCallback( spu2Irq, spu2DMA4Irq, spu2DMA7Irq );
|
||||
if( SPU2setDMABaseAddr != NULL ) SPU2setDMABaseAddr((uptr)iopMem->Main);
|
||||
#endif
|
||||
if( SPU2setClockPtr != NULL ) SPU2setClockPtr(&psxRegs.cycle);
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -220,9 +220,6 @@ SaveStateBase& SaveStateBase::FreezeInternals()
|
|||
FreezeTag( "IOP-Subsystems" );
|
||||
FreezeMem(iopMem->Sif, sizeof(iopMem->Sif)); // iop's sif memory (not really needed, but oh well)
|
||||
|
||||
#ifdef ENABLE_NEW_IOPDMA
|
||||
iopDmacFreeze();
|
||||
#endif
|
||||
psxRcntFreeze();
|
||||
sioFreeze();
|
||||
sio2Freeze();
|
||||
|
|
|
|||
|
|
@ -198,9 +198,6 @@ protected:
|
|||
void vuMicroFreeze();
|
||||
void vif0Freeze();
|
||||
void vif1Freeze();
|
||||
#ifdef ENABLE_NEW_IOPDMA
|
||||
void iopDmacFreeze();
|
||||
#endif
|
||||
void sifFreeze();
|
||||
void ipuFreeze();
|
||||
void ipuDmaFreeze();
|
||||
|
|
|
|||
|
|
@ -300,19 +300,11 @@ static __fi T _HwRead_16or32_Page1( u32 addr )
|
|||
// Soon-to-be outdated SPU2 DMA hack (spu2 manages its own DMA MADR).
|
||||
//
|
||||
mcase(0x1f8010C0):
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
ret = psxHu32(addr);
|
||||
#else
|
||||
ret = SPU2ReadMemAddr(0);
|
||||
#endif
|
||||
break;
|
||||
|
||||
mcase(0x1f801500):
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
ret = psxHu32(addr);
|
||||
#else
|
||||
ret = SPU2ReadMemAddr(1);
|
||||
#endif
|
||||
break;
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -347,16 +347,12 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
|
|||
// as asinine as that may seem).
|
||||
//
|
||||
mcase(0x1f8010C0):
|
||||
#ifndef ENABLE_NEW_IOPDMA_SPU2
|
||||
SPU2WriteMemAddr( 0, val );
|
||||
#endif
|
||||
HW_DMA4_MADR = val;
|
||||
break;
|
||||
|
||||
mcase(0x1f801500):
|
||||
#ifndef ENABLE_NEW_IOPDMA_SPU2
|
||||
SPU2WriteMemAddr( 1, val );
|
||||
#endif
|
||||
HW_DMA7_MADR = val;
|
||||
break;
|
||||
|
||||
|
|
@ -395,11 +391,7 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
|
|||
|
||||
mcase(0x1f8010c8): // DMA4 CHCR -- SPU2 Core 1
|
||||
psxHu(addr) = val;
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
DmaExecNew(4);
|
||||
#else
|
||||
DmaExec(4);
|
||||
#endif
|
||||
break;
|
||||
|
||||
mcase(0x1f8010e8): // DMA6 CHCR -- OT clear
|
||||
|
|
@ -409,20 +401,12 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
|
|||
|
||||
mcase(0x1f801508): // DMA7 CHCR -- SPU2 core 2
|
||||
psxHu(addr) = val;
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
DmaExecNew2(7);
|
||||
#else
|
||||
DmaExec2(7);
|
||||
#endif
|
||||
break;
|
||||
|
||||
mcase(0x1f801518): // DMA8 CHCR -- DEV9
|
||||
psxHu(addr) = val;
|
||||
#ifdef ENABLE_NEW_IOPDMA_DEV9
|
||||
DmaExecNew2(8);
|
||||
#else
|
||||
DmaExec2(8);
|
||||
#endif
|
||||
break;
|
||||
|
||||
mcase(0x1f801528): // DMA9 CHCR -- SIF0
|
||||
|
|
@ -438,20 +422,12 @@ static __fi void _HwWrite_16or32_Page1( u32 addr, T val )
|
|||
|
||||
mcase(0x1f801548): // DMA11 CHCR -- SIO2 IN
|
||||
psxHu(addr) = val;
|
||||
#ifdef ENABLE_NEW_IOPDMA_SIO
|
||||
DmaExecNew2(11);
|
||||
#else
|
||||
DmaExec2(11);
|
||||
#endif
|
||||
break;
|
||||
|
||||
mcase(0x1f801558): // DMA12 CHCR -- SIO2 OUT
|
||||
psxHu(addr) = val;
|
||||
#ifdef ENABLE_NEW_IOPDMA_SIO
|
||||
DmaExecNew2(12);
|
||||
#else
|
||||
DmaExec2(12);
|
||||
#endif
|
||||
break;
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
|
|
|||
|
|
@ -237,7 +237,6 @@ DEV9write32(u32 addr, u32 value)
|
|||
}
|
||||
}
|
||||
|
||||
//#ifdef ENABLE_NEW_IOPDMA_DEV9
|
||||
EXPORT_C_(s32)
|
||||
DEV9dmaRead(s32 channel, u32 *data, u32 bytesLeft, u32 *bytesProcessed)
|
||||
{
|
||||
|
|
@ -262,7 +261,7 @@ DEV9dmaInterrupt(s32 channel)
|
|||
{
|
||||
// See above.
|
||||
}
|
||||
//#else
|
||||
|
||||
EXPORT_C_(void)
|
||||
DEV9readDMA8Mem(u32 *pMem, int size)
|
||||
{
|
||||
|
|
@ -277,7 +276,6 @@ DEV9writeDMA8Mem(u32 *pMem, int size)
|
|||
// See above.
|
||||
g_plugin_log.WriteLn("Writing DMA8 Mem.");
|
||||
}
|
||||
//#endif
|
||||
|
||||
EXPORT_C_(void)
|
||||
DEV9irqCallback(DEV9callback callback)
|
||||
|
|
|
|||
|
|
@ -97,7 +97,6 @@ void V_Core::LogAutoDMA(FILE *fp)
|
|||
|
||||
void V_Core::AutoDMAReadBuffer(int mode) //mode: 0= split stereo; 1 = do not split stereo
|
||||
{
|
||||
#ifndef ENABLE_NEW_IOPDMA_SPU2
|
||||
int spos = ((InputPosRead + 0xff) & 0x100); //starting position of the free buffer
|
||||
|
||||
LogAutoDMA(Index ? ADMA7LogFile : ADMA4LogFile);
|
||||
|
|
@ -130,12 +129,10 @@ void V_Core::AutoDMAReadBuffer(int mode) //mode: 0= split stereo; 1 = do not spl
|
|||
}
|
||||
// See ReadInput at mixer.cpp for explanation on the commented out lines
|
||||
//
|
||||
#endif
|
||||
}
|
||||
|
||||
void V_Core::StartADMAWrite(u16 *pMem, u32 sz)
|
||||
{
|
||||
#ifndef ENABLE_NEW_IOPDMA_SPU2
|
||||
int size = (sz) & (~511);
|
||||
|
||||
if (MsgAutoDMA())
|
||||
|
|
@ -172,7 +169,6 @@ void V_Core::StartADMAWrite(u16 *pMem, u32 sz)
|
|||
DMAICounter = 1;
|
||||
}
|
||||
TADR = MADR + (size << 1);
|
||||
#endif
|
||||
}
|
||||
|
||||
// HACKFIX: The BIOS breaks if we check the IRQA for both cores when issuing DMA writes. The
|
||||
|
|
@ -317,7 +313,6 @@ void V_Core::PlainDMAWrite(u16 *pMem, u32 size)
|
|||
|
||||
void V_Core::DoDMAread(u16 *pMem, u32 size)
|
||||
{
|
||||
#ifndef ENABLE_NEW_IOPDMA_SPU2
|
||||
TSA &= 0xfffff;
|
||||
|
||||
u32 buff1end = TSA + size;
|
||||
|
|
@ -375,12 +370,10 @@ void V_Core::DoDMAread(u16 *pMem, u32 size)
|
|||
Regs.STATX &= ~0x80;
|
||||
//Regs.ATTR |= 0x30;
|
||||
TADR = MADR + (size << 1);
|
||||
#endif
|
||||
}
|
||||
|
||||
void V_Core::DoDMAwrite(u16 *pMem, u32 size)
|
||||
{
|
||||
#ifndef ENABLE_NEW_IOPDMA_SPU2
|
||||
DMAPtr = pMem;
|
||||
|
||||
if (size < 2) {
|
||||
|
|
@ -420,212 +413,4 @@ void V_Core::DoDMAwrite(u16 *pMem, u32 size)
|
|||
}
|
||||
Regs.STATX &= ~0x80;
|
||||
//Regs.ATTR |= 0x30;
|
||||
#endif
|
||||
}
|
||||
|
||||
s32 V_Core::NewDmaRead(u32 *data, u32 bytesLeft, u32 *bytesProcessed)
|
||||
{
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
bool DmaStarting = !DmaStarted;
|
||||
DmaStarted = true;
|
||||
|
||||
TSA &= 0xfffff;
|
||||
|
||||
u16 *pMem = (u16 *)data;
|
||||
|
||||
u32 buff1end = TSA + bytesLeft;
|
||||
u32 buff2end = 0;
|
||||
if (buff1end > 0x100000) {
|
||||
buff2end = buff1end - 0x100000;
|
||||
buff1end = 0x100000;
|
||||
}
|
||||
|
||||
const u32 buff1size = (buff1end - TSA);
|
||||
memcpy(pMem, GetMemPtr(TSA), buff1size * 2);
|
||||
|
||||
// Note on TSA's position after our copy finishes:
|
||||
// IRQA should be measured by the end of the writepos+0x20. But the TDA
|
||||
// should be written back at the precise endpoint of the xfer.
|
||||
|
||||
u32 TDA;
|
||||
|
||||
if (buff2end > 0) {
|
||||
// second branch needs cleared:
|
||||
// It starts at the beginning of memory and moves forward to buff2end
|
||||
|
||||
memcpy(&pMem[buff1size], GetMemPtr(0), buff2end * 2);
|
||||
|
||||
TDA = (buff2end + 0x20) & 0xfffff;
|
||||
|
||||
// Flag interrupt? If IRQA occurs between start and dest, flag it.
|
||||
// Important: Test both core IRQ settings for either DMA!
|
||||
// Note: Because this buffer wraps, we use || instead of &&
|
||||
|
||||
for (int i = 0; i < 2; i++) {
|
||||
if (Cores[i].IRQEnable && (Cores[i].IRQA > TSA || Cores[i].IRQA <= TDA)) {
|
||||
SetIrqCall(i);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
// Buffer doesn't wrap/overflow!
|
||||
// Just set the TDA and check for an IRQ...
|
||||
|
||||
TDA = (buff1end + 0x20) & 0xfffff;
|
||||
|
||||
// Flag interrupt? If IRQA occurs between start and dest, flag it.
|
||||
// Important: Test both core IRQ settings for either DMA!
|
||||
|
||||
for (int i = 0; i < 2; i++) {
|
||||
if (Cores[i].IRQEnable && (Cores[i].IRQA > TSA) && (Cores[i].IRQA <= TDA)) {
|
||||
SetIrqCall(i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TSA = TDA;
|
||||
|
||||
Regs.STATX &= ~0x80;
|
||||
Regs.STATX |= 0x400;
|
||||
|
||||
#endif
|
||||
*bytesProcessed = bytesLeft;
|
||||
return 0;
|
||||
}
|
||||
|
||||
s32 V_Core::NewDmaWrite(u32 *data, u32 bytesLeft, u32 *bytesProcessed)
|
||||
{
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
bool DmaStarting = !DmaStarted;
|
||||
DmaStarted = true;
|
||||
|
||||
if (bytesLeft < 2) {
|
||||
// execute interrupt code early
|
||||
NewDmaInterrupt();
|
||||
|
||||
*bytesProcessed = bytesLeft;
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (IsDevBuild) {
|
||||
DebugCores[Index].lastsize = bytesLeft;
|
||||
DebugCores[Index].dmaFlag = 1;
|
||||
}
|
||||
|
||||
TSA &= 0xfffff;
|
||||
|
||||
bool adma_enable = ((AutoDMACtrl & (Index + 1)) == (Index + 1));
|
||||
|
||||
if (adma_enable) {
|
||||
TSA &= 0x1fff;
|
||||
|
||||
if (MsgAutoDMA() && DmaStarting)
|
||||
ConLog("* SPU2-X: DMA%c AutoDMA Transfer of %d bytes to %x (%02x %x %04x).\n",
|
||||
GetDmaIndexChar(), bytesLeft << 1, TSA, DMABits, AutoDMACtrl, (~Regs.ATTR) & 0x7fff);
|
||||
|
||||
u32 processed = 0;
|
||||
while ((AutoDmaFree > 0) && (bytesLeft >= 0x400)) {
|
||||
// copy block
|
||||
|
||||
LogAutoDMA(Index ? ADMA7LogFile : ADMA4LogFile);
|
||||
|
||||
// HACKFIX!! DMAPtr can be invalid after a savestate load, so the savestate just forces it
|
||||
// to NULL and we ignore it here. (used to work in old VM editions of PCSX2 with fixed
|
||||
// addressing, but new PCSX2s have dynamic memory addressing).
|
||||
|
||||
s16 *mptr = (s16 *)data;
|
||||
|
||||
if (false) //(mode)
|
||||
{
|
||||
//memcpy((ADMATempBuffer+(InputPosWrite<<1)),mptr,0x400);
|
||||
memcpy(GetMemPtr(0x2000 + (Index << 10) + InputPosWrite), mptr, 0x400);
|
||||
mptr += 0x200;
|
||||
|
||||
// Flag interrupt? If IRQA occurs between start and dest, flag it.
|
||||
// Important: Test both core IRQ settings for either DMA!
|
||||
|
||||
u32 dummyTSA = 0x2000 + (Index << 10) + InputPosWrite;
|
||||
u32 dummyTDA = 0x2000 + (Index << 10) + InputPosWrite + 0x200;
|
||||
|
||||
for (int i = 0; i < 2; i++) {
|
||||
if (Cores[i].IRQEnable && (Cores[i].IRQA > dummyTSA) && (Cores[i].IRQA <= dummyTDA)) {
|
||||
SetIrqCall(i);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
//memcpy((ADMATempBuffer+InputPosWrite),mptr,0x200);
|
||||
memcpy(GetMemPtr(0x2000 + (Index << 10) + InputPosWrite), mptr, 0x200);
|
||||
mptr += 0x100;
|
||||
|
||||
// Flag interrupt? If IRQA occurs between start and dest, flag it.
|
||||
// Important: Test both core IRQ settings for either DMA!
|
||||
|
||||
u32 dummyTSA = 0x2000 + (Index << 10) + InputPosWrite;
|
||||
u32 dummyTDA = 0x2000 + (Index << 10) + InputPosWrite + 0x100;
|
||||
|
||||
for (int i = 0; i < 2; i++) {
|
||||
if (Cores[i].IRQEnable && (Cores[i].IRQA > dummyTSA) && (Cores[i].IRQA <= dummyTDA)) {
|
||||
SetIrqCall(i);
|
||||
}
|
||||
}
|
||||
|
||||
//memcpy((ADMATempBuffer+InputPosWrite+0x200),mptr,0x200);
|
||||
memcpy(GetMemPtr(0x2200 + (Index << 10) + InputPosWrite), mptr, 0x200);
|
||||
mptr += 0x100;
|
||||
|
||||
// Flag interrupt? If IRQA occurs between start and dest, flag it.
|
||||
// Important: Test both core IRQ settings for either DMA!
|
||||
|
||||
dummyTSA = 0x2200 + (Index << 10) + InputPosWrite;
|
||||
dummyTDA = 0x2200 + (Index << 10) + InputPosWrite + 0x100;
|
||||
|
||||
for (int i = 0; i < 2; i++) {
|
||||
if (Cores[i].IRQEnable && (Cores[i].IRQA > dummyTSA) && (Cores[i].IRQA <= dummyTDA)) {
|
||||
SetIrqCall(i);
|
||||
}
|
||||
}
|
||||
}
|
||||
// See ReadInput at mixer.cpp for explanation on the commented out lines
|
||||
//
|
||||
|
||||
InputPosWrite = (InputPosWrite + 0x100) & 0x1ff;
|
||||
AutoDmaFree -= 0x200;
|
||||
processed += 0x400;
|
||||
bytesLeft -= 0x400;
|
||||
}
|
||||
|
||||
if (processed == 0) {
|
||||
*bytesProcessed = 0;
|
||||
return 768 * 15; // pause a bit
|
||||
} else {
|
||||
*bytesProcessed = processed;
|
||||
return 0; // auto pause
|
||||
}
|
||||
} else {
|
||||
if (MsgDMA() && DmaStarting)
|
||||
ConLog("* SPU2-X: DMA%c Transfer of %d bytes to %x (%02x %x %04x).\n",
|
||||
GetDmaIndexChar(), bytesLeft, TSA, DMABits, AutoDMACtrl, (~Regs.ATTR) & 0x7fff);
|
||||
|
||||
if (bytesLeft > 2048)
|
||||
bytesLeft = 2048;
|
||||
|
||||
// TODO: Sliced transfers?
|
||||
PlainDMAWrite((u16 *)data, bytesLeft / 2);
|
||||
}
|
||||
Regs.STATX &= ~0x80;
|
||||
Regs.STATX |= 0x400;
|
||||
|
||||
#endif
|
||||
*bytesProcessed = bytesLeft;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void V_Core::NewDmaInterrupt()
|
||||
{
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
FileLog("[%10d] SPU2 interruptDMA4\n", Cycles);
|
||||
Regs.STATX |= 0x80;
|
||||
Regs.STATX &= ~0x400;
|
||||
//Regs.ATTR &= ~0x30;
|
||||
DmaStarted = false;
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -218,40 +218,6 @@ CALLBACK SPU2setLogDir(const char *dir)
|
|||
CfgSetLogDir(dir);
|
||||
}
|
||||
|
||||
EXPORT_C_(s32)
|
||||
SPU2dmaRead(s32 channel, u32 *data, u32 bytesLeft, u32 *bytesProcessed)
|
||||
{
|
||||
if (channel == 4)
|
||||
return Cores[0].NewDmaRead(data, bytesLeft, bytesProcessed);
|
||||
else
|
||||
return Cores[1].NewDmaRead(data, bytesLeft, bytesProcessed);
|
||||
}
|
||||
|
||||
EXPORT_C_(s32)
|
||||
SPU2dmaWrite(s32 channel, u32 *data, u32 bytesLeft, u32 *bytesProcessed)
|
||||
{
|
||||
if (channel == 4)
|
||||
return Cores[0].NewDmaWrite(data, bytesLeft, bytesProcessed);
|
||||
else
|
||||
return Cores[1].NewDmaWrite(data, bytesLeft, bytesProcessed);
|
||||
}
|
||||
|
||||
EXPORT_C_(void)
|
||||
SPU2dmaInterrupt(s32 channel)
|
||||
{
|
||||
if (channel == 4)
|
||||
return Cores[0].NewDmaInterrupt();
|
||||
else
|
||||
return Cores[1].NewDmaInterrupt();
|
||||
}
|
||||
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
EXPORT_C_(void)
|
||||
SPU2irqCallback(void (*SPU2callback)())
|
||||
{
|
||||
_irqcallback = SPU2callback;
|
||||
}
|
||||
#else
|
||||
EXPORT_C_(void)
|
||||
SPU2irqCallback(void (*SPU2callback)(), void (*DMA4callback)(), void (*DMA7callback)())
|
||||
{
|
||||
|
|
@ -259,7 +225,6 @@ SPU2irqCallback(void (*SPU2callback)(), void (*DMA4callback)(), void (*DMA7callb
|
|||
dma4callback = DMA4callback;
|
||||
dma7callback = DMA7callback;
|
||||
}
|
||||
#endif
|
||||
|
||||
EXPORT_C_(void)
|
||||
CALLBACK SPU2readDMA4Mem(u16 *pMem, u32 size) // size now in 16bit units
|
||||
|
|
|
|||
|
|
@ -48,18 +48,6 @@ SPU2write(u32 mem, u16 value);
|
|||
EXPORT_C_(u16)
|
||||
SPU2read(u32 mem);
|
||||
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
EXPORT_C_(s32)
|
||||
SPU2dmaRead(s32 channel, u32 *data, u32 bytesLeft, u32 *bytesProcessed);
|
||||
EXPORT_C_(s32)
|
||||
SPU2dmaWrite(s32 channel, u32 *data, u32 bytesLeft, u32 *bytesProcessed);
|
||||
EXPORT_C_(void)
|
||||
SPU2dmaInterrupt(s32 channel);
|
||||
|
||||
// dma irq callbacks not needed anymore, they are handled by the dmac
|
||||
EXPORT_C_(void)
|
||||
SPU2irqCallback(void (*SPU2callback)());
|
||||
#else
|
||||
// These defines are useless and gcc-4.6 complain about redefinition
|
||||
// so we remove them on linux
|
||||
#ifndef __POSIX__
|
||||
|
|
@ -85,7 +73,6 @@ SPU2WriteMemAddr(int core, u32 value);
|
|||
EXPORT_C_(void)
|
||||
SPU2irqCallback(void (*SPU2callback)(), void (*DMA4callback)(), void (*DMA7callback)());
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// extended funcs
|
||||
// if start is 1, starts recording spu2 data, else stops
|
||||
|
|
@ -114,13 +101,11 @@ extern u8 callirq;
|
|||
|
||||
extern void (*_irqcallback)();
|
||||
|
||||
#ifndef ENABLE_NEW_IOPDMA_SPU2
|
||||
extern void (*dma4callback)();
|
||||
extern void (*dma7callback)();
|
||||
|
||||
extern s16 *input_data;
|
||||
extern u32 input_data_ptr;
|
||||
#endif
|
||||
|
||||
extern double srate_pv;
|
||||
|
||||
|
|
|
|||
|
|
@ -66,10 +66,6 @@ StereoOut32 V_Core::ReadInput_HiFi()
|
|||
// One of these seems wrong, they should be the same. Since standard ADMA checks too I'm assuming that as default. -- air
|
||||
|
||||
if ((InputPosRead == 0x100) || (InputPosRead >= 0x200)) {
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
// WARNING: Assumes this to be in the same thread as the dmas
|
||||
AutoDmaFree += 0x200;
|
||||
#else
|
||||
AdmaInProgress = 0;
|
||||
if (InputDataLeft >= 0x200) {
|
||||
#ifdef PCM24_S1_INTERLEAVE
|
||||
|
|
@ -102,7 +98,6 @@ StereoOut32 V_Core::ReadInput_HiFi()
|
|||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
InputPosRead &= 0x1ff;
|
||||
}
|
||||
return retval;
|
||||
|
|
@ -134,10 +129,6 @@ StereoOut32 V_Core::ReadInput()
|
|||
InputPosRead++;
|
||||
|
||||
if (AutoDMACtrl & (Index + 1) && (InputPosRead == 0x100 || InputPosRead == 0x200)) {
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
// WARNING: Assumes this to be in the same thread as the dmas
|
||||
AutoDmaFree += 0x200;
|
||||
#else
|
||||
AdmaInProgress = 0;
|
||||
if (InputDataLeft >= 0x200) {
|
||||
//u8 k=InputDataLeft>=InputDataProgress;
|
||||
|
|
@ -170,7 +161,6 @@ StereoOut32 V_Core::ReadInput()
|
|||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
InputPosRead &= 0x1ff;
|
||||
return retval;
|
||||
|
|
|
|||
|
|
@ -149,16 +149,12 @@ void dummy1()
|
|||
|
||||
void dummy4()
|
||||
{
|
||||
#ifndef ENABLE_NEW_IOPDMA_SPU2
|
||||
SPU2interruptDMA4();
|
||||
#endif
|
||||
}
|
||||
|
||||
void dummy7()
|
||||
{
|
||||
#ifndef ENABLE_NEW_IOPDMA_SPU2
|
||||
SPU2interruptDMA7();
|
||||
#endif
|
||||
}
|
||||
|
||||
u64 HighResFrequency()
|
||||
|
|
@ -223,7 +219,6 @@ BOOL WINAPI HandlerRoutine(DWORD dwCtrlType)
|
|||
EXPORT_C_(void)
|
||||
s2r_replay(HWND hwnd, HINSTANCE hinst, LPSTR filename, int nCmdShow)
|
||||
{
|
||||
#ifndef ENABLE_NEW_IOPDMA_SPU2
|
||||
int events = 0;
|
||||
|
||||
Running = true;
|
||||
|
|
@ -332,6 +327,5 @@ Finish:
|
|||
#endif
|
||||
|
||||
replay_mode = false;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -39,26 +39,23 @@ EXPORTS
|
|||
SPU2write @15
|
||||
SPU2read @16
|
||||
SPU2async @17
|
||||
SPU2dmaRead @18
|
||||
SPU2dmaWrite @19
|
||||
SPU2dmaInterrupt @20
|
||||
|
||||
SPU2readDMA4Mem @21
|
||||
SPU2writeDMA4Mem @22
|
||||
SPU2readDMA7Mem @23
|
||||
SPU2writeDMA7Mem @24
|
||||
SPU2interruptDMA4 @25
|
||||
SPU2interruptDMA7 @26
|
||||
SPU2readDMA4Mem @18
|
||||
SPU2writeDMA4Mem @19
|
||||
SPU2readDMA7Mem @20
|
||||
SPU2writeDMA7Mem @21
|
||||
SPU2interruptDMA4 @22
|
||||
SPU2interruptDMA7 @23
|
||||
|
||||
SPU2irqCallback @27
|
||||
SPU2setupRecording @28
|
||||
SPU2irqCallback @24
|
||||
SPU2setupRecording @25
|
||||
|
||||
SPU2ReadMemAddr @29
|
||||
SPU2WriteMemAddr @30
|
||||
SPU2ReadMemAddr @26
|
||||
SPU2WriteMemAddr @27
|
||||
|
||||
SPU2setClockPtr @31
|
||||
SPU2setDMABaseAddr @32
|
||||
SPU2setClockPtr @28
|
||||
SPU2setDMABaseAddr @29
|
||||
|
||||
SPU2replay = s2r_replay @33
|
||||
SPU2replay = s2r_replay @30
|
||||
|
||||
SPU2reset @34
|
||||
SPU2reset @31
|
||||
|
|
|
|||
|
|
@ -411,7 +411,6 @@ __forceinline void TimeUpdate(u32 cClocks)
|
|||
_irqcallback();
|
||||
}
|
||||
|
||||
#ifndef ENABLE_NEW_IOPDMA_SPU2
|
||||
//Update DMA4 interrupt delay counter
|
||||
if (Cores[0].DMAICounter > 0) {
|
||||
Cores[0].DMAICounter -= TickInterval;
|
||||
|
|
@ -439,7 +438,6 @@ __forceinline void TimeUpdate(u32 cClocks)
|
|||
Cores[1].MADR += TickInterval << 1;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
dClocks -= TickInterval;
|
||||
lClocks += TickInterval;
|
||||
|
|
|
|||
|
|
@ -184,7 +184,6 @@ void CALLBACK SPU2interruptDMA(int channel)
|
|||
spu2stat_set_80(channel);
|
||||
}
|
||||
|
||||
#ifndef ENABLE_NEW_IOPDMA_SPU2
|
||||
void CALLBACK SPU2writeDMA4Mem(u16* pMem, int size)
|
||||
{
|
||||
LOG_CALLBACK("SPU2writeDMA4Mem()\n");
|
||||
|
|
@ -208,22 +207,3 @@ void CALLBACK SPU2interruptDMA7()
|
|||
LOG_CALLBACK("SPU2interruptDMA7()\n");
|
||||
SPU2interruptDMA(7);
|
||||
}
|
||||
#else
|
||||
s32 CALLBACK SPU2dmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
|
||||
{
|
||||
// Needs implementation.
|
||||
return 0;
|
||||
}
|
||||
|
||||
s32 CALLBACK SPU2dmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
|
||||
{
|
||||
// Needs implementation.
|
||||
return 0;
|
||||
}
|
||||
|
||||
void CALLBACK SPU2dmaInterrupt(s32 channel)
|
||||
{
|
||||
LOG_CALLBACK("SPU2dmaInterruptDMA()\n");
|
||||
SPU2interruptDMA(channel);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -95,10 +95,8 @@ void InitADSR();
|
|||
|
||||
// functions of main emu, called on spu irq
|
||||
void (*irqCallbackSPU2)()=0;
|
||||
#ifndef ENABLE_NEW_IOPDMA_SPU2
|
||||
void (*irqCallbackDMA4)()=0;
|
||||
void (*irqCallbackDMA7)()=0;
|
||||
#endif
|
||||
|
||||
uptr g_pDMABaseAddr=0;
|
||||
u32 RateTable[160];
|
||||
|
|
@ -393,9 +391,7 @@ void CALLBACK SPU2async(u32 cycle)
|
|||
if (SPUCycles - SPUStartCycle[1] >= SPUTargetCycle[1])
|
||||
{
|
||||
interrupt &= ~(1<<2);
|
||||
#ifndef ENABLE_NEW_IOPDMA_SPU2
|
||||
irqCallbackDMA7();
|
||||
#endif
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -405,9 +401,7 @@ void CALLBACK SPU2async(u32 cycle)
|
|||
if (SPUCycles - SPUStartCycle[0] >= SPUTargetCycle[0])
|
||||
{
|
||||
interrupt &= ~(1<<1);
|
||||
#ifndef ENABLE_NEW_IOPDMA_SPU2
|
||||
irqCallbackDMA4();
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -595,12 +589,10 @@ void MixChannels(s32 channel)
|
|||
interrupt &= ~(0x2 * (channel + 1));
|
||||
WARN_LOG("Stopping double interrupt DMA7\n");
|
||||
}
|
||||
#ifndef ENABLE_NEW_IOPDMA_SPU2
|
||||
if (channel == 0)
|
||||
irqCallbackDMA4();
|
||||
else
|
||||
irqCallbackDMA7();
|
||||
#endif
|
||||
|
||||
}
|
||||
if (channel == 1) Adma->Enabled = 2;
|
||||
|
|
@ -1148,13 +1140,6 @@ void CALLBACK SPU2setDMABaseAddr(uptr baseaddr)
|
|||
g_pDMABaseAddr = baseaddr;
|
||||
}
|
||||
|
||||
#ifdef ENABLE_NEW_IOPDMA_SPU2
|
||||
void CALLBACK SPU2irqCallback(void (*SPU2callback)())
|
||||
{
|
||||
LOG_CALLBACK("SPU2irqCallback()\n");
|
||||
irqCallbackSPU2 = SPU2callback;
|
||||
}
|
||||
#else
|
||||
void CALLBACK SPU2irqCallback(void (*SPU2callback)(),void (*DMA4callback)(),void (*DMA7callback)())
|
||||
{
|
||||
LOG_CALLBACK("SPU2irqCallback()\n");
|
||||
|
|
@ -1162,7 +1147,6 @@ void CALLBACK SPU2irqCallback(void (*SPU2callback)(),void (*DMA4callback)(),void
|
|||
irqCallbackDMA4 = DMA4callback;
|
||||
irqCallbackDMA7 = DMA7callback;
|
||||
}
|
||||
#endif
|
||||
|
||||
s32 CALLBACK SPU2test()
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue