mirror of https://github.com/PCSX2/pcsx2.git
A few changes to Sif, SPR, and Gif I've had sitting around.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2037 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42
parent
29e8fe94e9
commit
cf4719019d
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@ -30,15 +30,13 @@ using std::min;
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// A three-way toggle used to determine if the GIF is stalling (transferring) or done (finished).
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// Should be a gifstate_t rather then int, but I don't feel like possibly interfering with savestates right now.
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static int gifstate = GIF_STATE_READY;
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static bool gifempty = false;
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//static u64 s_gstag = 0; // used for querying the last tag
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// This should be a bool. Next time I feel like breaking the save state, it will be. --arcum42
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static bool gspath3done = false;
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static u32 gscycles = 0, prevcycles = 0, mfifocycles = 0;
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static u32 gifqwc = 0;
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bool gifmfifoirq = false;
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static bool gifmfifoirq = false;
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static __forceinline void clearFIFOstuff(bool full)
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{
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@ -60,8 +58,9 @@ __forceinline void gsInterrupt()
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return;
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}
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if ((vif1.cmd & 0x7f) == 0x51)
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if ((vif1.cmd & 0x7f) == 0x51) // DIRECTHL
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{
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// Not waiting for the end of the Gif transfer.
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if (Path3progress != IMAGE_MODE) vif1Regs->stat.VGW = 0;
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}
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@ -141,7 +140,7 @@ static __forceinline void GIFchain()
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static __forceinline bool checkTieBit(u32* &ptag)
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{
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if (gif->chcr.TIE && (Tag::IRQ(ptag))) //Check TIE bit of CHCR and IRQ bit of tag
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if (gif->chcr.TIE && (Tag::IRQ(ptag)))
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{
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GIF_LOG("dmaIrq Set");
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gspath3done = true;
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@ -151,28 +150,30 @@ static __forceinline bool checkTieBit(u32* &ptag)
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return false;
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}
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static __forceinline bool ReadTag(u32* &ptag, u32 &id)
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static __forceinline u32* ReadTag(u32 &id)
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{
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ptag = (u32*)dmaGetAddr(gif->tadr); //Set memory pointer to TADR
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u32* ptag = (u32*)dmaGetAddr(gif->tadr); //Set memory pointer to TADR
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if (!(Tag::Transfer("Gif", gif, ptag))) return NULL;
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if (!(Tag::Transfer("Gif", gif, ptag))) return false;
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gif->madr = ptag[1]; //MADR = ADDR field
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id = Tag::Id(ptag); //ID for DmaChain copied from bit 28 of the tag
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id = Tag::Id(ptag);
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gscycles += 2; // Add 1 cycles from the QW read for the tag
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gspath3done = hwDmacSrcChainWithStack(gif, id);
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return true;
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return ptag;
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}
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static __forceinline void ReadTag2(u32* &ptag)
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static __forceinline u32* ReadTag2()
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{
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ptag = (u32*)dmaGetAddr(gif->tadr); //Set memory pointer to TADR
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u32* ptag = (u32*)dmaGetAddr(gif->tadr); //Set memory pointer to TADR
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Tag::UnsafeTransfer(gif, ptag);
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gif->madr = ptag[1];
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gspath3done = hwDmacSrcChainWithStack(gif, Tag::Id(ptag));
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return ptag;
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}
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void GIFdma()
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@ -209,6 +210,7 @@ void GIFdma()
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//Path2 gets priority in intermittent mode
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if ((gifRegs->stat.P1Q || (vif1.cmd & 0x7f) == 0x50) && gifRegs->mode.IMT && (Path3progress == IMAGE_MODE))
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{
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// We are in image mode doing DIRECTHL, Path 1 is in queue, and in intermittant mode.
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GIF_LOG("Waiting VU %x, PATH2 %x, GIFMODE %x Progress %x", gifRegs->stat.P1Q, (vif1.cmd & 0x7f), gifRegs->mode._u32, Path3progress);
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CPU_INT(2, 16);
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return;
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@ -220,7 +222,8 @@ void GIFdma()
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{
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if ((gif->chcr.MOD == CHAIN_MODE) && gif->chcr.STR)
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{
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if (!ReadTag(ptag, id)) return;
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ptag = ReadTag(id);
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if (ptag == NULL) return;
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GIF_LOG("PTH3 MASK gifdmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx", ptag[1], ptag[0], gif->qwc, id, gif->madr);
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//Check TIE bit of CHCR and IRQ bit of tag
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@ -257,7 +260,8 @@ void GIFdma()
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if ((gif->chcr.MOD == CHAIN_MODE) && (!gspath3done)) // Chain Mode
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{
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if (!ReadTag(ptag, id)) return;
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ptag = ReadTag(id);
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if (ptag == NULL) return;
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GIF_LOG("gifdmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx", ptag[1], ptag[0], gif->qwc, id, gif->madr);
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if (dmacRegs->ctrl.STD == STD_GIF)
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@ -312,7 +316,7 @@ void dmaGIF()
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gspath3done = false; // For some reason this doesn't clear? So when the system starts the thread, we will clear it :)
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gifRegs->stat.P3Q = 1;
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gifRegs->stat.FQC |= 0x10;// FQC=31, hack ;) ( 31? 16! arcum42) [used to be 0xE00; // OPH=1 | APATH=3]
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gifRegs->stat.FQC |= 0x10; // hack ;)
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clearFIFOstuff(true);
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@ -325,9 +329,7 @@ void dmaGIF()
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if ((gif->qwc == 0) && (gif->chcr.MOD != NORMAL_MODE))
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{
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u32 *ptag;
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ReadTag2(ptag);
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u32* ptag = ReadTag2();
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GIF_LOG("gifdmaChain %8.8x_%8.8x size=%d, id=%d, addr=%lx", ptag[1], ptag[0], gif->qwc, (ptag[0] >> 28), gif->madr);
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checkTieBit(ptag);
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@ -401,10 +403,12 @@ static __forceinline int mfifoGIFchain()
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}
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else
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{
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int mfifoqwc = gif->qwc;
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int mfifoqwc;
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u32 *pMem = (u32*)dmaGetAddr(gif->madr);
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if (pMem == NULL) return -1;
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mfifoqwc = WRITERING_DMA(pMem, mfifoqwc);
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mfifoqwc = WRITERING_DMA(pMem, gif->qwc);
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mfifocycles += (mfifoqwc) * 2; /* guessing */
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}
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@ -420,7 +424,6 @@ void mfifoGIFtransfer(int qwc)
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{
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u32 *ptag;
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int id;
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u32 temp = 0;
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mfifocycles = 0;
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gifmfifoirq = false;
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@ -428,8 +431,11 @@ void mfifoGIFtransfer(int qwc)
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if(qwc > 0 )
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{
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gifqwc += qwc;
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if (gifstate != GIF_STATE_EMPTY) return;
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if (!(gifstate & GIF_STATE_EMPTY)) return;
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// if (gifempty == false) return;
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gifstate &= ~GIF_STATE_EMPTY;
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gifempty = false;
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}
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GIF_LOG("mfifoGIFtransfer %x madr %x, tadr %x", gif->chcr._u32, gif->madr, gif->tadr);
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@ -441,12 +447,13 @@ void mfifoGIFtransfer(int qwc)
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//if( gifqwc > 1 ) DevCon.WriteLn("gif mfifo tadr==madr but qwc = %d", gifqwc);
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hwDmacIrq(DMAC_MFIFO_EMPTY);
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gifstate |= GIF_STATE_EMPTY;
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gifempty = true;
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return;
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}
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gif->tadr = qwctag(gif->tadr);
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ptag = (u32*)dmaGetAddr(gif->tadr);
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ptag = (u32*)dmaGetAddr(gif->tadr);
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Tag::UnsafeTransfer(gif, ptag);
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gif->madr = ptag[1];
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@ -472,11 +479,13 @@ void mfifoGIFtransfer(int qwc)
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break;
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case TAG_NEXT: // Next - Transfer QWC following tag. TADR = ADDR
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temp = gif->madr; //Temporarily Store ADDR
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{
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u32 temp = gif->madr; //Temporarily Store ADDR
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gif->madr = qwctag(gif->tadr + 16); //Set MADR to QW following the tag
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gif->tadr = temp; //Copy temporarily stored ADDR to Tag
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gifstate = GIF_STATE_READY;
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break;
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}
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case TAG_REF: // Ref - Transfer QWC from ADDR field
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case TAG_REFS: // Refs - Transfer QWC from ADDR field (Stall Control)
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@ -507,7 +516,7 @@ void mfifoGIFtransfer(int qwc)
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}
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FreezeRegs(0);
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if ((gif->qwc == 0) && (gifstate == GIF_STATE_DONE)) gifstate = GIF_STATE_STALL;
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if ((gif->qwc == 0) && (gifstate & GIF_STATE_DONE)) gifstate = GIF_STATE_STALL;
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CPU_INT(11,mfifocycles);
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SPR_LOG("mfifoGIFtransfer end %x madr %x, tadr %x", gif->chcr._u32, gif->madr, gif->tadr);
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@ -515,6 +524,7 @@ void mfifoGIFtransfer(int qwc)
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void gifMFIFOInterrupt()
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{
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Console.WriteLn("gifMFIFOInterrupt");
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mfifocycles = 0;
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if (Path3progress == STOPPED_MODE)
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@ -543,13 +553,15 @@ void gifMFIFOInterrupt()
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return;
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}
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if (gifstate != GIF_STATE_STALL)
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if (!(gifstate & GIF_STATE_STALL))
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{
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if (gifqwc <= 0)
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{
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//Console.WriteLn("Empty");
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hwDmacIrq(DMAC_MFIFO_EMPTY);
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gifstate |= GIF_STATE_EMPTY;
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gifempty = true;
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gifRegs->stat.IMT = 0;
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return;
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}
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@ -558,7 +570,7 @@ void gifMFIFOInterrupt()
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}
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#ifdef PCSX2_DEVBUILD
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if (gifstate == GIF_STATE_READY || gif->qwc > 0)
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if ((gifstate & GIF_STATE_READY) || (gif->qwc > 0))
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{
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Console.Error("gifMFIFO Panic > Shouldn't go here!");
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return;
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@ -587,6 +599,6 @@ void SaveStateBase::gifFreeze()
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Freeze( gifqwc );
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Freeze( gspath3done );
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Freeze( gscycles );
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//Freeze(gifempty);
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// Note: mfifocycles is not a persistent var, so no need to save it here.
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}
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@ -134,10 +134,21 @@ enum DMAChcrAddresses
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enum DMATadrAddresses
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{
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HWx_DMA0_TADR = 0x1f80108c,
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HWx_DMA1_TADR = 0x1f80109c,
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HWx_DMA2_TADR = 0x1f8010ac,
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HWx_DMA3_TADR = 0x1f8010bc,
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HWx_DMA4_TADR = 0x1f8010cc,
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HWx_DMA9_TADR = 0x1f80152c
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HWx_DMA5_TADR = 0x1f8010dc,
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HWx_DMA6_TADR = 0x1f8010ec,
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HWx_DMA7_TADR = 0x1f80150c,
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HWx_DMA8_TADR = 0x1f80151c,
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HWx_DMA9_TADR = 0x1f80152c,
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HWx_DMA10_TADR = 0x1f80153c,
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HWx_DMA11_TADR = 0x1f80154c,
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HWx_DMA12_TADR = 0x1f80155c
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};
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/* Registers for the IOP Counters */
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enum IOPCountRegs
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{
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@ -66,14 +66,14 @@ int _SPR0chain()
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else
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mfifotransferred += spr0->qwc;
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hwMFIFOWrite(spr0->madr, (u8*)&PS2MEM_SCRATCH[spr0->sadr & 0x3fff], spr0->qwc << 4);
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hwMFIFOWrite(spr0->madr, &psSu8(spr0->sadr), spr0->qwc << 4);
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spr0->madr += spr0->qwc << 4;
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spr0->madr = dmacRegs->rbor.ADDR + (spr0->madr & dmacRegs->rbsr.RMSK);
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break;
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case NO_MFD:
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case MFD_RESERVED:
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memcpy_fast((u8*)pMem, &PS2MEM_SCRATCH[spr0->sadr & 0x3fff], spr0->qwc << 4);
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memcpy_fast((u8*)pMem, &psSu8(spr0->sadr), spr0->qwc << 4);
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// clear VU mem also!
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TestClearVUs(spr0->madr, spr0->qwc << 2); // Wtf is going on here? AFAIK, only VIF should affect VU micromem (cottonvibes)
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@ -115,7 +115,7 @@ void _SPR0interleave()
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{
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case MFD_VIF1:
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case MFD_GIF:
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hwMFIFOWrite(spr0->madr, (u8*)&PS2MEM_SCRATCH[spr0->sadr & 0x3fff], spr0->qwc << 4);
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hwMFIFOWrite(spr0->madr, &psSu8(spr0->sadr), spr0->qwc << 4);
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mfifotransferred += spr0->qwc;
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break;
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@ -123,7 +123,7 @@ void _SPR0interleave()
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case MFD_RESERVED:
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// clear VU mem also!
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TestClearVUs(spr0->madr, spr0->qwc << 2);
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memcpy_fast((u8*)pMem, &PS2MEM_SCRATCH[spr0->sadr & 0x3fff], spr0->qwc << 4);
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memcpy_fast((u8*)pMem, &psSu8(spr0->sadr), spr0->qwc << 4);
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break;
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}
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spr0->sadr += spr0->qwc * 16;
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@ -163,7 +163,7 @@ static __forceinline void _dmaSPR0()
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return;
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}
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// Destination Chain Mode
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ptag = (u32*) & PS2MEM_SCRATCH[spr0->sadr & 0x3fff];
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ptag = &psSu32(spr0->sadr);
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spr0->sadr += 16;
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Tag::UnsafeTransfer(spr0, ptag);
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@ -186,25 +186,26 @@ static __forceinline void _dmaSPR0()
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break;
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case TAG_CNT: // CNT - Transfer QWC following the tag.
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done = FALSE;
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done = false;
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break;
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case TAG_END: // End - Transfer QWC following the tag
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done = TRUE;
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done = true;
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break;
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}
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SPR0chain();
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if (spr0->chcr.TIE && Tag::IRQ(ptag)) //Check TIE bit of CHCR and IRQ bit of tag
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{
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//Console.WriteLn("SPR0 TIE");
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done = TRUE;
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done = true;
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}
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spr0finished = done;
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if (!done)
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{
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ptag = (u32*) & PS2MEM_SCRATCH[spr0->sadr & 0x3fff]; //Set memory pointer to SADR
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ptag = &psSu32(spr0->sadr); //Set memory pointer to SADR
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CPU_INT(8, ((u16)ptag[0]) / BIAS); // the lower 16bits of the tag / BIAS);
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return;
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}
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@ -229,6 +230,16 @@ void SPRFROMinterrupt()
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{
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switch (dmacRegs->ctrl.MFD)
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{
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case MFD_VIF1: // Most common case.
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{
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if ((spr0->madr & ~dmacRegs->rbsr.RMSK) != dmacRegs->rbor.ADDR) Console.WriteLn("VIF MFIFO Write outside MFIFO area");
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spr0->madr = dmacRegs->rbor.ADDR + (spr0->madr & dmacRegs->rbsr.RMSK);
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//Console.WriteLn("mfifoVIF1transfer %x madr %x, tadr %x", vif1ch->chcr._u32, vif1ch->madr, vif1ch->tadr);
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mfifoVIF1transfer(mfifotransferred);
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mfifotransferred = 0;
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if (vif1ch->chcr.STR) return;
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break;
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}
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case MFD_GIF:
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{
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if ((spr0->madr & ~dmacRegs->rbsr.RMSK) != dmacRegs->rbor.ADDR) Console.WriteLn("GIF MFIFO Write outside MFIFO area");
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@ -239,16 +250,6 @@ void SPRFROMinterrupt()
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if (gif->chcr.STR) return;
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break;
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}
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case MFD_VIF1:
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{
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if ((spr0->madr & ~psHu32(DMAC_RBSR)) != psHu32(DMAC_RBOR)) Console.WriteLn("VIF MFIFO Write outside MFIFO area");
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spr0->madr = dmacRegs->rbor.ADDR + (spr0->madr & dmacRegs->rbsr.RMSK);
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//Console.WriteLn("mfifoVIF1transfer %x madr %x, tadr %x", vif1ch->chcr._u32, vif1ch->madr, vif1ch->tadr);
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mfifoVIF1transfer(mfifotransferred);
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mfifotransferred = 0;
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if (vif1ch->chcr.STR) return;
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break;
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}
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default:
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break;
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}
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@ -258,7 +259,6 @@ void SPRFROMinterrupt()
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hwDmacIrq(DMAC_FROM_SPR);
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}
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void dmaSPR0() // fromSPR
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{
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SPR_LOG("dmaSPR0 chcr = %lx, madr = %lx, qwc = %lx, sadr = %lx",
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@ -267,7 +267,7 @@ void dmaSPR0() // fromSPR
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if ((spr0->chcr.MOD == CHAIN_MODE) && spr0->qwc == 0)
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{
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u32 *ptag;
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ptag = (u32*) & PS2MEM_SCRATCH[spr0->sadr & 0x3fff]; //Set memory pointer to SADR
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ptag = &psSu32(spr0->sadr); //Set memory pointer to SADR
|
||||
CPU_INT(8, (ptag[0] & 0xffff) / BIAS);
|
||||
return;
|
||||
}
|
||||
|
|
@ -279,7 +279,7 @@ void dmaSPR0() // fromSPR
|
|||
|
||||
__forceinline static void SPR1transfer(u32 *data, int size)
|
||||
{
|
||||
memcpy_fast(&PS2MEM_SCRATCH[spr1->sadr & 0x3fff], (u8*)data, size << 2);
|
||||
memcpy_fast(&psSu8(spr1->sadr), (u8*)data, size << 2);
|
||||
|
||||
spr1->sadr += size << 2;
|
||||
}
|
||||
|
|
@ -305,7 +305,6 @@ __forceinline void SPR1chain()
|
|||
spr1->qwc = 0;
|
||||
}
|
||||
|
||||
|
||||
void _SPR1interleave()
|
||||
{
|
||||
int qwc = spr1->qwc;
|
||||
|
|
@ -322,7 +321,7 @@ void _SPR1interleave()
|
|||
spr1->qwc = std::min(tqwc, qwc);
|
||||
qwc -= spr1->qwc;
|
||||
pMem = (u32*)dmaGetAddr(spr1->madr);
|
||||
memcpy_fast(&PS2MEM_SCRATCH[spr1->sadr & 0x3fff], (u8*)pMem, spr1->qwc << 4);
|
||||
memcpy_fast(&psSu8(spr1->sadr), (u8*)pMem, spr1->qwc << 4);
|
||||
spr1->sadr += spr1->qwc * 16;
|
||||
spr1->madr += (sqwc + spr1->qwc) * 16;
|
||||
}
|
||||
|
|
@ -405,11 +404,10 @@ void _dmaSPR1() // toSPR work function
|
|||
break;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void dmaSPR1() // toSPR
|
||||
{
|
||||
|
||||
SPR_LOG("dmaSPR1 chcr = 0x%x, madr = 0x%x, qwc = 0x%x\n"
|
||||
" tadr = 0x%x, sadr = 0x%x",
|
||||
spr1->chcr._u32, spr1->madr, spr1->qwc,
|
||||
|
|
|
|||
|
|
@ -365,7 +365,7 @@ void memSavingState::FreezeMem( void* data, int size )
|
|||
|
||||
void memSavingState::FreezeAll()
|
||||
{
|
||||
// 90% of all savestates fit in under 45 megs (and require more than 43 megs, so migght as well...)
|
||||
// 90% of all savestates fit in under 45 megs (and require more than 43 megs, so might as well...)
|
||||
m_memory.ChunkSize = ReallocThreshold;
|
||||
m_memory.MakeRoomFor( MemoryBaseAllocSize );
|
||||
|
||||
|
|
|
|||
|
|
@ -201,8 +201,8 @@ __forceinline void SIF0Dma()
|
|||
else
|
||||
SIF_LOG(" EE SIF interrupt");
|
||||
|
||||
eesifbusy[0] = false;
|
||||
CPU_INT(5, cycles*BIAS);
|
||||
eesifbusy[0] = false;
|
||||
done = true;
|
||||
}
|
||||
else if (sif0.fifoSize >= 4) // Read a tag
|
||||
|
|
@ -277,9 +277,7 @@ __forceinline void SIF1Dma()
|
|||
ptag = _dmaGetAddr(sif1dma, sif1dma->tadr, DMAC_SIF1);
|
||||
if (ptag == NULL) return;
|
||||
|
||||
|
||||
sif1dma->chcr._u32 = (sif1dma->chcr._u32 & 0xFFFF) | ((*ptag) & 0xFFFF0000); // Copy the tag
|
||||
sif1dma->qwc = (u16)ptag[0];
|
||||
Tag::UnsafeTransfer(sif1dma, ptag);
|
||||
|
||||
if (sif1dma->chcr.TTE)
|
||||
{
|
||||
|
|
@ -287,6 +285,11 @@ __forceinline void SIF1Dma()
|
|||
SIF1write(ptag + 2, 2);
|
||||
}
|
||||
|
||||
if ((sif1dma->chcr.TIE) && (Tag::IRQ(ptag)))
|
||||
{
|
||||
Console.WriteLn("SIF1 TIE");
|
||||
sif1.end = 1;
|
||||
}
|
||||
//sif1.chain = 1;
|
||||
|
||||
switch (Tag::Id(ptag))
|
||||
|
|
@ -327,11 +330,6 @@ __forceinline void SIF1Dma()
|
|||
default:
|
||||
Console.WriteLn("Bad addr1 source chain");
|
||||
}
|
||||
if ((sif1dma->chcr.TIE) && (Tag::IRQ(ptag)))
|
||||
{
|
||||
Console.WriteLn("SIF1 TIE");
|
||||
sif1.end = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
else // There's some data ready to transfer into the fifo..
|
||||
|
|
|
|||
Loading…
Reference in New Issue