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Experimental stuff, "newly discovered" flag from some old ps1 source code (so yeah not new, just I had never seen it) which appears to indicate the status of the spu's internal transfer queue (both dma and non-dma transfer styles). 

Only applied for DMAs, and only in the new dmac code. Please tell if it breaks anything! and also if it fixes anything!


git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2566 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
gigaherz 2010-02-06 01:35:36 +00:00
parent 0de9848106
commit cdb5de009b
3 changed files with 17 additions and 11 deletions
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14
plugins/spu2-x/src/Dma.cpp
View File

@ -500,7 +500,7 @@ s32 V_Core::NewDmaRead(u32* data, u32 bytesLeft, u32* bytesProcessed)
TSA = TDA & 0xFFFFF; TSA = TDA & 0xFFFFF;
Regs.STATX &= ~0x80; Regs.STATX &= ~0x80;
//Regs.ATTR |= 0x30; Regs.STATX |= 0x400;
#endif #endif
*bytesProcessed = bytesLeft; *bytesProcessed = bytesLeft;
@ -558,8 +558,8 @@ s32 V_Core::NewDmaWrite(u32* data, u32 bytesLeft, u32* bytesProcessed)
// Flag interrupt? If IRQA occurs between start and dest, flag it. // Flag interrupt? If IRQA occurs between start and dest, flag it.
// Important: Test both core IRQ settings for either DMA! // Important: Test both core IRQ settings for either DMA!
int dummyTSA = 0x2000+(Index<<10)+InputPosWrite; u32 dummyTSA = 0x2000+(Index<<10)+InputPosWrite;
int dummyTDA = 0x2000+(Index<<10)+InputPosWrite+0x200; u32 dummyTDA = 0x2000+(Index<<10)+InputPosWrite+0x200;
for( int i=0; i<2; i++ ) for( int i=0; i<2; i++ )
{ {
@ -579,8 +579,8 @@ s32 V_Core::NewDmaWrite(u32* data, u32 bytesLeft, u32* bytesProcessed)
// Flag interrupt? If IRQA occurs between start and dest, flag it. // Flag interrupt? If IRQA occurs between start and dest, flag it.
// Important: Test both core IRQ settings for either DMA! // Important: Test both core IRQ settings for either DMA!
int dummyTSA = 0x2000+(Index<<10)+InputPosWrite; u32 dummyTSA = 0x2000+(Index<<10)+InputPosWrite;
int dummyTDA = 0x2000+(Index<<10)+InputPosWrite+0x100; u32 dummyTDA = 0x2000+(Index<<10)+InputPosWrite+0x100;
for( int i=0; i<2; i++ ) for( int i=0; i<2; i++ )
{ {
@ -643,7 +643,8 @@ s32 V_Core::NewDmaWrite(u32* data, u32 bytesLeft, u32* bytesProcessed)
PlainDMAWrite((u16*)data,bytesLeft/2); PlainDMAWrite((u16*)data,bytesLeft/2);
} }
Regs.STATX &= ~0x80; Regs.STATX &= ~0x80;
//Regs.ATTR |= 0x30; Regs.STATX |= 0x400;
#endif #endif
*bytesProcessed = bytesLeft; *bytesProcessed = bytesLeft;
return 0; return 0;
@ -654,6 +655,7 @@ void V_Core::NewDmaInterrupt()
#ifdef ENABLE_NEW_IOPDMA_SPU2 #ifdef ENABLE_NEW_IOPDMA_SPU2
FileLog("[%10d] SPU2 interruptDMA4\n",Cycles); FileLog("[%10d] SPU2 interruptDMA4\n",Cycles);
Regs.STATX |= 0x80; Regs.STATX |= 0x80;
Regs.STATX &= ~0x400;
//Regs.ATTR &= ~0x30; //Regs.ATTR &= ~0x30;
DmaStarted = false; DmaStarted = false;
#endif #endif

3
plugins/spu2-x/src/defs.h
View File

@ -417,8 +417,7 @@ struct V_Core
u8 CoreEnabled; u8 CoreEnabled;
u8 AttrBit0; u8 AttrBit0;
u8 AttrBit4; u8 DmaMode;
u8 AttrBit5;
// new dma only // new dma only
bool DmaStarted; bool DmaStarted;

11
plugins/spu2-x/src/spu2sys.cpp
View File

@ -847,7 +847,7 @@ static void __fastcall RegWrite_Core( u16 value )
{ {
bool irqe = thiscore.IRQEnable; bool irqe = thiscore.IRQEnable;
int bit0 = thiscore.AttrBit0; int bit0 = thiscore.AttrBit0;
//int bit4 = thiscore.AttrBit4; u8 oldDmaMode = thiscore.DmaMode;
if( ((value>>15)&1) && (!thiscore.CoreEnabled) && (thiscore.InitDelay==0) ) // on init/reset if( ((value>>15)&1) && (!thiscore.CoreEnabled) && (thiscore.InitDelay==0) ) // on init/reset
{ {
@ -871,8 +871,7 @@ static void __fastcall RegWrite_Core( u16 value )
thiscore.AttrBit0 =(value>> 0) & 0x01; //1 bit thiscore.AttrBit0 =(value>> 0) & 0x01; //1 bit
thiscore.DMABits =(value>> 1) & 0x07; //3 bits thiscore.DMABits =(value>> 1) & 0x07; //3 bits
thiscore.AttrBit4 =(value>> 4) & 0x01; //1 bit thiscore.DmaMode =(value>> 4) & 0x03; //2 bit (not necessary, we get the direction from the iop)
thiscore.AttrBit5 =(value>> 5) & 0x01; //1 bit
thiscore.IRQEnable =(value>> 6) & 0x01; //1 bit thiscore.IRQEnable =(value>> 6) & 0x01; //1 bit
thiscore.FxEnable =(value>> 7) & 0x01; //1 bit thiscore.FxEnable =(value>> 7) & 0x01; //1 bit
thiscore.NoiseClk =(value>> 8) & 0x3f; //6 bits thiscore.NoiseClk =(value>> 8) & 0x3f; //6 bits
@ -881,6 +880,12 @@ static void __fastcall RegWrite_Core( u16 value )
thiscore.CoreEnabled=(value>>15) & 0x01; //1 bit thiscore.CoreEnabled=(value>>15) & 0x01; //1 bit
thiscore.Regs.ATTR =value&0x7fff; thiscore.Regs.ATTR =value&0x7fff;
if(oldDmaMode != thiscore.DmaMode)
{
// FIXME... maybe: if this mode was cleared in the middle of a DMA, should we interrupt it?
thiscore.Regs.STATX &= ~0x400; // ready to transfer
}
if(value&0x000E) if(value&0x000E)
{ {
ConLog(" * SPU2: Core %d ATTR unknown bits SET! value=%04x\n",core,value); ConLog(" * SPU2: Core %d ATTR unknown bits SET! value=%04x\n",core,value);