mirror of https://github.com/PCSX2/pcsx2.git
- Better IOP synchronization when using the X2 and X3 IOP hacks. Still not perfect, though (music may run a little behind or ahead of the games). I'll look into it tomorrow first thing.
- IOP Counter optimizations. The IOP counter code now only updates counters actually being modified instead of blindly updating all counters. git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@259 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
Jake.Stine
Gregory Hainaut
parent
1bd9f54c9b
commit
cd653603e5
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@ -48,53 +48,57 @@ static void psxRcntReset32(u32 index) {
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psxRcntUpd32(index);
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}
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static void psxRcntSet() {
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__forceinline static void _rcntSet( int i, int bitwise )
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{
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// thanks to being forceinline'd, this conditional will always be optimized
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// to a constant by VC (confirmed via disassembler):
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u64 overflowCap = (bitwise==32) ? 0x100000000 : 0x10000;
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u64 c;
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#ifdef _DEBUG
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if(bitwise == 32)
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assert( (i < 6) && (i >= 3) );
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else
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assert( i < 3 );
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#endif
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if(psxCounters[i].rate == PSXHBLANK) return;
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c = (u64)((overflowCap - psxCounters[i].count) * psxCounters[i].rate) - (psxRegs.cycle - psxCounters[i].sCycleT);
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if (c < psxNextCounter) psxNextCounter = (u32)c;
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//if((psxCounters[i].mode & 0x10) == 0 || psxCounters[i].target > 0xffff) continue;
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c = (u64)((psxCounters[i].target - psxCounters[i].count) * psxCounters[i].rate) - (psxRegs.cycle - psxCounters[i].sCycleT);
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if (c < psxNextCounter) psxNextCounter = (u32)c;
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}
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static void psxRcntSet() {
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int i;
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psxNextCounter = 0xffffffff;
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psxNextsCounter = psxRegs.cycle;
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for (i=0; i<3; i++) {
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if(psxCounters[i].rate == PSXHBLANK) continue;
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c = (u64)((0x10000 - psxCounters[i].count) * psxCounters[i].rate) - (psxRegs.cycle - psxCounters[i].sCycleT);
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if (c < psxNextCounter) {
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psxNextCounter = (u32)c;
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}
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//if((psxCounters[i].mode & 0x10) == 0 || psxCounters[i].target > 0xffff) continue;
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c = (u64)((psxCounters[i].target - psxCounters[i].count) * psxCounters[i].rate) - (psxRegs.cycle - psxCounters[i].sCycleT);
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if (c < psxNextCounter) {
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psxNextCounter = (u32)c;
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}
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_rcntSet( i, 16 );
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}
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for (i=3; i<6; i++) {
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if(psxCounters[i].rate == PSXHBLANK) continue;
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c = (u64)((0x100000000 - psxCounters[i].count) * psxCounters[i].rate) - (psxRegs.cycle - psxCounters[i].sCycleT);
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if (c < psxNextCounter) {
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psxNextCounter = (u32)c;
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}
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//if((psxCounters[i].mode & 0x10) == 0 || psxCounters[i].target > 0xffffffff) continue;
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c = (u64)((psxCounters[i].target - psxCounters[i].count) * psxCounters[i].rate) - (psxRegs.cycle - psxCounters[i].sCycleT);
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if (c < psxNextCounter) {
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psxNextCounter = (u32)c;
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}
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_rcntSet( i, 32 );
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}
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if(SPU2async)
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{
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c = (u32)(psxCounters[6].CycleT - (psxRegs.cycle - psxCounters[6].sCycleT)) ;
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u32 c = (psxCounters[6].CycleT - (psxRegs.cycle - psxCounters[6].sCycleT)) ;
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if (c < psxNextCounter) {
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psxNextCounter = (u32)c;
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psxNextCounter = c;
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}
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}
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if(USBasync)
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{
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c = (u32)(psxCounters[7].CycleT - (psxRegs.cycle - psxCounters[7].sCycleT)) ;
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u32 c = (psxCounters[7].CycleT - (psxRegs.cycle - psxCounters[7].sCycleT)) ;
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if (c < psxNextCounter) {
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psxNextCounter = (u32)c;
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psxNextCounter = c;
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}
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}
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}
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@ -224,8 +228,9 @@ void psxCheckStartGate(int counter) { //Check Gate events when Vsync Starts
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}*/
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}
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if(counter < 3){ //Gates for 16bit counters
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if((psxCounters[i].mode & 0x1) == 0) return; //Ignore Gate
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if(counter < 3){ //Gates for 16bit counters
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//SysPrintf("PSX Gate %x\n", i);
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switch((psxCounters[i].mode & 0x6) >> 1) {
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case 0x0: //GATE_ON_count
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@ -250,7 +255,6 @@ void psxCheckStartGate(int counter) { //Check Gate events when Vsync Starts
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}
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if(counter >= 3){ //Gates for 32bit counters
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if((psxCounters[i].mode & 0x1) == 0) return; //Ignore Gate
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//SysPrintf("PSX Gate %x\n", i);
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switch((psxCounters[i].mode & 0x6) >> 1) {
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case 0x0: //GATE_ON_count
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@ -411,7 +415,6 @@ void _testRcnt32(int i) {
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}
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extern int spu2interrupts[2];
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void psxRcntUpdate() {
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int i;
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u32 change = 0;
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@ -441,7 +444,8 @@ void psxRcntUpdate() {
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if(SPU2async)
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{
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if((psxRegs.cycle - psxCounters[6].sCycleT) >= psxCounters[6].CycleT){
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if((psxRegs.cycle - psxCounters[6].sCycleT) >= psxCounters[6].CycleT)
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{
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SPU2async(psxRegs.cycle - psxCounters[6].sCycleT);
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//SysPrintf("cycles sent to SPU2 %x\n", psxRegs.cycle - psxCounters[6].sCycleT);
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psxCounters[6].sCycleT = psxRegs.cycle;
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@ -480,7 +484,7 @@ void psxRcntWcount16(int index, u32 value) {
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}
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if(psxCounters[index].rate == PSXHBLANK)SysPrintf("Whoops 16 IOP\n");
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psxRcntUpd16(index);
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psxRcntSet();
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_rcntSet( index, 16 );
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}
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void psxRcntWcount32(int index, u32 value) {
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@ -503,7 +507,7 @@ void psxRcntWcount32(int index, u32 value) {
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}
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if(psxCounters[index].rate == PSXHBLANK)SysPrintf("Whoops 32 IOP\n");
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//psxRcntUpd32(index);
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psxRcntSet();
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_rcntSet( index, 32 );
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}
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void psxRcnt0Wmode(u32 value) {
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@ -511,9 +515,11 @@ void psxRcnt0Wmode(u32 value) {
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PSXCNT_LOG("IOP writeCmode[0] = %lx\n", value);
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#endif
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#if 0
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if (value & 0x1c00) {
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SysPrintf("Counter 0 Value write %x\n", value & 0x1c00);
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}
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#endif
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psxCounters[0].mode = value;
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psxCounters[0].mode|= 0x0400;
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@ -537,7 +543,7 @@ void psxRcnt0Wmode(u32 value) {
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//SysPrintf("IOP 16 Correcting target 0 after mode write\n");
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psxCounters[0].target &= 0xffff;
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}
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psxRcntSet();
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_rcntSet( 0, 16 );
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//}
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}
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@ -572,7 +578,7 @@ void psxRcnt1Wmode(u32 value) {
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//SysPrintf("IOP 16 Correcting target 1 after mode write\n");
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psxCounters[1].target &= 0xffff;
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}
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psxRcntSet();
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_rcntSet( 1, 16 );
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//}
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}
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@ -610,7 +616,7 @@ void psxRcnt2Wmode(u32 value) {
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//SysPrintf("IOP 16 Correcting target 2 after mode write\n");
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psxCounters[2].target &= 0xffff;
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}
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psxRcntSet();
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_rcntSet( 2, 16 );
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}
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void psxRcnt3Wmode(u32 value) {
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@ -644,7 +650,7 @@ void psxRcnt3Wmode(u32 value) {
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//SysPrintf("IOP 32 Correcting target 3 after mode write\n");
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psxCounters[3].target &= 0xffffffff;
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}
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psxRcntSet();
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_rcntSet( 3, 32 );
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//}
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}
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@ -689,7 +695,7 @@ void psxRcnt4Wmode(u32 value) {
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//SysPrintf("IOP 32 Correcting target 4 after mode write\n");
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psxCounters[4].target &= 0xffffffff;
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}
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psxRcntSet();
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_rcntSet( 4, 32 );
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}
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void psxRcnt5Wmode(u32 value) {
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@ -733,7 +739,7 @@ void psxRcnt5Wmode(u32 value) {
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//SysPrintf("IOP 32 Correcting target 5 after mode write\n");
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psxCounters[5].target &= 0xffffffff;
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}
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psxRcntSet();
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_rcntSet( 5, 32 );
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}
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void psxRcntWtarget16(int index, u32 value) {
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@ -746,7 +752,7 @@ void psxRcntWtarget16(int index, u32 value) {
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psxCounters[index].target += 0x1000000000;
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}
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psxRcntSet();
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_rcntSet( index, 16 );
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}
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void psxRcntWtarget32(int index, u32 value) {
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@ -761,7 +767,7 @@ void psxRcntWtarget32(int index, u32 value) {
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psxCounters[index].target += 0x1000000000;
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}
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psxRcntSet();
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_rcntSet( index, 32 );
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}
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u16 psxRcntRcount16(int index) {
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@ -25,7 +25,6 @@
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// Dma8 in PsxSpd.c
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// Dma11/12 in PsxSio2.c
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//static int spudmaenable[2];
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int spu2interrupts[2];
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int iopsifbusy[2] = { 0, 0 };
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void psxDma4(u32 madr, u32 bcr, u32 chcr) { // SPU
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int size;
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@ -161,13 +161,16 @@ static void _psxTestInterrupts() {
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PSX_TESTINT(21, usbInterrupt);
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}
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#define IOP_WAIT_CYCLE 256 // was (and is again!) 64
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// Higher Wait cycle values should, in theory, reduce IOP overhead without much
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// drawback. The IOP is almost always forced to perform branch tests at import-
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// ant intervals regardless of this value (such as counter or irq events, hsyncs,
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// etc.)
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#define IOP_WAIT_CYCLE 256
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void psxBranchTest()
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{
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// g_psxNextBranchCycle is initialized for us by iPsxBranchTest.
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g_psxNextBranchCycle = psxRegs.cycle;
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if( EEsCycle >= 0 ) g_psxNextBranchCycle += IOP_WAIT_CYCLE;
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//if( EEsCycle >= 0 ) g_psxNextBranchCycle += IOP_WAIT_CYCLE;
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if ((int)(psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
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psxRcntUpdate();
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@ -435,6 +435,12 @@ void cpuBranchTest()
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//#endif
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_cpuTestTIMR();
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// Signal for an immediate branch test! This is important! The IOP must
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// be able to act on the state the EE has given it before executing any
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// additional code. Otherwise things won't be anywhere near "in sync."
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psxBranchTest();
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EEsCycle += cpuRegs.cycle - EEoCycle;
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EEoCycle = cpuRegs.cycle;
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@ -987,19 +987,16 @@ static void iPsxBranchTest(u32 newpc, u32 cpuBranch)
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MOV32RtoM((uptr)&psxRegs.cycle, ECX); // update cycles
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}
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else {
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SUB32ItoM((uptr)&EEsCycle, s_psxBlockCycles*PSXCYCLE_MULT*8); // 8 EE clocks for every IOP clock.
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SUB32ItoM((uptr)&EEsCycle, ((u32)(s_psxBlockCycles*PSXCYCLE_MULT))*8); // 8 EE clocks for every IOP clock.
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ADD32ItoM((uptr)&psxRegs.cycle, s_psxBlockCycles*PSXCYCLE_MULT);
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return;
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}
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// check if we've caught up with the EE
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SUB32ItoM((uptr)&EEsCycle, s_psxBlockCycles*PSXCYCLE_MULT*8); // 8 EE clocks for every IOP clock.
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SUB32ItoM((uptr)&EEsCycle, ((u32)(s_psxBlockCycles*PSXCYCLE_MULT))*8); // 8 EE clocks for every IOP clock.
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j8Ptr[2] = JGE8(0);
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// Break the Block-execute Loop here.
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// (but not without running another branch test! And do it regardless
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// because the EE needs at least one IOP branch test or else bad things happen)
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CALLFunc((uptr)psxBranchTest);
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if( REC_INC_STACK )
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ADD64ItoR(ESP, REC_INC_STACK);
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