mirror of https://github.com/PCSX2/pcsx2.git
gsdx: Relax SSE/AVX constraint on 64 bits
The JIT will automatically select the best ISA (only AVX1 so far)
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@ -212,16 +212,16 @@ bool GSUtil::CheckSSE()
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ISA checks[] = {
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{Xbyak::util::Cpu::tSSE2, "SSE2"},
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#if _M_SSE >= 0x301 || defined(_M_AMD64)
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#if _M_SSE >= 0x301
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{Xbyak::util::Cpu::tSSSE3, "SSSE3"},
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#endif
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#if _M_SSE >= 0x401 || defined(_M_AMD64)
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#if _M_SSE >= 0x401
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{Xbyak::util::Cpu::tSSE41, "SSE41"},
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#endif
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#if _M_SSE >= 0x402 || defined(_M_AMD64)
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#if _M_SSE >= 0x402
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{Xbyak::util::Cpu::tSSE42, "SSE42"},
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#endif
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#if _M_SSE >= 0x500 || defined(_M_AMD64)
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#if _M_SSE >= 0x500
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{Xbyak::util::Cpu::tAVX, "AVX1"},
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#endif
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#if _M_SSE >= 0x501
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@ -266,9 +266,10 @@ using namespace stdext;
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#define ASSERT assert
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#ifdef __x86_64__
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#define _M_AMD64
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#endif
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#ifdef _M_AMD64
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// Yeah let use mips naming ;)
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#ifdef _WIN64
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#define a0 rcx
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@ -285,42 +286,26 @@ using namespace stdext;
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#define t0 r8
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#define t1 r9
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#endif
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#endif
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// sse
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#if defined(__GNUC__) && !defined(__x86_64__)
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#if defined(__GNUC__)
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// Convert gcc see define into GSdx (windows) define
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#if defined(__AVX2__)
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#if defined(__x86_64__)
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#define _M_SSE 0x500 // TODO
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#else
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#define _M_SSE 0x501
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#endif
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#elif defined(__AVX__)
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#define _M_SSE 0x500
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#elif defined(__SSE4_2__)
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#define _M_SSE 0x402
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#elif defined(__SSE4_1__)
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#define _M_SSE 0x401
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#elif defined(__SSSE3__)
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#define _M_SSE 0x301
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#elif defined(__SSE2__)
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#define _M_SSE 0x200
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#elif defined(__SSE__)
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#define _M_SSE 0x100
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#endif
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#elif defined(__GNUC__)
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#if defined(__AVX2__)
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// FIXME until code is done
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#define _M_SSE 0x500
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#elif defined(__AVX__)
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#define _M_SSE 0x500
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#elif defined(__SSE4_1__)
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#define _M_SSE 0x401
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#else
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// FIXME won't likely be supported but allow to compile the code
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// Note: from steam survey SSE4.1 is supported by 87% (end of 2015)
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#define _M_SSE 0x200
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#endif
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#endif
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