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gsdx: Relax SSE/AVX constraint on 64 bits 

The JIT will automatically select the best ISA (only AVX1 so far)
This commit is contained in:
Gregory Hainaut 2016-11-19 15:01:14 +01:00
parent 8fd46e96aa
commit cc6d193e1d
2 changed files with 12 additions and 27 deletions
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8
plugins/GSdx/GSUtil.cpp
View File

@ -212,16 +212,16 @@ bool GSUtil::CheckSSE()
ISA checks[] = {
{Xbyak::util::Cpu::tSSE2, "SSE2"},
#if _M_SSE >= 0x301 || defined(_M_AMD64)
#if _M_SSE >= 0x301
{Xbyak::util::Cpu::tSSSE3, "SSSE3"},
#endif
#if _M_SSE >= 0x401 || defined(_M_AMD64)
#if _M_SSE >= 0x401
{Xbyak::util::Cpu::tSSE41, "SSE41"},
#endif
#if _M_SSE >= 0x402 || defined(_M_AMD64)
#if _M_SSE >= 0x402
{Xbyak::util::Cpu::tSSE42, "SSE42"},
#endif
#if _M_SSE >= 0x500 || defined(_M_AMD64)
#if _M_SSE >= 0x500
{Xbyak::util::Cpu::tAVX, "AVX1"},
#endif
#if _M_SSE >= 0x501

31
plugins/GSdx/stdafx.h
View File

@ -266,9 +266,10 @@ using namespace stdext;
#define ASSERT assert
#ifdef __x86_64__
#define _M_AMD64
#endif
#ifdef _M_AMD64
// Yeah let use mips naming ;)
#ifdef _WIN64
#define a0 rcx
@ -285,42 +286,26 @@ using namespace stdext;
#define t0 r8
#define t1 r9
#endif
#endif
// sse
#if defined(__GNUC__) && !defined(__x86_64__)
#if defined(__GNUC__)
// Convert gcc see define into GSdx (windows) define
#if defined(__AVX2__)
#define _M_SSE 0x501
#if defined(__x86_64__)
#define _M_SSE 0x500 // TODO
#else
#define _M_SSE 0x501
#endif
#elif defined(__AVX__)
#define _M_SSE 0x500
#elif defined(__SSE4_2__)
#define _M_SSE 0x402
#elif defined(__SSE4_1__)
#define _M_SSE 0x401
#elif defined(__SSSE3__)
#define _M_SSE 0x301
#elif defined(__SSE2__)
#define _M_SSE 0x200
#elif defined(__SSE__)
#define _M_SSE 0x100
#endif
#elif defined(__GNUC__)
#if defined(__AVX2__)
// FIXME until code is done
#define _M_SSE 0x500
#elif defined(__AVX__)
#define _M_SSE 0x500
#elif defined(__SSE4_1__)
#define _M_SSE 0x401
#else
// FIXME won't likely be supported but allow to compile the code
// Note: from steam survey SSE4.1 is supported by 87% (end of 2015)
#define _M_SSE 0x200
#endif
#endif