mirror of https://github.com/PCSX2/pcsx2.git
pcsx2: manually cast function pointer to void*
Templace is nicer but give a hard time to compiler. New version compile in both gcc&clang without hack v2: add an uptr cast too for VS2013 sigh... v3: use an ugly function pointer cast to please VS2013
This commit is contained in:
Gregory Hainaut
parent
15db7eeb81
commit
cc68776069
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@ -19,23 +19,6 @@
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namespace x86Emitter {
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#ifdef __GNUG__
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// GCC has a bug that causes the templated function handler for Jmp/Call emitters to generate
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// bad asm code. (error is something like "7#*_uber_379s_mangled_$&02_name is already defined!")
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// Using GCC's always_inline attribute fixes it. This differs from __fi in that it
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// inlines *even in debug builds* which is (usually) undesirable.
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// ... except when it avoids compiler bugs.
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// Note: I try with -fabi-version=6 without success
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// {standard input}: Assembler messages:
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// {standard input}:30773: Error: symbol `_ZNK10x86Emitter13xImpl_JmpCallclIFvvEEEvPT_' is already defined
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// pcsx2/CMakeFiles/PCSX2.dir/build.make:4550: recipe for target 'pcsx2/CMakeFiles/PCSX2.dir/x86/ix86-32/iR5900-32.cpp.o' failed
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# define __always_inline_tmpl_fail __attribute__((always_inline))
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#else
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# define __always_inline_tmpl_fail
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#endif
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extern void xJccKnownTarget( JccComparisonType comparison, const void* target, bool slideForward );
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// ------------------------------------------------------------------------
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@ -48,8 +31,7 @@ struct xImpl_JmpCall
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// Special form for calling functions. This form automatically resolves the
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// correct displacement based on the size of the instruction being generated.
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template< typename T > __fi __always_inline_tmpl_fail
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void operator()( T* func ) const
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void operator()( void* func ) const
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{
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if( isJmp )
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xJccKnownTarget( Jcc_Unconditional, (void*)(uptr)func, false ); // double cast to/from (uptr) needed to appease GCC
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@ -79,35 +61,34 @@ struct xImpl_FastCall
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#ifdef __x86_64__
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#define XFASTCALL \
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xCALL(func);
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xCALL(f);
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#define XFASTCALL1 \
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xMOV(rdi, a1); \
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xCALL(func);
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xCALL(f);
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#define XFASTCALL2 \
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xMOV(rdi, a1); \
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xMOV(rsi, a2); \
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xCALL(func);
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xCALL(f);
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#else
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#define XFASTCALL \
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xCALL(func);
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xCALL(f);
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#define XFASTCALL1 \
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xMOV(ecx, a1); \
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xCALL(func);
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xCALL(f);
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#define XFASTCALL2 \
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xMOV(ecx, a1); \
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xMOV(edx, a2); \
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xCALL(func);
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xCALL(f);
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#endif
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template< typename T > __fi __always_inline_tmpl_fail
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void operator()( T* func, const xRegisterLong& a1 = xEmptyReg, const xRegisterLong& a2 = xEmptyReg) const
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void operator()( void* f, const xRegisterLong& a1 = xEmptyReg, const xRegisterLong& a2 = xEmptyReg) const
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{
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#ifdef __x86_64__
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if (a1.IsEmpty()) {
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@ -128,9 +109,11 @@ struct xImpl_FastCall
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#endif
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}
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template< typename T > __fi __always_inline_tmpl_fail
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template< typename T > __fi
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void operator()( T* func, u32 a1, const xRegisterLong& a2) const
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{
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void* f = (void*)func;
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#ifdef __x86_64__
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XFASTCALL2;
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#else
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@ -138,9 +121,11 @@ struct xImpl_FastCall
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#endif
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}
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template< typename T > __fi __always_inline_tmpl_fail
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template< typename T > __fi
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void operator()( T* func, const xIndirectVoid& a1) const
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{
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void* f = (void*)func;
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#ifdef __x86_64__
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XFASTCALL1;
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#else
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@ -148,9 +133,11 @@ struct xImpl_FastCall
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#endif
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}
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template< typename T > __fi __always_inline_tmpl_fail
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template< typename T > __fi
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void operator()( T* func, u32 a1, u32 a2) const
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{
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void* f = (void*)func;
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#ifdef __x86_64__
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XFASTCALL2;
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#else
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@ -158,9 +145,11 @@ struct xImpl_FastCall
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#endif
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}
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template< typename T > __fi __always_inline_tmpl_fail
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template< typename T > __fi
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void operator()( T* func, u32 a1) const
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{
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void* f = (void*)func;
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#ifdef __x86_64__
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XFASTCALL1;
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#else
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@ -168,7 +157,7 @@ struct xImpl_FastCall
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#endif
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}
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void operator()(const xIndirect32& func, const xRegisterLong& a1 = xEmptyReg, const xRegisterLong& a2 = xEmptyReg) const
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void operator()(const xIndirect32& f, const xRegisterLong& a1 = xEmptyReg, const xRegisterLong& a2 = xEmptyReg) const
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{
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#ifdef __x86_64__
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if (a1.IsEmpty()) {
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@ -169,13 +169,13 @@ void recMFC0()
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else if (0 == (_Imm_ & 2)) // MFPC 0, only LSB of register matters
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{
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iFlushCall(FLUSH_INTERPRETER);
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xFastCall(COP0_UpdatePCCR);
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xFastCall((void*)COP0_UpdatePCCR);
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xMOV(eax, ptr[&cpuRegs.PERF.n.pcr0]);
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}
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else // MFPC 1
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{
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iFlushCall(FLUSH_INTERPRETER);
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xFastCall(COP0_UpdatePCCR);
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xFastCall((void*)COP0_UpdatePCCR);
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xMOV(eax, ptr[&cpuRegs.PERF.n.pcr1]);
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}
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_deleteEEreg(_Rt_, 0);
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@ -206,7 +206,7 @@ void recMTC0()
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{
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case 12:
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iFlushCall(FLUSH_INTERPRETER);
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xFastCall(WriteCP0Status, g_cpuConstRegs[_Rt_].UL[0] );
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xFastCall((void*)WriteCP0Status, g_cpuConstRegs[_Rt_].UL[0] );
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break;
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case 9:
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@ -222,9 +222,9 @@ void recMTC0()
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break;
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// Updates PCRs and sets the PCCR.
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iFlushCall(FLUSH_INTERPRETER);
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xFastCall(COP0_UpdatePCCR);
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xFastCall((void*)COP0_UpdatePCCR);
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xMOV(ptr32[&cpuRegs.PERF.n.pccr], g_cpuConstRegs[_Rt_].UL[0]);
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xFastCall(COP0_DiagnosticPCCR);
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xFastCall((void*)COP0_DiagnosticPCCR);
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}
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else if (0 == (_Imm_ & 2)) // MTPC 0, only LSB of register matters
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{
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@ -256,7 +256,7 @@ void recMTC0()
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case 12:
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iFlushCall(FLUSH_INTERPRETER);
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_eeMoveGPRtoR(ecx, _Rt_);
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xFastCall(WriteCP0Status, ecx );
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xFastCall((void*)WriteCP0Status, ecx );
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break;
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case 9:
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@ -271,9 +271,9 @@ void recMTC0()
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if (0 != (_Imm_ & 0x3E)) // only effective when the register is 0
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break;
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iFlushCall(FLUSH_INTERPRETER);
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xFastCall(COP0_UpdatePCCR);
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xFastCall((void*)COP0_UpdatePCCR);
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_eeMoveGPRtoM((uptr)&cpuRegs.PERF.n.pccr, _Rt_);
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xFastCall(COP0_DiagnosticPCCR);
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xFastCall((void*)COP0_DiagnosticPCCR);
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}
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else if (0 == (_Imm_ & 2)) // MTPC 0, only LSB of register matters
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{
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@ -128,7 +128,7 @@ static DynGenFunc* _DynGen_JITCompile()
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u8* retval = xGetPtr();
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xFastCall(iopRecRecompile, ptr[&psxRegs.pc] );
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xFastCall((void*)iopRecRecompile, ptr[&psxRegs.pc] );
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xMOV( eax, ptr[&psxRegs.pc] );
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xMOV( ebx, eax );
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@ -142,7 +142,7 @@ static DynGenFunc* _DynGen_JITCompile()
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static DynGenFunc* _DynGen_JITCompileInBlock()
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{
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u8* retval = xGetPtr();
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xJMP( iopJITCompile );
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xJMP( (void*)iopJITCompile );
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return (DynGenFunc*)retval;
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}
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@ -174,7 +174,7 @@ static DynGenFunc* _DynGen_EnterRecompiledCode()
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{ // Properly scope the frame prologue/epilogue
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xScopedStackFrame frame(IsDevBuild);
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xJMP(iopDispatcherReg);
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xJMP((void*)iopDispatcherReg);
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// Save an exit point
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iopExitRecompiledCode = (DynGenFunc*)xGetPtr();
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@ -198,7 +198,7 @@ static void _DynGen_Dispatchers()
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// Place the EventTest and DispatcherReg stuff at the top, because they get called the
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// most and stand to benefit from strong alignment and direct referencing.
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iopDispatcherEvent = (DynGenFunc*)xGetPtr();
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xFastCall(recEventTest );
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xFastCall((void*)recEventTest );
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iopDispatcherReg = _DynGen_DispatcherReg();
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iopJITCompile = _DynGen_JITCompile();
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@ -520,15 +520,15 @@ void psxRecompileCodeConst1(R3000AFNPTR constcode, R3000AFNPTR_INFO noconstcode)
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xMOV(ecx, (uptr)libname);
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xMOV(edx, index);
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xPUSH((uptr)funcname);
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xCALL(irxImportLog);
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xCALL((void*)irxImportLog);
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}
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if (debug)
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xFastCall(debug);
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xFastCall((void*)debug);
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#endif
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irxHLE hle = irxImportHLE(libname, index);
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if (hle) {
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xFastCall(hle);
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xFastCall((void*)hle);
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xCMP(eax, 0);
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xJNE(iopDispatcherReg);
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}
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@ -908,7 +908,7 @@ static void iPsxBranchTest(u32 newpc, u32 cpuBranch)
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xSUB(ptr32[&iopCycleEE], eax);
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xJLE(iopExitRecompiledCode);
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xFastCall(iopEventTest);
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xFastCall((void*)iopEventTest);
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if( newpc != 0xffffffff )
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{
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@ -930,7 +930,7 @@ static void iPsxBranchTest(u32 newpc, u32 cpuBranch)
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xSUB(eax, ptr32[&g_iopNextEventCycle]);
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xForwardJS<u8> nointerruptpending;
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xFastCall(iopEventTest);
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xFastCall((void*)iopEventTest);
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if( newpc != 0xffffffff ) {
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xCMP(ptr32[&psxRegs.pc], newpc);
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@ -967,7 +967,7 @@ void rpsxSYSCALL()
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//xMOV( ecx, 0x20 ); // exception code
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//xMOV( edx, psxbranch==1 ); // branch delay slot?
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xFastCall(psxException, 0x20, psxbranch == 1 );
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xFastCall((void*)psxException, 0x20, psxbranch == 1 );
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xCMP(ptr32[&psxRegs.pc], psxpc-4);
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j8Ptr[0] = JE8(0);
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@ -990,7 +990,7 @@ void rpsxBREAK()
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//xMOV( ecx, 0x24 ); // exception code
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//xMOV( edx, psxbranch==1 ); // branch delay slot?
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xFastCall(psxException, 0x24, psxbranch == 1 );
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xFastCall((void*)psxException, 0x24, psxbranch == 1 );
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xCMP(ptr32[&psxRegs.pc], psxpc-4);
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j8Ptr[0] = JE8(0);
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@ -1113,7 +1113,7 @@ static void __fastcall iopRecRecompile( const u32 startpc )
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if( IsDebugBuild )
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{
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xFastCall(PreBlockCheck, psxpc);
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xFastCall((void*)PreBlockCheck, psxpc);
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}
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// go until the next branch
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@ -631,7 +631,7 @@ static void rpsxLB()
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xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
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if (_Imm_) xADD(ecx, _Imm_);
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xFastCall(iopMemRead8, ecx ); // returns value in EAX
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xFastCall((void*)iopMemRead8, ecx ); // returns value in EAX
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if (_Rt_) {
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xMOVSX(eax, al);
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xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax);
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@ -647,7 +647,7 @@ static void rpsxLBU()
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xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
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if (_Imm_) xADD(ecx, _Imm_);
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xFastCall(iopMemRead8, ecx ); // returns value in EAX
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xFastCall((void*)iopMemRead8, ecx ); // returns value in EAX
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if (_Rt_) {
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xMOVZX(eax, al);
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xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax);
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@ -663,7 +663,7 @@ static void rpsxLH()
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xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
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if (_Imm_) xADD(ecx, _Imm_);
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xFastCall(iopMemRead16, ecx ); // returns value in EAX
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xFastCall((void*)iopMemRead16, ecx ); // returns value in EAX
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if (_Rt_) {
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xMOVSX(eax, ax);
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xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax);
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@ -679,7 +679,7 @@ static void rpsxLHU()
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xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
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if (_Imm_) xADD(ecx, _Imm_);
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xFastCall(iopMemRead16, ecx ); // returns value in EAX
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xFastCall((void*)iopMemRead16, ecx ); // returns value in EAX
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if (_Rt_) {
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xMOVZX(eax, ax);
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xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax);
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@ -700,7 +700,7 @@ static void rpsxLW()
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xTEST(ecx, 0x10000000);
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j8Ptr[0] = JZ8(0);
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xFastCall(iopMemRead32, ecx ); // returns value in EAX
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xFastCall((void*)iopMemRead32, ecx ); // returns value in EAX
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if (_Rt_) {
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xMOV(ptr[&psxRegs.GPR.r[_Rt_]], eax);
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}
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@ -728,7 +728,7 @@ static void rpsxSB()
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xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
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if (_Imm_) xADD(ecx, _Imm_);
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xMOV( edx, ptr[&psxRegs.GPR.r[_Rt_]] );
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xFastCall(iopMemWrite8, ecx, edx );
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xFastCall((void*)iopMemWrite8, ecx, edx );
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}
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static void rpsxSH()
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@ -739,7 +739,7 @@ static void rpsxSH()
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xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
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if (_Imm_) xADD(ecx, _Imm_);
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xMOV( edx, ptr[&psxRegs.GPR.r[_Rt_]] );
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xFastCall(iopMemWrite16, ecx, edx );
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xFastCall((void*)iopMemWrite16, ecx, edx );
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}
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static void rpsxSW()
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@ -750,7 +750,7 @@ static void rpsxSW()
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xMOV(ecx, ptr[&psxRegs.GPR.r[_Rs_]]);
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if (_Imm_) xADD(ecx, _Imm_);
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xMOV( edx, ptr[&psxRegs.GPR.r[_Rt_]] );
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xFastCall(iopMemWrite32, ecx, edx );
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xFastCall((void*)iopMemWrite32, ecx, edx );
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}
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//// SLL
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@ -307,7 +307,7 @@ void recBranchCall( void (*func)() )
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void recCall( void (*func)() )
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{
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iFlushCall(FLUSH_INTERPRETER);
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xFastCall(func);
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xFastCall((void*)func);
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}
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// =====================================================================================================
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@ -347,7 +347,7 @@ static DynGenFunc* _DynGen_JITCompile()
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u8* retval = xGetAlignedCallTarget();
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xFastCall(recRecompile, ptr[&cpuRegs.pc] );
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xFastCall((void*)recRecompile, ptr[&cpuRegs.pc] );
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xMOV( eax, ptr[&cpuRegs.pc] );
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xMOV( ebx, eax );
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@ -361,7 +361,7 @@ static DynGenFunc* _DynGen_JITCompile()
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static DynGenFunc* _DynGen_JITCompileInBlock()
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{
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u8* retval = xGetAlignedCallTarget();
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xJMP( JITCompile );
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xJMP( (void*)JITCompile );
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return (DynGenFunc*)retval;
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}
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@ -383,7 +383,7 @@ static DynGenFunc* _DynGen_DispatcherEvent()
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{
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u8* retval = xGetPtr();
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xFastCall(recEventTest );
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xFastCall((void*)recEventTest );
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return (DynGenFunc*)retval;
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}
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@ -397,7 +397,7 @@ static DynGenFunc* _DynGen_EnterRecompiledCode()
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{ // Properly scope the frame prologue/epilogue
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xScopedStackFrame frame(IsDevBuild);
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xJMP(DispatcherReg);
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xJMP((void*)DispatcherReg);
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||||
// Save an exit point
|
||||
ExitRecompiledCode = (DynGenFunc*)xGetPtr();
|
||||
|
|
@ -411,16 +411,16 @@ static DynGenFunc* _DynGen_EnterRecompiledCode()
|
|||
static DynGenFunc* _DynGen_DispatchBlockDiscard()
|
||||
{
|
||||
u8* retval = xGetPtr();
|
||||
xFastCall(dyna_block_discard);
|
||||
xJMP(ExitRecompiledCode);
|
||||
xFastCall((void*)dyna_block_discard);
|
||||
xJMP((void*)ExitRecompiledCode);
|
||||
return (DynGenFunc*)retval;
|
||||
}
|
||||
|
||||
static DynGenFunc* _DynGen_DispatchPageReset()
|
||||
{
|
||||
u8* retval = xGetPtr();
|
||||
xFastCall(dyna_page_reset);
|
||||
xJMP(ExitRecompiledCode);
|
||||
xFastCall((void*)dyna_page_reset);
|
||||
xJMP((void*)ExitRecompiledCode);
|
||||
return (DynGenFunc*)retval;
|
||||
}
|
||||
|
||||
|
|
@ -742,7 +742,7 @@ void R5900::Dynarec::OpcodeImpl::recSYSCALL()
|
|||
xADD(ptr32[&cpuRegs.cycle], scaleblockcycles());
|
||||
// Note: technically the address is 0x8000_0180 (or 0x180)
|
||||
// (if CPU is booted)
|
||||
xJMP( DispatcherReg );
|
||||
xJMP( (void*)DispatcherReg );
|
||||
x86SetJ8(j8Ptr[0]);
|
||||
//g_branch = 2;
|
||||
}
|
||||
|
|
@ -757,7 +757,7 @@ void R5900::Dynarec::OpcodeImpl::recBREAK()
|
|||
xCMP(ptr32[&cpuRegs.pc], pc);
|
||||
j8Ptr[0] = JE8(0);
|
||||
xADD(ptr32[&cpuRegs.cycle], scaleblockcycles());
|
||||
xJMP( DispatcherEvent );
|
||||
xJMP( (void*)DispatcherEvent );
|
||||
x86SetJ8(j8Ptr[0]);
|
||||
//g_branch = 2;
|
||||
}
|
||||
|
|
@ -1034,7 +1034,7 @@ static void iBranchTest(u32 newpc)
|
|||
xCMOVS(eax, ptr32[&cpuRegs.cycle]);
|
||||
xMOV(ptr32[&cpuRegs.cycle], eax);
|
||||
|
||||
xJMP( DispatcherEvent );
|
||||
xJMP( (void*)DispatcherEvent );
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -1048,7 +1048,7 @@ static void iBranchTest(u32 newpc)
|
|||
else
|
||||
recBlocks.Link(HWADDR(newpc), xJcc32(Jcc_Signed));
|
||||
|
||||
xJMP( DispatcherEvent );
|
||||
xJMP( (void*)DispatcherEvent );
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1179,7 +1179,7 @@ void recMemcheck(u32 op, u32 bits, bool store)
|
|||
if (bits == 128)
|
||||
xAND(ecx, ~0x0F);
|
||||
|
||||
xFastCall(standardizeBreakpointAddress, ecx);
|
||||
xFastCall((void*)standardizeBreakpointAddress, ecx);
|
||||
xMOV(ecx,eax);
|
||||
xMOV(edx,eax);
|
||||
xADD(edx,bits/8);
|
||||
|
|
@ -1210,10 +1210,10 @@ void recMemcheck(u32 op, u32 bits, bool store)
|
|||
// hit the breakpoint
|
||||
if (checks[i].result & MEMCHECK_LOG) {
|
||||
xMOV(edx, store);
|
||||
xFastCall(dynarecMemLogcheck, ecx, edx);
|
||||
xFastCall((void*)dynarecMemLogcheck, ecx, edx);
|
||||
}
|
||||
if (checks[i].result & MEMCHECK_BREAK) {
|
||||
xFastCall(dynarecMemcheck);
|
||||
xFastCall((void*)dynarecMemcheck);
|
||||
}
|
||||
|
||||
next1.SetTarget();
|
||||
|
|
@ -1226,7 +1226,7 @@ void encodeBreakpoint()
|
|||
if (isBreakpointNeeded(pc) != 0)
|
||||
{
|
||||
iFlushCall(FLUSH_EVERYTHING|FLUSH_PC);
|
||||
xFastCall(dynarecCheckBreakpoint);
|
||||
xFastCall((void*)dynarecCheckBreakpoint);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1657,7 +1657,7 @@ static void __fastcall recRecompile( const u32 startpc )
|
|||
}
|
||||
|
||||
if (eeloadMain && HWADDR(startpc) == HWADDR(eeloadMain)) {
|
||||
xFastCall(eeloadHook);
|
||||
xFastCall((void*)eeloadHook);
|
||||
|
||||
// On fast/full boot this will have a crc of 0x0. But when the game/elf itself is
|
||||
// recompiled (below - ElfEntry && g_GameLoading), then the crc would be from the elf.
|
||||
|
|
@ -1671,7 +1671,7 @@ static void __fastcall recRecompile( const u32 startpc )
|
|||
// this is the only way patches get applied, doesn't depend on a hack
|
||||
if (g_GameLoading && HWADDR(startpc) == ElfEntry) {
|
||||
Console.WriteLn(L"Elf entry point @ 0x%08x about to get recompiled. Load patches first.", startpc);
|
||||
xFastCall(eeGameStarting);
|
||||
xFastCall((void*)eeGameStarting);
|
||||
|
||||
// Apply patch as soon as possible. Normally it is done in
|
||||
// eeGameStarting but first block is already compiled.
|
||||
|
|
@ -1695,18 +1695,18 @@ static void __fastcall recRecompile( const u32 startpc )
|
|||
// [TODO] : These must be enabled from the GUI or INI to be used, otherwise the
|
||||
// code that calls PreBlockCheck will not be generated.
|
||||
|
||||
xFastCall(PreBlockCheck, pc);
|
||||
xFastCall((void*)PreBlockCheck, pc);
|
||||
}
|
||||
|
||||
if (EmuConfig.Gamefixes.GoemonTlbHack) {
|
||||
if (pc == 0x33ad48 || pc == 0x35060c) {
|
||||
// 0x33ad48 and 0x35060c are the return address of the function (0x356250) that populate the TLB cache
|
||||
xFastCall(GoemonPreloadTlb);
|
||||
xFastCall((void*)GoemonPreloadTlb);
|
||||
} else if (pc == 0x3563b8) {
|
||||
// Game will unmap some virtual addresses. If a constant address were hardcoded in the block, we would be in a bad situation.
|
||||
eeRecNeedsReset = true;
|
||||
// 0x3563b8 is the start address of the function that invalidate entry in TLB cache
|
||||
xFastCall(GoemonUnloadTlb, ptr[&cpuRegs.GPR.n.a0.UL[0]]);
|
||||
xFastCall((void*)GoemonUnloadTlb, ptr[&cpuRegs.GPR.n.a0.UL[0]]);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -57,8 +57,8 @@ void mVUDTendProgram(mV, microFlagCycles* mFC, int isEbit) {
|
|||
mVU_XGKICK_DELAY(mVU);
|
||||
}
|
||||
if (doEarlyExit(mVU)) {
|
||||
if (!isVU1) xFastCall(mVU0clearlpStateJIT);
|
||||
else xFastCall(mVU1clearlpStateJIT);
|
||||
if (!isVU1) xFastCall((void*)mVU0clearlpStateJIT);
|
||||
else xFastCall((void*)mVU1clearlpStateJIT);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -117,9 +117,9 @@ void mVUendProgram(mV, microFlagCycles* mFC, int isEbit) {
|
|||
}
|
||||
if (doEarlyExit(mVU)) {
|
||||
if (!isVU1)
|
||||
xFastCall(mVU0clearlpStateJIT);
|
||||
xFastCall((void*)mVU0clearlpStateJIT);
|
||||
else
|
||||
xFastCall(mVU1clearlpStateJIT);
|
||||
xFastCall((void*)mVU1clearlpStateJIT);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -192,8 +192,8 @@ void normJumpCompile(mV, microFlagCycles& mFC, bool isEvilJump) {
|
|||
xJMP(mVU.exitFunct);
|
||||
}
|
||||
|
||||
if (!mVU.index) xFastCall(mVUcompileJIT<0>, gprT2, gprT3); //(u32 startPC, uptr pState)
|
||||
else xFastCall(mVUcompileJIT<1>, gprT2, gprT3);
|
||||
if (!mVU.index) xFastCall((void*)(void(*)())mVUcompileJIT<0>, gprT2, gprT3); //(u32 startPC, uptr pState)
|
||||
else xFastCall((void*)(void(*)())mVUcompileJIT<1>, gprT2, gprT3);
|
||||
|
||||
mVUrestoreRegs(mVU);
|
||||
xJMP(gprT1); // Jump to rec-code address
|
||||
|
|
|
|||
|
|
@ -27,8 +27,8 @@ void mVUdispatcherAB(mV) {
|
|||
xScopedStackFrame frame(false, true);
|
||||
|
||||
// __fastcall = The caller has already put the needed parameters in ecx/edx:
|
||||
if (!isVU1) { xFastCall(mVUexecuteVU0, ecx, edx); }
|
||||
else { xFastCall(mVUexecuteVU1, ecx, edx); }
|
||||
if (!isVU1) { xFastCall((void*)mVUexecuteVU0, ecx, edx); }
|
||||
else { xFastCall((void*)mVUexecuteVU1, ecx, edx); }
|
||||
|
||||
// Load VU's MXCSR state
|
||||
xLDMXCSR(g_sseVUMXCSR);
|
||||
|
|
@ -61,8 +61,8 @@ void mVUdispatcherAB(mV) {
|
|||
|
||||
// __fastcall = The first two DWORD or smaller arguments are passed in ECX and EDX registers;
|
||||
// all other arguments are passed right to left.
|
||||
if (!isVU1) { xFastCall(mVUcleanUpVU0); }
|
||||
else { xFastCall(mVUcleanUpVU1); }
|
||||
if (!isVU1) { xFastCall((void*)mVUcleanUpVU0); }
|
||||
else { xFastCall((void*)mVUcleanUpVU1); }
|
||||
}
|
||||
|
||||
xRET();
|
||||
|
|
|
|||
|
|
@ -249,15 +249,15 @@ void recBC2TL() { _setupBranchTest(JZ32, true); }
|
|||
void COP2_Interlock(bool mBitSync) {
|
||||
if (cpuRegs.code & 1) {
|
||||
iFlushCall(FLUSH_EVERYTHING | FLUSH_PC);
|
||||
if (mBitSync) xFastCall(_vu0WaitMicro);
|
||||
else xFastCall(_vu0FinishMicro);
|
||||
if (mBitSync) xFastCall((void*)_vu0WaitMicro);
|
||||
else xFastCall((void*)_vu0FinishMicro);
|
||||
}
|
||||
}
|
||||
|
||||
void TEST_FBRST_RESET(FnType_Void* resetFunct, int vuIndex) {
|
||||
xTEST(eax, (vuIndex) ? 0x200 : 0x002);
|
||||
xForwardJZ8 skip;
|
||||
xFastCall(resetFunct);
|
||||
xFastCall((void*)resetFunct);
|
||||
xMOV(eax, ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]);
|
||||
skip.SetTarget();
|
||||
}
|
||||
|
|
@ -316,8 +316,8 @@ static void recCTC2() {
|
|||
xMOV(ecx, ptr32[&cpuRegs.GPR.r[_Rt_].UL[0]]);
|
||||
}
|
||||
else xXOR(ecx, ecx);
|
||||
xFastCall(vu1ExecMicro, ecx);
|
||||
xFastCall(vif1VUFinish);
|
||||
xFastCall((void*)vu1ExecMicro, ecx);
|
||||
xFastCall((void*)vif1VUFinish);
|
||||
break;
|
||||
case REG_FBRST:
|
||||
if (!_Rt_) {
|
||||
|
|
@ -336,7 +336,7 @@ static void recCTC2() {
|
|||
// Executing vu0 block here fixes the intro of Ratchet and Clank
|
||||
// sVU's COP2 has a comment that "Donald Duck" needs this too...
|
||||
if (_Rd_) _eeMoveGPRtoM((uptr)&vu0Regs.VI[_Rd_].UL, _Rt_);
|
||||
xFastCall(BaseVUmicroCPU::ExecuteBlockJIT, (uptr)CpuVU0);
|
||||
xFastCall((void*)BaseVUmicroCPU::ExecuteBlockJIT, (uptr)CpuVU0);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -298,9 +298,9 @@ __fi void mVUaddrFix(mV, const x32& gprReg)
|
|||
if (IsDevBuild && !isCOP2) { // Lets see which games do this!
|
||||
xMOV(gprT2, mVU.prog.cur->idx); // Note: Kernel does it via COP2 to initialize VU1!
|
||||
xMOV(gprT3, xPC); // So we don't spam console, we'll only check micro-mode...
|
||||
xCALL(mVUwarningRegAccess);
|
||||
xCALL((void*)mVUwarningRegAccess);
|
||||
}
|
||||
xCALL(mVUwaitMTVU);
|
||||
xCALL((void*)mVUwaitMTVU);
|
||||
#ifdef __GNUC__
|
||||
xADD(esp, 4);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -2890,7 +2890,7 @@ void VuBaseBlock::Recompile()
|
|||
if (itparent == parents.end()) xMOV(ptr32[&skipparent], -1);
|
||||
|
||||
xMOV( ecx, s_vu );
|
||||
xCALL( svudispfn );
|
||||
xCALL( (void*)svudispfn );
|
||||
#endif
|
||||
|
||||
s_pCurBlock = this;
|
||||
|
|
@ -3599,7 +3599,7 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
|
|||
u8* jptr = JZ8(0);
|
||||
xOR(ptr32[&VU0.VI[REG_VPU_STAT].UL], s_vu ? 0x200 : 0x002);
|
||||
xMOV( ecx, s_vu ? INTC_VU1 : INTC_VU0 );
|
||||
xCALL( hwIntcIrq );
|
||||
xCALL( (void*)hwIntcIrq );
|
||||
x86SetJ8(jptr);
|
||||
}
|
||||
if (code_ptr[1] & 0x08000000) // T flag
|
||||
|
|
@ -3608,7 +3608,7 @@ void VuInstruction::Recompile(std::list<VuInstruction>::iterator& itinst, u32 vu
|
|||
u8* jptr = JZ8(0);
|
||||
xOR(ptr32[&VU0.VI[REG_VPU_STAT].UL], s_vu ? 0x400 : 0x004);
|
||||
xMOV( ecx, s_vu ? INTC_VU1 : INTC_VU0 );
|
||||
xCALL( hwIntcIrq );
|
||||
xCALL( (void*)hwIntcIrq );
|
||||
x86SetJ8(jptr);
|
||||
}
|
||||
|
||||
|
|
@ -4311,7 +4311,7 @@ void recVUMI_XGKICK_(VURegs *VU)
|
|||
_freeXMMregs();
|
||||
|
||||
xMOV(ecx, xRegister32(s_XGKICKReg));
|
||||
xCALL(VU1XGKICK_MTGSTransfer);
|
||||
xCALL((void*)VU1XGKICK_MTGSTransfer);
|
||||
|
||||
s_ScheduleXGKICK = 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue