mirror of https://github.com/PCSX2/pcsx2.git
microVU: Made the new logs mVU logs for Rama <3
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@5591 96395faa-99c1-11dd-bbfe-3dabce05a288
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@ -496,12 +496,12 @@ void mVUDoDBit(microVU& mVU, microFlagCycles* mFC)
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{
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incPC(-2); // Go back to branch opcode
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DevCon.Warning("D Bit on branch");
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DevCon.Warning("microVU%d: D-Bit on branch [%04x]", getIndex, xPC);
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mVUDTendProgram(mVU, mFC, 2);
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xCMP(ptr16[&mVU.branch], 0);
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switch (mVUlow.branch) {
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case 1: case 2: Jcc = Jcc_Unconditional; DevCon.Warning("D Bit on B/BAL, might be buggy"); break; // B/BAL
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case 9: case 10: DevCon.Warning("JR/JALR probably not supported on D Bit!"); break; // JR/JALR
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case 1: case 2: Jcc = Jcc_Unconditional; DevCon.Warning("microVU%d: D Bit on B/BAL, might be buggy", getIndex); break; // B/BAL
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case 9: case 10: DevCon.Warning("microVU%d: JR/JALR probably not supported on D Bit!", getIndex); break; // JR/JALR
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case 3: Jcc = Jcc_Equal; break; // IBEQ
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case 4: Jcc = Jcc_GreaterOrEqual; break; // IBGEZ
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case 5: Jcc = Jcc_Greater; break; // IBGTZ
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@ -549,13 +549,12 @@ void mVUDoTBit(microVU& mVU, microFlagCycles* mFC)
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if(isBranch)
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{
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incPC(-2); // Go back to branch opcode
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DevCon.Warning("T Bit on branch");
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DevCon.Warning("microVU%d: T-Bit on branch [%04x]", getIndex, xPC);
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mVUDTendProgram(mVU, mFC, 2);
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xCMP(ptr16[&mVU.branch], 0);
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switch (mVUlow.branch) {
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case 1: case 2: Jcc = Jcc_Unconditional; DevCon.Warning("T Bit on B/BAL, might be buggy"); break; // B/BAL
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case 9: case 10: DevCon.Warning("JR/JALR probably not supported on T Bit!"); break; // JR/JALR
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case 1: case 2: Jcc = Jcc_Unconditional; DevCon.Warning("microVU%d: T Bit on B/BAL, might be buggy", getIndex); break; // B/BAL
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case 9: case 10: DevCon.Warning("microVU%d: JR/JALR probably not supported on T Bit!", getIndex); break; // JR/JALR
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case 3: Jcc = Jcc_Equal; break; // IBEQ
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case 4: Jcc = Jcc_GreaterOrEqual; break; // IBGEZ
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case 5: Jcc = Jcc_Greater; break; // IBGTZ
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