ShuriZma
/
pcsx2
mirror of https://github.com/PCSX2/pcsx2.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

SPU2: remove setup irq callback functions

This commit is contained in:
Gauvain 'GovanifY' Roussel-Tarbouriech 2020-09-24 23:39:21 +02:00 committed by refractionpcsx2
parent 0ece59b710
commit cb0e422228
9 changed files with 38 additions and 399 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
pcsx2/IopDma.h
View File

@ -36,6 +36,8 @@ extern void usbInterrupt();
extern void usbIrq(int cycles);
extern void fwIrq();
extern void spu2Irq();
extern void spu2DMA4Irq();
extern void spu2DMA7Irq();
extern void iopIntcIrq( uint irqType );
extern void iopTestIntc();

1
pcsx2/SPU2/Dma.cpp
View File

@ -377,7 +377,6 @@ void V_Core::DoDMAwrite(u16 *pMem, u32 size)
DMAPtr = pMem;
if (size < 2) {
//if(dma7callback) dma7callback();
Regs.STATX &= ~0x80;
//Regs.ATTR |= 0x30;
DMAICounter = 1;

25
pcsx2/SPU2/ReadInput.cpp
View File

@ -17,6 +17,7 @@
#include "Global.h"
#include "Dma.h"
#include "IopDma.h"
#include "spu2.h" // required for ENABLE_NEW_IOPDMA_SPU2 define
@ -90,11 +91,15 @@ StereoOut32 V_Core::ReadInput_HiFi()
// Hack, kinda. We call the interrupt early here, since PCSX2 doesn't like them delayed.
//DMAICounter = 1;
if (Index == 0) {
if (dma4callback)
dma4callback();
if(!SPU2_dummy_callback)
spu2DMA4Irq();
else
SPU2interruptDMA4();
} else {
if (dma7callback)
dma7callback();
if(!SPU2_dummy_callback)
spu2DMA7Irq();
else
SPU2interruptDMA7();
}
}
}
@ -153,11 +158,15 @@ StereoOut32 V_Core::ReadInput()
// Hack, kinda. We call the interrupt early here, since PCSX2 doesn't like them delayed.
//DMAICounter = 1;
if (Index == 0) {
if (dma4callback)
dma4callback();
if(!SPU2_dummy_callback)
spu2DMA4Irq();
else
SPU2interruptDMA4();
} else {
if (dma7callback)
dma7callback();
if(!SPU2_dummy_callback)
spu2DMA7Irq();
else
SPU2interruptDMA7();
}
}
}

321
pcsx2/SPU2/Spu2replay.cpp
View File

@ -1,321 +0,0 @@
//GiGaHeRz's SPU2 Driver
//Copyright (c) 2003-2008, David Quintana <gigaherz@gmail.com>
//
//This library is free software; you can redistribute it and/or
//modify it under the terms of the GNU Lesser General Public
//License as published by the Free Software Foundation; either
//version 2.1 of the License, or (at your option) any later version.
//
//This library is distributed in the hope that it will be useful,
//but WITHOUT ANY WARRANTY; without even the implied warranty of
//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
//Lesser General Public License for more details.
//
//You should have received a copy of the GNU Lesser General Public
//License along with this library; if not, write to the Free Software
//Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
//
#include "Global.h"
#include "PS2E-spu2.h"
#ifdef _MSC_VER
#include "Windows.h"
#endif
FILE *s2rfile;
void s2r_write16(s16 data)
{
fwrite(&data, 2, 1, s2rfile);
}
void s2r_write32(u32 data)
{
fwrite(&data, 4, 1, s2rfile);
}
static void EMITC(u32 i, u32 a)
{
s2r_write32(((i & 0x7u) << 29u) | (a & 0x1FFFFFFFu));
}
int s2r_open(u32 ticks, char *filename)
{
s2rfile = fopen(filename, "wb");
if (s2rfile)
s2r_write32(ticks);
return s2rfile ? 0 : -1;
}
void s2r_readreg(u32 ticks, u32 addr)
{
if (!s2rfile)
return;
s2r_write32(ticks);
EMITC(0, addr);
}
void s2r_writereg(u32 ticks, u32 addr, s16 value)
{
if (!s2rfile)
return;
s2r_write32(ticks);
EMITC(1, addr);
s2r_write16(value);
}
void s2r_writedma4(u32 ticks, u16 *data, u32 len)
{
u32 i;
if (!s2rfile)
return;
s2r_write32(ticks);
EMITC(2, len);
for (i = 0; i < len; i++, data++)
s2r_write16(*data);
}
void s2r_writedma7(u32 ticks, u16 *data, u32 len)
{
u32 i;
if (!s2rfile)
return;
s2r_write32(ticks);
EMITC(3, len);
for (i = 0; i < len; i++, data++)
s2r_write16(*data);
}
void s2r_close()
{
if (!s2rfile)
return;
fclose(s2rfile);
}
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
// replay code
bool replay_mode = false;
u16 dmabuffer[0xFFFFF];
const u32 IOP_CLK = 768 * 48000;
const u32 IOPCiclesPerMS = 768 * 48;
u32 CurrentIOPCycle = 0;
u64 HighResFreq;
u64 HighResPrev;
double HighResScale;
bool Running = false;
#ifdef _MSC_VER
int conprintf(const char *fmt, ...)
{
#ifdef _WIN32
char s[1024];
va_list list;
va_start(list, fmt);
vsprintf(s, fmt, list);
va_end(list);
HANDLE handle = GetStdHandle(STD_OUTPUT_HANDLE);
if (handle == INVALID_HANDLE_VALUE)
return 0;
DWORD written = 0;
WriteConsoleA(handle, s, strlen(s), &written, 0);
FlushFileBuffers(handle);
return written;
#else
va_list list;
va_start(list, fmt);
int ret = vsprintf(stderr, fmt, list);
va_end(list);
return ret;
#endif
}
void dummy1()
{
}
void dummy4()
{
SPU2interruptDMA4();
}
void dummy7()
{
SPU2interruptDMA7();
}
u64 HighResFrequency()
{
u64 freq;
#ifdef _WIN32
QueryPerformanceFrequency((LARGE_INTEGER *)&freq);
#else
// TODO
#endif
return freq;
}
u64 HighResCounter()
{
u64 time;
#ifdef _WIN32
QueryPerformanceCounter((LARGE_INTEGER *)&time);
#else
// TODO
#endif
return time;
}
void InitWaitSync() // not extremely accurate but enough.
{
HighResFreq = HighResFrequency();
HighResPrev = HighResCounter();
HighResScale = (double)HighResFreq / (double)IOP_CLK;
}
u32 WaitSync(u32 TargetCycle)
{
u32 WaitCycles = (TargetCycle - CurrentIOPCycle);
u32 WaitTime = WaitCycles / IOPCiclesPerMS;
if (WaitTime > 10)
WaitTime = 10;
if (WaitTime == 0)
WaitTime = 1;
SleepEx(WaitTime, TRUE);
// Refresh current time after sleeping
u64 Current = HighResCounter();
u32 delta = (u32)floor((Current - HighResPrev) / HighResScale + 0.5); // We lose some precision here, cycles might drift away over long periods of time ;P
// Calculate time delta
CurrentIOPCycle += delta;
HighResPrev += (u64)floor(delta * HighResScale + 0.5); // Trying to compensate drifting mentioned above, not necessarily useful.
return delta;
}
#ifdef _WIN32
BOOL WINAPI HandlerRoutine(DWORD dwCtrlType)
{
Running = false;
return TRUE;
}
#endif
#include "Windows/Dialogs.h"
EXPORT_C_(void)
s2r_replay(HWND hwnd, HINSTANCE hinst, LPSTR filename, int nCmdShow)
{
int events = 0;
Running = true;
#ifdef _WIN32
AllocConsole();
SetConsoleCtrlHandler(HandlerRoutine, TRUE);
conprintf("Playing %s file on %x...", filename, hwnd);
#endif
// load file
FILE *file = fopen(filename, "rb");
if (!file) {
conprintf("Could not open the replay file.");
return;
}
// if successful, init the plugin
#define TryRead(dest, size, count, file) \
if (fread(dest, size, count, file) < count) { \
conprintf("Error reading from file."); \
goto Finish; /* Need to exit the while() loop and maybe also the switch */ \
}
TryRead(&CurrentIOPCycle, 4, 1, file);
replay_mode = true;
InitWaitSync(); // Initialize the WaitSync stuff
SPU2init();
SPU2irqCallback(dummy1, dummy4, dummy7);
SPU2setClockPtr(&CurrentIOPCycle);
SPU2open(&hwnd);
CurrentIOPCycle = 0;
SPU2async(0);
while (!feof(file) && Running) {
u32 ccycle = 0;
u32 evid = 0;
u32 sval = 0;
u32 tval = 0;
TryRead(&ccycle, 4, 1, file);
TryRead(&sval, 4, 1, file);
evid = sval >> 29;
sval &= 0x1FFFFFFF;
u32 TargetCycle = ccycle * 768;
while (TargetCycle > CurrentIOPCycle) {
u32 delta = WaitSync(TargetCycle);
SPU2async(delta);
}
switch (evid) {
case 0:
SPU2read(sval);
break;
case 1:
TryRead(&tval, 2, 1, file);
SPU2write(sval, tval);
break;
case 2:
TryRead(dmabuffer, sval, 2, file);
SPU2writeDMA4Mem(dmabuffer, sval);
break;
case 3:
TryRead(dmabuffer, sval, 2, file);
SPU2writeDMA7Mem(dmabuffer, sval);
break;
default:
// not implemented
return;
break;
}
events++;
}
Finish:
//shutdown
SPU2close();
SPU2shutdown();
fclose(file);
conprintf("Finished playing %s file (%d cycles, %d events).", filename, CurrentIOPCycle, events);
#ifdef _WIN32
FreeConsole();
#endif
replay_mode = false;
}
#endif

31
pcsx2/SPU2/Spu2replay.h
View File

@ -1,31 +0,0 @@
//GiGaHeRz's SPU2 Driver
//Copyright (c) 2003-2008, David Quintana <gigaherz@gmail.com>
//
//This library is free software; you can redistribute it and/or
//modify it under the terms of the GNU Lesser General Public
//License as published by the Free Software Foundation; either
//version 2.1 of the License, or (at your option) any later version.
//
//This library is distributed in the hope that it will be useful,
//but WITHOUT ANY WARRANTY; without even the implied warranty of
//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
//Lesser General Public License for more details.
//
//You should have received a copy of the GNU Lesser General Public
//License along with this library; if not, write to the Free Software
//Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
//
#pragma once
//#define S2R_ENABLE
// s2r dumping
int s2r_open(u32 ticks, char *filename);
void s2r_readreg(u32 ticks, u32 addr);
void s2r_writereg(u32 ticks, u32 addr, s16 value);
void s2r_writedma4(u32 ticks, u16 *data, u32 len);
void s2r_writedma7(u32 ticks, u16 *data, u32 len);
void s2r_close();
extern bool replay_mode;

13
pcsx2/SPU2/spu2.cpp
View File

@ -27,6 +27,7 @@
using namespace Threading;
MutexRecursive mtx_SPU2Status;
bool SPU2_dummy_callback = false;
#include "svnrev.h"
@ -93,9 +94,6 @@ s32 SPU2test()
// --------------------------------------------------------------------------------------
u16 *DMABaseAddr;
void (*_irqcallback)();
void (*dma4callback)();
void (*dma7callback)();
u32 SPU2ReadMemAddr(int core)
{
@ -121,13 +119,6 @@ void SPU2setLogDir(const char *dir)
CfgSetLogDir(dir);
}
void SPU2irqCallback(void (*SPU2callback)(), void (*DMA4callback)(), void (*DMA7callback)())
{
_irqcallback = SPU2callback;
dma4callback = DMA4callback;
dma7callback = DMA7callback;
}
void SPU2readDMA4Mem(u16 *pMem, u32 size) // size now in 16bit units
{
if (cyclePtr != NULL)
@ -252,6 +243,7 @@ s32 SPU2init()
}
IsInitialized = true;
SPU2_dummy_callback = false;
ReadSettings();
@ -409,6 +401,7 @@ void SPU2shutdown()
if (!IsInitialized)
return;
IsInitialized = false;
SPU2_dummy_callback = false;
ConLog("* SPU2-X: Shutting down.\n");

8
pcsx2/SPU2/spu2.h
View File

@ -23,6 +23,8 @@
extern Threading::MutexRecursive mtx_SPU2Status;
extern bool SPU2_dummy_callback;
s32 SPU2init();
s32 SPU2reset();
s32 SPU2ps1reset();
@ -53,7 +55,6 @@ void SPU2WriteMemAddr(int core, u32 value);
void SPU2setDMABaseAddr(uptr baseaddr);
void SPU2setSettingsDir(const char *dir);
void SPU2setLogDir(const char *dir);
void SPU2irqCallback(void (*SPU2callback)(), void (*DMA4callback)(), void (*DMA7callback)());
void SPU2readDMA4Mem(u16 *pMem, u32 size);
void SPU2writeDMA4Mem(u16 *pMem, u32 size);
void SPU2interruptDMA4();
@ -64,11 +65,6 @@ void SPU2writeDMA7Mem(u16 *pMem, u32 size);
extern u8 callirq;
extern void (*_irqcallback)();
extern void (*dma4callback)();
extern void (*dma7callback)();
extern s16 *input_data;
extern u32 input_data_ptr;

16
pcsx2/SPU2/spu2replay.cpp
View File

@ -143,20 +143,6 @@ int conprintf(const char *fmt, ...)
#endif
}
void dummy1()
{
}
void dummy4()
{
SPU2interruptDMA4();
}
void dummy7()
{
SPU2interruptDMA7();
}
u64 HighResFrequency()
{
u64 freq;
@ -252,7 +238,7 @@ s2r_replay(HWND hwnd, HINSTANCE hinst, LPSTR filename, int nCmdShow)
InitWaitSync(); // Initialize the WaitSync stuff
SPU2init();
SPU2irqCallback(dummy1, dummy4, dummy7);
SPU2_dummy_callback = true;
SPU2setClockPtr(&CurrentIOPCycle);
SPU2open(&hwnd);

20
pcsx2/SPU2/spu2sys.cpp
View File

@ -24,6 +24,7 @@
#include "Global.h"
#include "Dma.h"
#include "IopDma.h"
#include "spu2.h" // needed until I figure out a nice solution for irqcallback dependencies.
@ -407,8 +408,8 @@ __forceinline void TimeUpdate(u32 cClocks)
if (has_to_call_irq) {
//ConLog("* SPU2-X: Irq Called (%04x) at cycle %d.\n", Spdif.Info, Cycles);
has_to_call_irq = false;
if (_irqcallback)
_irqcallback();
if(!SPU2_dummy_callback)
spu2Irq();
}
//Update DMA4 interrupt delay counter
@ -418,8 +419,10 @@ __forceinline void TimeUpdate(u32 cClocks)
//ConLog("counter set and callback!\n");
Cores[0].MADR = Cores[0].TADR;
Cores[0].DMAICounter = 0;
if (dma4callback)
dma4callback();
if(!SPU2_dummy_callback)
spu2DMA4Irq();
else
SPU2interruptDMA4();
} else {
Cores[0].MADR += TickInterval << 1;
}
@ -432,8 +435,10 @@ __forceinline void TimeUpdate(u32 cClocks)
Cores[1].MADR = Cores[1].TADR;
Cores[1].DMAICounter = 0;
//ConLog( "* SPU2 > DMA 7 Callback! %d\n", Cycles );
if (dma7callback)
dma7callback();
if(!SPU2_dummy_callback)
spu2DMA7Irq();
else
SPU2interruptDMA7();
} else {
Cores[1].MADR += TickInterval << 1;
}
@ -693,7 +698,8 @@ void V_Core::WriteRegPS1(u32 mem, u16 value)
//ConLog("SPU direct DMA Write. Current TSA = %x\n", TSA);
if (Cores[0].IRQEnable && (Cores[0].IRQA <= Cores[0].TSA)) {
SetIrqCall(0);
_irqcallback();
if(!SPU2_dummy_callback)
spu2Irq();
}
DmaWrite(value);
show = false;