Assorted header cleanup.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1921 96395faa-99c1-11dd-bbfe-3dabce05a288

pcsx2/FiFo.cpp

@@ -15,13 +15,12 @@
 
 
 #include "PrecompiledHeader.h"
-
 #include "Common.h"
-#include "Hw.h"
-#include "GS.h"
 
+#include "GS.h"
 #include "Vif.h"
 #include "VifDma.h"
+#include "IPU/IPU.h"
 
 //////////////////////////////////////////////////////////////////////////
 /////////////////////////// Quick & dirty FIFO :D ////////////////////////
@@ -39,13 +38,6 @@
 // 0x6000 - 0x7000 : GS    (all registers map to 0x6000)
 // 0x7000 - 0x8000 : IPU   (registers map to 0x7000 and 0x7010, respectively)
 
-extern int FIFOto_write(u32* pMem, int size);
-extern void FIFOfrom_readsingle(void *value);
-
-extern int g_nIPU0Data;
-extern u8* g_pIPU0Pointer;
-extern int FOreadpos;
-
 //////////////////////////////////////////////////////////////////////////
 // ReadFIFO Pages
 

pcsx2/Gif.cpp

@@ -19,10 +19,10 @@
 #include "VU.h"
 #include "GS.h"
 #include "Gif.h"
+#include "VifDma.h"
+
 #include "iR5900.h"
 #include "Counters.h"
-
-#include "VifDma.h"
 #include "Tags.h"
 
 using std::min;

pcsx2/Gif.h

@@ -16,7 +16,8 @@
 #ifndef __GIF_H__
 #define __GIF_H__
 
-#define gifsplit 0x10000
+const int gifsplit = 0x10000;
+
 enum gifstate_t
 {
 	GIF_STATE_READY = 0,
@@ -25,15 +26,38 @@ enum gifstate_t
 	GIF_STATE_EMPTY = 0x10
 };
 
+enum Path3Modes //0 = Image Mode (DirectHL), 1 = transferring, 2 = Stopped at End of Packet
+{
+	IMAGE_MODE = 0,
+	TRANSFER_MODE = 1,
+	STOPPED_MODE = 2
+};
 
-extern void gsInterrupt();
+//GIF_STAT
-int _GIFchain();
+enum gif_stat_flags
-void GIFdma();
+{
-void dmaGIF();
+	GIF_STAT_M3R		= (1),		// GIF_MODE Mask
-void mfifoGIFtransfer(int qwc);
+	GIF_STAT_M3P		= (1<<1),	// VIF PATH3 Mask
-void gifMFIFOInterrupt();
+	GIF_STAT_IMT		= (1<<2),	// Intermittent Transfer Mode
+	GIF_STAT_PSE		= (1<<3),	// Temporary Transfer Stop
+	GIF_STAT_IP3		= (1<<5),	// Interrupted PATH3
+	GIF_STAT_P3Q		= (1<<6),	// PATH3 request Queued
+	GIF_STAT_P2Q		= (1<<7),	// PATH2 request Queued
+	GIF_STAT_P1Q		= (1<<8),	// PATH1 request Queued
+	GIF_STAT_OPH		= (1<<9),	// Output Path (Outputting Data)
+	GIF_STAT_APATH1	= (1<<10),	// Data Transfer Path 1 (In progress)
+	GIF_STAT_APATH2	= (2<<10),	// Data Transfer Path 2 (In progress)
+	GIF_STAT_APATH3	= (3<<10),	// Data Transfer Path 3 (In progress) (Mask too)
+	GIF_STAT_DIR		= (1<<12),	// Transfer Direction
+	GIF_STAT_FQC		= (31<<24)	// QWC in GIF-FIFO
+};
+
+enum gif_mode_flags
+{
+	GIF_MODE_M3R	= (1),
+	GIF_MODE_IMT		= (1<<2)
+};
 
-// Under construction; use with caution.
 union tGIF_CTRL
 {
 	struct
@@ -174,7 +198,6 @@ union tGIF_P3TAG
 
 struct GIFregisters
 {
-	// To do: Pad to the correct positions and hook up.
 	tGIF_CTRL 	ctrl;
 	u32 padding[3];
 	tGIF_MODE 	mode;
@@ -201,20 +224,13 @@ struct GIFregisters
 
 #define gifRegs ((GIFregisters*)(PS2MEM_HW+0x3000))
 
-// Quick function to see if everythings in the write position.
+extern Path3Modes Path3progress;
-/*static void checkGifRegs()
-{
-	Console::WriteLn("psHu32(GIF_CTRL) == 0x%x; gifRegs->ctrl == 0x%x", params &psHu32(GIF_CTRL),&gifRegs->ctrl);
-	Console::WriteLn("psHu32(GIF_MODE) == 0x%x; gifRegs->mode == 0x%x", params &psHu32(GIF_MODE),&gifRegs->mode);
-	Console::WriteLn("psHu32(GIF_STAT) == 0x%x; gifRegs->stat == 0x%x", params &psHu32(GIF_STAT),&gifRegs->stat);
-	Console::WriteLn("psHu32(GIF_TAG0) == 0x%x; gifRegs->tag0 == 0x%x", params &psHu32(GIF_TAG0),&gifRegs->tag0);
-	Console::WriteLn("psHu32(GIF_TAG1) == 0x%x; gifRegs->tag1 == 0x%x", params &psHu32(GIF_TAG1),&gifRegs->tag1);
-	Console::WriteLn("psHu32(GIF_TAG2) == 0x%x; gifRegs->tag2 == 0x%x", params &psHu32(GIF_TAG2),&gifRegs->tag2);
-	Console::WriteLn("psHu32(GIF_TAG3) == 0x%x; gifRegs->tag3 == 0x%x", params &psHu32(GIF_TAG3),&gifRegs->tag3);
-	Console::WriteLn("psHu32(GIF_CNT) == 0x%x; gifRegs->cnt == 0x%x", params &psHu32(GIF_CNT),&gifRegs->cnt);
-	Console::WriteLn("psHu32(GIF_P3CNT) == 0x%x; gifRegs->p3cnt == 0x%x", params &psHu32(GIF_P3CNT),&gifRegs->p3cnt);
-	Console::WriteLn("psHu32(GIF_P3TAG) == 0x%x; gifRegs->p3tag == 0x%x", params &psHu32(GIF_P3TAG),&gifRegs->p3tag);
 
-}*/
+extern void gsInterrupt();
+int _GIFchain();
+void GIFdma();
+void dmaGIF();
+void mfifoGIFtransfer(int qwc);
+void gifMFIFOInterrupt();
 
 #endif

pcsx2/Hw.h

@@ -339,88 +339,6 @@ enum DMACIrqs
 	DMAC_BUS_ERROR	= 15
 };
 
-enum vif0_stat_flags
-{
-	VIF0_STAT_VPS_W 	= (1),
-	VIF0_STAT_VPS_D 	= (2),
-	VIF0_STAT_VPS_T		= (3),
-	VIF0_STAT_VPS 		= (3),
-	VIF0_STAT_VEW		= (1<<2),
-	VIF0_STAT_MRK		= (1<<6),
-	VIF0_STAT_DBF		= (1<<7),
-	VIF0_STAT_VSS		= (1<<8),
-	VIF0_STAT_VFS		= (1<<9),
-	VIF0_STAT_VIS		= (1<<10),
-	VIF0_STAT_INT		= (1<<11),
-	VIF0_STAT_ER0		= (1<<12),
-	VIF0_STAT_ER1		= (1<<13),
-	VIF0_STAT_FQC		= (15<<24)
-};
-
-enum vif1_stat_flags
-{
-	VIF1_STAT_VPS_W 	= (1),
-	VIF1_STAT_VPS_D 	= (2),
-	VIF1_STAT_VPS_T		= (3),
-	VIF1_STAT_VPS 		= (3),
-	VIF1_STAT_VEW		= (1<<2),
-	VIF1_STAT_VGW		= (1<<3),
-	VIF1_STAT_MRK		= (1<<6),
-	VIF1_STAT_DBF		= (1<<7),
-	VIF1_STAT_VSS		= (1<<8),
-	VIF1_STAT_VFS		= (1<<9),
-	VIF1_STAT_VIS		= (1<<10),
-	VIF1_STAT_INT		= (1<<11),
-	VIF1_STAT_ER0		= (1<<12),
-	VIF1_STAT_ER1		= (1<<13),
-	VIF1_STAT_FDR 		= (1<<23),
-	VIF1_STAT_FQC		= (31<<24)
-};
-
-// These are the stat flags that are the same for vif0 & vif1,
-// for occassions where we don't neccessarily know which we are using.
-enum vif_stat_flags
-{
-	VIF_STAT_VPS_W 	= (1),
-	VIF_STAT_VPS_D 	= (2),
-	VIF_STAT_VPS_T		= (3),
-	VIF_STAT_VPS 		= (3),
-	VIF_STAT_VEW		= (1<<2),
-	VIF_STAT_MRK		= (1<<6),
-	VIF_STAT_DBF		= (1<<7),
-	VIF_STAT_VSS		= (1<<8),
-	VIF_STAT_VFS		= (1<<9),
-	VIF_STAT_VIS		= (1<<10),
-	VIF_STAT_INT		= (1<<11),
-	VIF_STAT_ER0		= (1<<12),
-	VIF_STAT_ER1		= (1<<13)
-};
-
-//GIF_STAT
-enum gif_stat_flags
-{
-	GIF_STAT_M3R		= (1),		// GIF_MODE Mask
-	GIF_STAT_M3P		= (1<<1),	// VIF PATH3 Mask
-	GIF_STAT_IMT		= (1<<2),	// Intermittent Transfer Mode
-	GIF_STAT_PSE		= (1<<3),	// Temporary Transfer Stop
-	GIF_STAT_IP3		= (1<<5),	// Interrupted PATH3
-	GIF_STAT_P3Q		= (1<<6),	// PATH3 request Queued
-	GIF_STAT_P2Q		= (1<<7),	// PATH2 request Queued
-	GIF_STAT_P1Q		= (1<<8),	// PATH1 request Queued
-	GIF_STAT_OPH		= (1<<9),	// Output Path (Outputting Data)
-	GIF_STAT_APATH1	= (1<<10),	// Data Transfer Path 1 (In progress)
-	GIF_STAT_APATH2	= (2<<10),	// Data Transfer Path 2 (In progress)
-	GIF_STAT_APATH3	= (3<<10),	// Data Transfer Path 3 (In progress) (Mask too)
-	GIF_STAT_DIR		= (1<<12),	// Transfer Direction
-	GIF_STAT_FQC		= (31<<24)	// QWC in GIF-FIFO
-};
-
-enum gif_mode_flags
-{
-	GIF_MODE_M3R	= (1),
-	GIF_MODE_IMT		= (1<<2)
-};
-
 //DMA interrupts & masks
 enum DMAInter
 {

pcsx2/IPU/IPU.cpp

@@ -18,9 +18,7 @@
 #include "Common.h"
 
 #include "IPU.h"
-#include "mpeg2lib/Mpeg.h"
 #include "yuv2rgb.h"
-#include "coroutine.h"
 
 #include "Vif.h"
 #include "Tags.h"
@@ -343,6 +341,8 @@ __forceinline void ipuWrite32(u32 mem, u32 value)
 			break;
 
 		ipucase(IPU_CTRL): // IPU_CTRL
+            // CTRL = the first 16 bits of ctrl [0x8000ffff], + value for the next 16 bits,
+            // minus the reserved bits. (18-19; 27-29) [0x47f30000]
 			ipuRegs->ctrl._u32 = (value & 0x47f30000) | (ipuRegs->ctrl._u32 & 0x8000ffff);
 			if (ipuRegs->ctrl.IDP == 3)
 			{

pcsx2/IPU/IPU.h

@@ -17,6 +17,7 @@
 #define __IPU_H__
 
 #include "mpeg2lib/Mpeg.h"
+#include "coroutine.h"
 
 // IPU_INLINE_IRQS
 // Scheduling ints into the future is a purist approach to emulation, and
@@ -33,7 +34,6 @@
 
 //#define IPU_INLINE_IRQS
 
-
 #ifdef _MSC_VER
 #pragma pack(1)
 #endif
@@ -43,7 +43,7 @@
 #define ipucase( src ) case ipumsk(src)
 
 //
-// Bitfield Structure
+// Bitfield Structures
 //
 union tIPU_CMD {
 	struct {
@@ -57,9 +57,6 @@ union tIPU_CMD {
 	};
 };
 
-//
-// Bitfield Structure
-//
 union tIPU_CTRL {
 	struct {
 		u32 IFC : 4;	// Input FIFO counter
@@ -81,9 +78,6 @@ union tIPU_CTRL {
 	u32 _u32;
 };
 
-//
-// Bitfield Structure
-//
 struct tIPU_BP {
 	u32 BP;		// Bit stream point
 	u16 IFC;	// Input FIFO counter
@@ -203,6 +197,8 @@ extern tIPU_BP g_BP;
 extern int coded_block_pattern;
 extern int g_nIPU0Data; // or 0x80000000 whenever transferring
 extern u8* g_pIPU0Pointer;
+extern int FOreadpos;
+extern void FIFOfrom_readsingle(void *value);
 
 // The IPU can only do one task at once and never uses other buffers so these
 // should be made available to functions in other modules to save registers.
@@ -215,7 +211,6 @@ extern void ipuShutdown();
 extern int  ipuFreeze(gzFile f, int Mode);
 extern bool ipuCanFreeze();
 
-
 extern u32 ipuRead32(u32 mem);
 extern u64 ipuRead64(u32 mem);
 extern void ipuWrite32(u32 mem,u32 value);

pcsx2/IPU/mpeg2lib/Mpeg.cpp

@@ -30,7 +30,6 @@
 
 #include "Common.h"
 #include "IPU/IPU.h"
-#include "IPU/coroutine.h"
 #include "Mpeg.h"
 #include "Vlc.h"
 

pcsx2/Sif.h

@@ -34,12 +34,12 @@ extern void SIF1Dma();
 extern void dmaSIF0();
 extern void dmaSIF1();
 extern void dmaSIF2();
-extern void  sif1Interrupt();
+extern void sif1Interrupt();
-extern void  sif0Interrupt();
+extern void sif0Interrupt();
-extern void  EEsif1Interrupt();
+extern void EEsif1Interrupt();
-extern void  EEsif0Interrupt();
+extern void EEsif0Interrupt();
 extern int  EEsif2Interrupt();
-int  sifFreeze(gzFile f, int Mode);
+int sifFreeze(gzFile f, int Mode);
 
 
 #endif /* __SIF_H__ */

pcsx2/VU.h

@@ -16,20 +16,23 @@
 #pragma once
 #include "Vif.h"
 
-#define REG_STATUS_FLAG	16
+enum VURegFlags
-#define REG_MAC_FLAG	17
+{
-#define REG_CLIP_FLAG	18
+    REG_STATUS_FLAG	= 16,
-#define REG_ACC_FLAG	19 // dummy flag that indicates that VFACC is written/read (nothing to do with VI[19])
+    REG_MAC_FLAG	= 17,
-#define REG_R			20
+    REG_CLIP_FLAG	= 18,
-#define REG_I			21
+    REG_ACC_FLAG	= 19, // dummy flag that indicates that VFACC is written/read (nothing to do with VI[19])
-#define REG_Q			22
+    REG_R			= 20,
-#define REG_P           23 // only exists in micromode 
+    REG_I			= 21,
-#define REG_VF0_FLAG	24 // dummy flag that indicates VF0 is read (nothing to do with VI[24])
+    REG_Q			= 22,
-#define REG_TPC			26
+    REG_P           = 23, // only exists in micromode 
-#define REG_CMSAR0		27
+    REG_VF0_FLAG	= 24, // dummy flag that indicates VF0 is read (nothing to do with VI[24])
-#define REG_FBRST		28
+    REG_TPC			= 26,
-#define REG_VPU_STAT	29
+    REG_CMSAR0		= 27,
-#define REG_CMSAR1		31
+    REG_FBRST		= 28,
+    REG_VPU_STAT	= 29,
+    REG_CMSAR1		= 31
+};
 
 //interpreter hacks, WIP
 //#define INT_VUSTALLHACK //some games work without those, big speedup
@@ -150,14 +153,16 @@ struct VURegs {
 	{
 	}
 };
-
+enum VUPipeState
-#define VUPIPE_NONE		0
+{
-#define VUPIPE_FMAC		1
+    VUPIPE_NONE = 0,
-#define VUPIPE_FDIV		2
+    VUPIPE_FMAC,
-#define VUPIPE_EFU		3
+    VUPIPE_FDIV,
-#define VUPIPE_IALU		4
+    VUPIPE_EFU,
-#define VUPIPE_BRANCH	5
+    VUPIPE_IALU,
-#define VUPIPE_XGKICK	6
+    VUPIPE_BRANCH,
+    VUPIPE_XGKICK
+};
 
 #define VUREG_READ		0x1
 #define VUREG_WRITE		0x2

pcsx2/VUmicro.h

@@ -15,6 +15,7 @@
 
 #pragma once
 #include "VU.h"
+#include "VUops.h"
 
 struct VUmicroCpu
 {
@@ -1294,19 +1295,13 @@ void (*PREFIX##_LOWER_OPCODE[128])(_VURegsNum *VUregsn) = { \
 	VUM_LOG("%s", dis##VU##MicroUF(VU.code, VU.VI[REG_TPC].UL));
 #define IdebugLOWER(VU) \
 	VUM_LOG("%s", dis##VU##MicroLF(VU.code, VU.VI[REG_TPC].UL));
+#define _vuExecMicroDebug(VU) \
+	VUM_LOG("_vuExecMicro: %8.8x", VU.VI[REG_TPC].UL);
 
 #else
 
 #define IdebugUPPER(VU)
 #define IdebugLOWER(VU)
-
-#endif
-
-#ifdef VUM_LOG
-#define _vuExecMicroDebug(VU) \
-	VUM_LOG("_vuExecMicro: %8.8x", VU.VI[REG_TPC].UL);
-#else
 #define _vuExecMicroDebug(VU)
-#endif
 
-#include "VUops.h"
+#endif

pcsx2/Vif.h

@@ -16,9 +16,61 @@
 #ifndef __VIF_H__
 #define __VIF_H__
 
-struct vifCycle {
+enum vif0_stat_flags
-	u8 cl, wl;
+{
-	u8 pad[2];
+	VIF0_STAT_VPS_W 	= (1),
+	VIF0_STAT_VPS_D 	= (2),
+	VIF0_STAT_VPS_T		= (3),
+	VIF0_STAT_VPS 		= (3),
+	VIF0_STAT_VEW		= (1<<2),
+	VIF0_STAT_MRK		= (1<<6),
+	VIF0_STAT_DBF		= (1<<7),
+	VIF0_STAT_VSS		= (1<<8),
+	VIF0_STAT_VFS		= (1<<9),
+	VIF0_STAT_VIS		= (1<<10),
+	VIF0_STAT_INT		= (1<<11),
+	VIF0_STAT_ER0		= (1<<12),
+	VIF0_STAT_ER1		= (1<<13),
+	VIF0_STAT_FQC		= (15<<24)
+};
+
+enum vif1_stat_flags
+{
+	VIF1_STAT_VPS_W 	= (1),
+	VIF1_STAT_VPS_D 	= (2),
+	VIF1_STAT_VPS_T		= (3),
+	VIF1_STAT_VPS 		= (3),
+	VIF1_STAT_VEW		= (1<<2),
+	VIF1_STAT_VGW		= (1<<3),
+	VIF1_STAT_MRK		= (1<<6),
+	VIF1_STAT_DBF		= (1<<7),
+	VIF1_STAT_VSS		= (1<<8),
+	VIF1_STAT_VFS		= (1<<9),
+	VIF1_STAT_VIS		= (1<<10),
+	VIF1_STAT_INT		= (1<<11),
+	VIF1_STAT_ER0		= (1<<12),
+	VIF1_STAT_ER1		= (1<<13),
+	VIF1_STAT_FDR 		= (1<<23),
+	VIF1_STAT_FQC		= (31<<24)
+};
+
+// These are the stat flags that are the same for vif0 & vif1,
+// for occassions where we don't neccessarily know which we are using.
+enum vif_stat_flags
+{
+	VIF_STAT_VPS_W 	= (1),
+	VIF_STAT_VPS_D 	= (2),
+	VIF_STAT_VPS_T		= (3),
+	VIF_STAT_VPS 		= (3),
+	VIF_STAT_VEW		= (1<<2),
+	VIF_STAT_MRK		= (1<<6),
+	VIF_STAT_DBF		= (1<<7),
+	VIF_STAT_VSS		= (1<<8),
+	VIF_STAT_VFS		= (1<<9),
+	VIF_STAT_VIS		= (1<<10),
+	VIF_STAT_INT		= (1<<11),
+	VIF_STAT_ER0		= (1<<12),
+	VIF_STAT_ER1		= (1<<13)
 };
 
 //
@@ -66,6 +118,11 @@ union tVIF_ERR {
 	u32 _u32;
 };
 
+struct vifCycle {
+	u8 cl, wl;
+	u8 pad[2];
+};
+
 struct VIFregisters {
 	u32 stat;
 	u32 pad0[3];
@@ -119,26 +176,6 @@ struct VIFregisters {
 	u32 addr;
 };
 
-/*enum vif_errors
-{
-	VIF_ERR_MII = 0x1,
-	VIF_ERR_ME0 = 0x2,
-	VIF_ERR_ME1 = 0x4
-};
-
-// Masks or unmasks errors
-namespace VIF_ERR
-{
-	// If true, interrupts by the i bit of Vifcode are masked.
-	static __forceinline bool MII(VIFregisters *tag) { return !!(tag->err & VIF_ERR_MII); }
-	
-	// If true, DMAtag Mismatch errors are masked. (We never check for this?)
-	static __forceinline bool ME0(VIFregisters *tag) { return !!(tag->err & VIF_ERR_ME0); }
-	
-	// If true, VifCode errors are masked.
-	static __forceinline bool ME1(VIFregisters *tag) { return !!(tag->err & VIF_ERR_ME1); }
-}*/
-
 extern "C"
 {
 	// these use cdecl for Asm code references.
@@ -148,11 +185,6 @@ extern "C"
 	extern u32* _vifCol;
 }
 
-//extern u32 setVifRowRegs(u32 reg, u32 data);
-//extern u32 getVifRowRegs(u32 reg);
-//extern u32 setVifColRegs(u32 reg, u32 data);
-//extern u32 getVifColRegs(u32 reg);
-
 #define vif0Regs ((VIFregisters*)&PS2MEM_HW[0x3800])
 #define vif1Regs ((VIFregisters*)&PS2MEM_HW[0x3c00])
 
@@ -176,5 +208,4 @@ void __fastcall SetNewMask(u32* vif1masks, u32* hasmask, u32 mask, u32 oldmask);
 
 #define XMM_R3			XMM_COL
 
-
 #endif /* __VIF_H__ */

pcsx2/VifDma.cpp

@@ -16,11 +16,11 @@
 #include "PrecompiledHeader.h"
 
 #include "Common.h"
-#include "Vif.h"
-#include "VUmicro.h"
 #include "GS.h"
 #include "Gif.h"
+#include "Vif.h"
 #include "VifDma.h"
+#include "VUmicro.h"
 #include "Tags.h"
 
 #include <xmmintrin.h>

pcsx2/VifDma.h

@@ -22,13 +22,6 @@ enum VifModes
 	VIF_CHAIN_MODE = 2
 };
 
-enum Path3Modes //0 = Image Mode (DirectHL), 1 = transferring, 2 = Stopped at End of Packet
-{
-	IMAGE_MODE = 0,
-	TRANSFER_MODE = 1,
-	STOPPED_MODE = 2
-};
-
 struct vifCode {
    u32 addr;
    u32 size;
@@ -58,7 +51,6 @@ struct vifStruct {
 };
 
 extern vifStruct vif0, vif1;
-extern Path3Modes Path3progress;
 extern u8 schedulepath3msk;
 
 void __fastcall UNPACK_S_32( u32 *dest, u32 *data, int size );

pcsx2/gui/AppMain.cpp

@@ -780,6 +780,7 @@ void AppApplySettings( const AppConfig* oldconf )
 		}
 	}
 
+    // Both AppInvokes cause unhandled runtime errors in Linux.
 	AppInvoke( MainFrame, ApplySettings() );
 	AppInvoke( CoreThread, ApplySettings( g_Conf->EmuOptions ) );
 }

pcsx2/ps2/GIFpath.cpp

@@ -16,7 +16,7 @@
 #include "PrecompiledHeader.h"
 #include "Common.h"
 #include "GS.h"
-
+#include "Gif.h"
 #include "VifDma.h"
 
 // --------------------------------------------------------------------------------------

pcsx2/x86/sVU_zerorec.cpp

@@ -31,8 +31,10 @@
 #include "Common.h"
 
 #include "GS.h"
-#include "R5900.h"
+#include "Gif.h"
 #include "VU.h"
+
+#include "R5900.h"
 #include "iR5900.h"
 
 #include "sVU_zerorec.h"