From c904878257e37c618196903dab66b81fa3a449f4 Mon Sep 17 00:00:00 2001 From: cottonvibes Date: Sat, 7 Mar 2009 04:21:26 +0000 Subject: [PATCH] implemented more microVU 'crap' :D git-svn-id: http://pcsx2.googlecode.com/svn/trunk@710 96395faa-99c1-11dd-bbfe-3dabce05a288 --- pcsx2/x86/microVU.h | 2 + pcsx2/x86/microVU_Alloc.inl | 82 ++++++++++++++++++++++++++++++++++++- pcsx2/x86/microVU_Upper.inl | 59 ++++++++++++++++++++++---- 3 files changed, 133 insertions(+), 10 deletions(-) diff --git a/pcsx2/x86/microVU.h b/pcsx2/x86/microVU.h index ce69dc76b1..d31d659694 100644 --- a/pcsx2/x86/microVU.h +++ b/pcsx2/x86/microVU.h @@ -110,6 +110,8 @@ struct microVU { u8* cache; // Dynarec Cache Start (where we will start writing the recompiled code to) u8* ptr; // Pointer to next place to write recompiled code to u32 code; // Contains the current Instruction + u32 iReg; // iReg + /* uptr x86eax; // Accumulator register. Used in arithmetic operations. uptr x86ecx; // Counter register. Used in shift/rotate instructions. diff --git a/pcsx2/x86/microVU_Alloc.inl b/pcsx2/x86/microVU_Alloc.inl index 52c3bba95d..46ea6933b9 100644 --- a/pcsx2/x86/microVU_Alloc.inl +++ b/pcsx2/x86/microVU_Alloc.inl @@ -214,7 +214,6 @@ microVUt(void) mVUallocFMAC4a(int& ACC, int& Fs, int& Ft) { microVUt(void) mVUallocFMAC4b(int& ACC, int& Fs) { microVU* mVU = mVUx; - if (!_Fd_) return; if (CHECK_VU_OVERFLOW) mVUclamp1(Fs, xmmT1, (_XYZW_SS && !_X) ? 15 : _X_Y_Z_W); mVUmergeRegs(ACC, Fs, _X_Y_Z_W); } @@ -253,6 +252,87 @@ microVUt(void) mVUallocFMAC5b(int& ACC, int& Fs) { mVUallocFMAC4b(ACC, Fs); } +//------------------------------------------------------------------ +// FMAC6 - Normal FMAC Opcodes (I Reg) +//------------------------------------------------------------------ + +#define getIreg(reg) { \ + MOV32ItoR(gprT1, mVU->iReg); \ + SSE2_MOVD_R_to_XMM(reg, gprT1); \ + if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT1, 8); \ + if (!_XYZW_SS) { mVUunpack_xyzw(reg, reg, 0); } \ +} + +microVUt(void) mVUallocFMAC6a(int& Fd, int& Fs, int& Ft) { + microVU* mVU = mVUx; + Fs = xmmFs; + Ft = xmmFt; + Fd = xmmFs; + getIreg(Ft); + if (_XYZW_SS) { + if (!_Fs_) { getZeroSS(Fs); } + else { getReg(Fs, _Fs_); } + } + else { + if (!_Fs_) { getZero(Fs); } + else { getReg(Fs, _Fs_); } + } +} + +microVUt(void) mVUallocFMAC6b(int& Fd) { + mVUallocFMAC1b(Fd); +} + +//------------------------------------------------------------------ +// FMAC7 - FMAC Opcodes Storing Result to ACC (I Reg) +//------------------------------------------------------------------ + +microVUt(void) mVUallocFMAC7a(int& ACC, int& Fs, int& Ft) { + microVU* mVU = mVUx; + Fs = xmmFs; + Ft = xmmFt; + getACC(ACC); + getIreg(Ft); + if (_XYZW_SS && _X) { + if (!_Fs_) { getZeroSS(Fs); } + else { getReg(Fs, _Fs_); } + } + else { + if (!_Fs_) { getZero4(Fs); } + else { getReg4(Fs, _Fs_); } + } +} + +microVUt(void) mVUallocFMAC7b(int& ACC, int& Fs) { + mVUallocFMAC4b(ACC, Fs); +} + +//------------------------------------------------------------------ +// FMAC17 - OPMULA FMAC Opcode +//------------------------------------------------------------------ + +microVUt(void) mVUallocFMAC17a(int& ACC, int& Fs, int& Ft) { + microVU* mVU = mVUx; + Fs = xmmFs; + Ft = xmmFt; + getACC(ACC); + + if (!_Fs_) { getZero4(Fs); } + else { getReg4(Fs, _Fs_); } + + if (!_Ft_) { getZero4(Ft); } + else { getReg4(Ft, _Ft_); } + + SSE_SHUFPS_XMM_to_XMM( Fs, Fs, 0xC9 ); // WXZY + SSE_SHUFPS_XMM_to_XMM( Ft, Ft, 0xD2 ); // WYXZ +} + +microVUt(void) mVUallocFMAC17b(int& ACC, int& Fs) { + microVU* mVU = mVUx; + if (CHECK_VU_OVERFLOW) mVUclamp1(Fs, xmmT1, _X_Y_Z_W); + mVUmergeRegs(ACC, Fs, _X_Y_Z_W); +} + //------------------------------------------------------------------ // Flag Allocators //------------------------------------------------------------------ diff --git a/pcsx2/x86/microVU_Upper.inl b/pcsx2/x86/microVU_Upper.inl index bc187fb29b..98b626b02c 100644 --- a/pcsx2/x86/microVU_Upper.inl +++ b/pcsx2/x86/microVU_Upper.inl @@ -133,6 +133,47 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw) { } \ } +#define mVU_FMAC6(operation) { \ + microVU* mVU = mVUx; \ + if (recPass == 0) {} \ + else { \ + int Fd, Fs, Ft; \ + if (isNOP) return; \ + mVUallocFMAC6a(Fd, Fs, Ft); \ + if (_XYZW_SS) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ + else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ + mVUupdateFlags(Fd, xmmT1, Ft, _X_Y_Z_W); \ + mVUallocFMAC6b(Fd); \ + } \ +} + +#define mVU_FMAC7(operation) { \ + microVU* mVU = mVUx; \ + if (recPass == 0) {} \ + else { \ + int ACC, Fs, Ft; \ + if (isNOP) return; \ + mVUallocFMAC7a(ACC, Fs, Ft); \ + if (_XYZW_SS && _X) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \ + else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ + mVUupdateFlags(Fs, xmmT1, Ft, _X_Y_Z_W); \ + mVUallocFMAC7b(ACC, Fs); \ + } \ +} + +#define mVU_FMAC17(operation) { \ + microVU* mVU = mVUx; \ + if (recPass == 0) {} \ + else { \ + int ACC, Fs, Ft; \ + if (isNOP) return; \ + mVUallocFMAC7a(ACC, Fs, Ft); \ + SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \ + mVUupdateFlags(Fs, xmmT1, Ft, _X_Y_Z_W); \ + mVUallocFMAC7b(ACC, Fs); \ + } \ +} + //------------------------------------------------------------------ // Micro VU Micromode Upper instructions //------------------------------------------------------------------ @@ -149,42 +190,42 @@ microVUf(void) mVU_ABS() { } } microVUf(void) mVU_ADD() { mVU_FMAC1(ADD); } -microVUf(void) mVU_ADDi(){} +microVUf(void) mVU_ADDi() { mVU_FMAC6(ADD); } microVUf(void) mVU_ADDq(){} microVUf(void) mVU_ADDx() { mVU_FMAC3(ADD); } microVUf(void) mVU_ADDy() { mVU_FMAC3(ADD); } microVUf(void) mVU_ADDz() { mVU_FMAC3(ADD); } microVUf(void) mVU_ADDw() { mVU_FMAC3(ADD); } microVUf(void) mVU_ADDA() { mVU_FMAC4(ADD); } -microVUf(void) mVU_ADDAi(){} +microVUf(void) mVU_ADDAi() { mVU_FMAC7(ADD); } microVUf(void) mVU_ADDAq(){} microVUf(void) mVU_ADDAx() { mVU_FMAC5(ADD); } microVUf(void) mVU_ADDAy() { mVU_FMAC5(ADD); } microVUf(void) mVU_ADDAz() { mVU_FMAC5(ADD); } microVUf(void) mVU_ADDAw() { mVU_FMAC5(ADD); } microVUf(void) mVU_SUB() { mVU_FMAC1(SUB); } -microVUf(void) mVU_SUBi(){} +microVUf(void) mVU_SUBi() { mVU_FMAC6(SUB); } microVUf(void) mVU_SUBq(){} microVUf(void) mVU_SUBx() { mVU_FMAC3(SUB); } microVUf(void) mVU_SUBy() { mVU_FMAC3(SUB); } microVUf(void) mVU_SUBz() { mVU_FMAC3(SUB); } microVUf(void) mVU_SUBw() { mVU_FMAC3(SUB); } microVUf(void) mVU_SUBA() { mVU_FMAC4(SUB); } -microVUf(void) mVU_SUBAi(){} +microVUf(void) mVU_SUBAi() { mVU_FMAC7(SUB); } microVUf(void) mVU_SUBAq(){} microVUf(void) mVU_SUBAx() { mVU_FMAC5(SUB); } microVUf(void) mVU_SUBAy() { mVU_FMAC5(SUB); } microVUf(void) mVU_SUBAz() { mVU_FMAC5(SUB); } microVUf(void) mVU_SUBAw() { mVU_FMAC5(SUB); } microVUf(void) mVU_MUL() { mVU_FMAC1(MUL); } -microVUf(void) mVU_MULi(){} +microVUf(void) mVU_MULi() { mVU_FMAC6(MUL); } microVUf(void) mVU_MULq(){} microVUf(void) mVU_MULx() { mVU_FMAC3(MUL); } microVUf(void) mVU_MULy() { mVU_FMAC3(MUL); } microVUf(void) mVU_MULz() { mVU_FMAC3(MUL); } microVUf(void) mVU_MULw() { mVU_FMAC3(MUL); } microVUf(void) mVU_MULA() { mVU_FMAC4(MUL); } -microVUf(void) mVU_MULAi(){} +microVUf(void) mVU_MULAi() { mVU_FMAC7(MUL); } microVUf(void) mVU_MULAq(){} microVUf(void) mVU_MULAx() { mVU_FMAC5(MUL); } microVUf(void) mVU_MULAy() { mVU_FMAC5(MUL); } @@ -219,18 +260,18 @@ microVUf(void) mVU_MSUBAy(){} microVUf(void) mVU_MSUBAz(){} microVUf(void) mVU_MSUBAw(){} microVUf(void) mVU_MAX() { mVU_FMAC1(MAX); } -microVUf(void) mVU_MAXi(){} +microVUf(void) mVU_MAXi() { mVU_FMAC6(MAX); } microVUf(void) mVU_MAXx() { mVU_FMAC3(MAX); } microVUf(void) mVU_MAXy() { mVU_FMAC3(MAX); } microVUf(void) mVU_MAXz() { mVU_FMAC3(MAX); } microVUf(void) mVU_MAXw() { mVU_FMAC3(MAX); } microVUf(void) mVU_MINI() { mVU_FMAC1(MIN); } -microVUf(void) mVU_MINIi(){} +microVUf(void) mVU_MINIi() { mVU_FMAC6(MIN); } microVUf(void) mVU_MINIx() { mVU_FMAC3(MIN); } microVUf(void) mVU_MINIy() { mVU_FMAC3(MIN); } microVUf(void) mVU_MINIz() { mVU_FMAC3(MIN); } microVUf(void) mVU_MINIw() { mVU_FMAC3(MIN); } -microVUf(void) mVU_OPMULA(){} +microVUf(void) mVU_OPMULA() { mVU_FMAC17(MUL); } microVUf(void) mVU_OPMSUB(){} microVUf(void) mVU_NOP(){} microVUq(void) mVU_FTOIx(uptr addr) {