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pcsx2
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git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2579 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
gigaherz 2010-02-10 14:24:01 +00:00
parent 4a6b425832
commit c8269a44a3
1 changed files with 13 additions and 3 deletions
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16
pcsx2/IopDma.cpp
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@ -274,6 +274,16 @@ struct DmaHandlerInfo
#define _ER_ 6 #define _ER_ 6
#define _ERW 7 #define _ERW 7
//////////////////////////////////////////////////////////////////////////////////////////////
// Plugin interface accessors
s32 CALLBACK spu2DmaRead (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { return SPU2dmaRead(channel,data,bytesLeft,bytesProcessed); }
s32 CALLBACK spu2DmaWrite (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { return SPU2dmaWrite(channel,data,bytesLeft,bytesProcessed); }
void CALLBACK spu2DmaInterrupt (s32 channel) { SPU2dmaInterrupt(channel); }
s32 CALLBACK dev9DmaRead (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { return DEV9dmaRead(channel,data,bytesLeft,bytesProcessed); }
s32 CALLBACK dev9DmaWrite (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { return DEV9dmaWrite(channel,data,bytesLeft,bytesProcessed); }
void CALLBACK dev9DmaInterrupt (s32 channel) { DEV9dmaInterrupt(channel); }
////////////////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////////
// Dma channel definitions // Dma channel definitions
@ -289,7 +299,7 @@ const DmaHandlerInfo IopDmaHandlers[DMA_CHANNEL_MAX] =
{"CDVD", _D__}, //3: CDVD {"CDVD", _D__}, //3: CDVD
#endif #endif
#ifdef ENABLE_NEW_IOPDMA_SPU2 #ifdef ENABLE_NEW_IOPDMA_SPU2
{"SPU2 Core0", _ERW, CHANNEL_BASE1(4), SPU2dmaRead, SPU2dmaWrite, SPU2dmaInterrupt}, //4: Spu/Spu2 Core0 {"SPU2 Core0", _ERW, CHANNEL_BASE1(4), spu2DmaRead, spu2DmaWrite, spu2DmaInterrupt}, //4: Spu/Spu2 Core0
#else #else
{"SPU2 Core0", _D__}, //4: Spu/Spu2 Core0 {"SPU2 Core0", _D__}, //4: Spu/Spu2 Core0
#endif #endif
@ -298,12 +308,12 @@ const DmaHandlerInfo IopDmaHandlers[DMA_CHANNEL_MAX] =
// Second DMAC, new in PS2 IOP // Second DMAC, new in PS2 IOP
#ifdef ENABLE_NEW_IOPDMA_SPU2 #ifdef ENABLE_NEW_IOPDMA_SPU2
{"SPU2 Core1", _ERW, CHANNEL_BASE2(0), SPU2dmaRead, SPU2dmaWrite, SPU2dmaInterrupt}, //7: Spu2 Core1 {"SPU2 Core1", _ERW, CHANNEL_BASE2(0), spu2DmaRead, spu2DmaWrite, spu2DmaInterrupt}, //7: Spu2 Core1
#else #else
{"SPU2 Core1", _D__}, //7: Spu2 Core1 {"SPU2 Core1", _D__}, //7: Spu2 Core1
#endif #endif
#ifdef ENABLE_NEW_IOPDMA_DEV9 #ifdef ENABLE_NEW_IOPDMA_DEV9
{"Dev9", _ERW, CHANNEL_BASE2(1), DEV9dmaRead, DEV9dmaWrite, DEV9dmaInterrupt}, //8: Dev9 {"Dev9", _ERW, CHANNEL_BASE2(1), dev9DmaRead, dev9DmaWrite, dev9DmaInterrupt}, //8: Dev9
#else #else
{"Dev9", _D__}, //8: Dev9 {"Dev9", _D__}, //8: Dev9
#endif #endif