mirror of https://github.com/PCSX2/pcsx2.git
MFIFO: Refactor of some of the VIF/GIF MFIFO functionality. Centralised the MFIFO resume function which should have been separate anyway.
Added some more memory address safeguards. Logging now makes a bit more sense to look at.
This commit is contained in:
refractionpcsx2
parent
810bec2d65
commit
c78b5b706d
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@ -563,6 +563,7 @@ extern void hwDmacIrq(int n);
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extern void FireMFIFOEmpty();
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extern bool hwMFIFOWrite(u32 addr, const u128* data, uint size_qwc);
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extern void hwMFIFOResume(u32 transferred);
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extern void hwDmacSrcTadrInc(DMACh& dma);
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extern bool hwDmacSrcChainWithStack(DMACh& dma, int id);
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extern bool hwDmacSrcChain(DMACh& dma, int id);
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254
pcsx2/Gif.cpp
254
pcsx2/Gif.cpp
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@ -24,14 +24,10 @@
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// A three-way toggle used to determine if the GIF is stalling (transferring) or done (finished).
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// Should be a gifstate_t rather then int, but I don't feel like possibly interfering with savestates right now.
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static int gifstate = GIF_STATE_READY;
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static bool gspath3done = false;
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static u32 gscycles = 0, prevcycles = 0, mfifocycles = 0;
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static u32 gifqwc = 0;
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static bool gifmfifoirq = false;
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__aligned16 GIF_Fifo gif_fifo;
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__aligned16 gifStruct gif;
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static __fi void GifDMAInt(int cycles) {
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if (dmacRegs.ctrl.MFD == MFD_GIF) {
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@ -44,7 +40,7 @@ static __fi void GifDMAInt(int cycles) {
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CPU_INT(DMAC_GIF, cycles);
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}
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}
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static __fi void clearFIFOstuff(bool full) {
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__fi void clearFIFOstuff(bool full) {
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CSRreg.FIFO = full ? CSR_FIFO_FULL : CSR_FIFO_EMPTY;
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}
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@ -69,6 +65,14 @@ void GIF_Fifo::init()
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memzero(readdata);
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gifRegs.stat.FQC = 0;
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CSRreg.FIFO = CSR_FIFO_EMPTY;
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gif.gifstate = GIF_STATE_READY;
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gif.gspath3done = false;
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gif.gscycles = 0;
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gif.prevcycles = 0;
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gif.mfifocycles = 0;
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gif.gifqwc = 0;
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}
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@ -205,7 +209,7 @@ __fi void gifInterrupt()
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if (!gifUnit.CanDoPath3() && gifRegs.stat.FQC == 16)
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{
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if (gifch.qwc > 0 || gspath3done == false) {
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if (gifch.qwc > 0 || gif.gspath3done == false) {
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if (!gifUnit.Path3Masked()) {
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GifDMAInt(128);
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}
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@ -238,7 +242,7 @@ __fi void gifInterrupt()
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if (!(gifch.chcr.STR)) return;
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if ((gifch.qwc > 0) || (!gspath3done)) {
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if ((gifch.qwc > 0) || (!gif.gspath3done)) {
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if (!dmacRegs.ctrl.DMAE) {
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Console.Warning("gs dma masked, re-scheduling...");
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// re-raise the int shortly in the future
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@ -257,7 +261,7 @@ __fi void gifInterrupt()
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gifRegs.stat.FQC = 0;
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clearFIFOstuff(false);
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}
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gscycles = 0;
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gif.gscycles = 0;
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gifch.chcr.STR = false;
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hwDmacIrq(DMAC_GIF);
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@ -307,14 +311,14 @@ static __fi void GIFchain() {
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// Voodoocycles
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// >> 2 so Drakan and Tekken 5 don't mess up in some PATH3 transfer. Cycles to interrupt were getting huge..
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/*if (gifch.qwc)*/
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gscycles+= _GIFchain() * BIAS; /* guessing */
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gif.gscycles+= _GIFchain() * BIAS; /* guessing */
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}
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static __fi bool checkTieBit(tDMA_TAG* &ptag)
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{
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if (gifch.chcr.TIE && ptag->IRQ) {
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GIF_LOG("dmaIrq Set");
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gspath3done = true;
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gif.gspath3done = true;
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return true;
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}
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return false;
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@ -327,9 +331,9 @@ static __fi tDMA_TAG* ReadTag()
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if (!(gifch.transfer("Gif", ptag))) return NULL;
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gifch.madr = ptag[1]._u32; //MADR = ADDR field + SPR
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gscycles += 2; // Add 1 cycles from the QW read for the tag
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gif.gscycles += 2; // Add 1 cycles from the QW read for the tag
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gspath3done = hwDmacSrcChainWithStack(gifch, ptag->ID);
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gif.gspath3done = hwDmacSrcChainWithStack(gifch, ptag->ID);
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return ptag;
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}
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@ -340,7 +344,7 @@ static __fi tDMA_TAG* ReadTag2()
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gifch.unsafeTransfer(ptag);
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gifch.madr = ptag[1]._u32;
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gspath3done = hwDmacSrcChainWithStack(gifch, ptag->ID);
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gif.gspath3done = hwDmacSrcChainWithStack(gifch, ptag->ID);
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return ptag;
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}
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@ -362,7 +366,7 @@ bool CheckPaths() {
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void GIFdma()
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{
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tDMA_TAG *ptag;
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gscycles = prevcycles;
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gif.gscycles = gif.prevcycles;
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if (gifRegs.ctrl.PSE) { // temporarily stop
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Console.WriteLn("Gif dma temp paused? (non MFIFO GIF)");
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@ -370,18 +374,18 @@ void GIFdma()
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return;
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}
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if ((dmacRegs.ctrl.STD == STD_GIF) && (prevcycles != 0)) {
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if ((dmacRegs.ctrl.STD == STD_GIF) && (gif.prevcycles != 0)) {
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//Console.WriteLn("GS Stall Control Source = %x, Drain = %x\n MADR = %x, STADR = %x", (psHu32(0xe000) >> 4) & 0x3, (psHu32(0xe000) >> 6) & 0x3, gifch.madr, psHu32(DMAC_STADR));
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if ((gifch.madr + (gifch.qwc * 16)) > dmacRegs.stadr.ADDR) {
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GifDMAInt(4);
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gscycles = 0;
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gif.gscycles = 0;
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return;
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}
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prevcycles = 0;
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gif.prevcycles = 0;
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gifch.qwc = 0;
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}
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if ((gifch.chcr.MOD == CHAIN_MODE) && (!gspath3done) && gifch.qwc == 0) // Chain Mode
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if ((gifch.chcr.MOD == CHAIN_MODE) && (!gif.gspath3done) && gifch.qwc == 0) // Chain Mode
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{
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ptag = ReadTag();
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if (ptag == NULL) return;
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@ -396,12 +400,12 @@ void GIFdma()
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// stalled.
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// We really need to test this. Pay attention to prevcycles, as it used to trigger GIFchains in the code above. (rama)
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//Console.WriteLn("GS Stall Control start Source = %x, Drain = %x\n MADR = %x, STADR = %x", (psHu32(0xe000) >> 4) & 0x3, (psHu32(0xe000) >> 6) & 0x3,gifch.madr, psHu32(DMAC_STADR));
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prevcycles = gscycles;
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gif.prevcycles = gif.gscycles;
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gifch.tadr -= 16;
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gifch.qwc = 0;
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hwDmacIrq(DMAC_STALL_SIS);
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GifDMAInt(gscycles);
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gscycles = 0;
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GifDMAInt(gif.gscycles);
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gif.gscycles = 0;
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return;
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}
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}
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@ -426,12 +430,12 @@ void GIFdma()
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GIFchain(); //Transfers the data set by the switch
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//if (gscycles < 8) DevCon.Warning("GSCycles = %d", gscycles);
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GifDMAInt(gscycles);
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GifDMAInt(gif.gscycles);
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return;
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} else if(!gspath3done) GIFdma(); //Loop round if there was a blank tag, causes hell otherwise with P3 masking games.
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} else if(!gif.gspath3done) GIFdma(); //Loop round if there was a blank tag, causes hell otherwise with P3 masking games.
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//QWC == 0 && gspath3done == true - End of DMA
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prevcycles = 0;
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gif.prevcycles = 0;
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//if (gscycles < 8) DevCon.Warning("1 GSCycles = %d", gscycles);
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GifDMAInt(16);
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}
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@ -442,7 +446,7 @@ void dmaGIF()
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//It takes the time of 24 QW for the BUS to become ready - The Punisher And Streetball
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//DevCon.Warning("dmaGIFstart chcr = %lx, madr = %lx, qwc = %lx\n tadr = %lx, asr0 = %lx, asr1 = %lx", gifch.chcr._u32, gifch.madr, gifch.qwc, gifch.tadr, gifch.asr0, gifch.asr1);
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gspath3done = false; // For some reason this doesn't clear? So when the system starts the thread, we will clear it :)
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gif.gspath3done = false; // For some reason this doesn't clear? So when the system starts the thread, we will clear it :)
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if (!CHECK_GIFFIFOHACK) {
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gifRegs.stat.FQC |= 0x10; // hack ;)
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@ -450,14 +454,14 @@ void dmaGIF()
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}
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if (gifch.chcr.MOD == NORMAL_MODE) { //Else it really is a normal transfer and we want to quit, else it gets confused with chains
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gspath3done = true;
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gif.gspath3done = true;
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}
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if(gifch.chcr.MOD == CHAIN_MODE && gifch.qwc > 0) {
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//DevCon.Warning(L"GIF QWC on Chain " + gifch.chcr.desc());
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if ((gifch.chcr.tag().ID == TAG_REFE) || (gifch.chcr.tag().ID == TAG_END) || (gifch.chcr.tag().IRQ && gifch.chcr.TIE)) {
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gspath3done = true;
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gif.gspath3done = true;
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}
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}
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@ -468,11 +472,9 @@ static u16 QWCinGIFMFIFO(u32 DrainADDR)
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{
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u32 ret;
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GIF_LOG("GIF MFIFO Requesting %x QWC from the MFIFO Base %x, SPR MADR %x Drain %x", gifch.qwc, dmacRegs.rbor.ADDR, spr0ch.madr, DrainADDR);
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SPR_LOG("GIF MFIFO Requesting %x QWC from the MFIFO Base %x, SPR MADR %x Drain %x", gifch.qwc, dmacRegs.rbor.ADDR, spr0ch.madr, DrainADDR);
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//Calculate what we have in the fifo.
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if(DrainADDR <= spr0ch.madr) {
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if (DrainADDR <= spr0ch.madr) {
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//Drain is below the write position, calculate the difference between them
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ret = (spr0ch.madr - DrainADDR) >> 4;
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}
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@ -482,17 +484,19 @@ static u16 QWCinGIFMFIFO(u32 DrainADDR)
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//calculate from base to the SPR tag addr and what is left in the top of the ring
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ret = ((spr0ch.madr - dmacRegs.rbor.ADDR) + (limit - DrainADDR)) >> 4;
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}
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if(ret == 0)
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gifstate |= GIF_STATE_EMPTY;
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if (ret == 0)
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gif.gifstate |= GIF_STATE_EMPTY;
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GIF_LOG("%x Available of the %x requested", ret, gifch.qwc);
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SPR_LOG("%x Available of the %x requested", ret, gifch.qwc);
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return ret;
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}
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static __fi bool mfifoGIFrbTransfer()
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{
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u16 qwc = std::min(QWCinGIFMFIFO(gifch.madr), gifch.qwc);
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if (qwc == 0) return true; //Lets skip all this, we don't have any data
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if (qwc == 0) {
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DevCon.Warning("GIF FIFO EMPTY before transfer (how??)");
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}
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u8* src = (u8*)PSM(gifch.madr);
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if (src == NULL) return false;
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@ -502,18 +506,22 @@ static __fi bool mfifoGIFrbTransfer()
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u32 firstTransQWC = needWrap ? MFIFOUntilEnd : qwc;
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u32 transferred;
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if (!CHECK_GIFFIFOHACK) {
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if (!CHECK_GIFFIFOHACK)
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{
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transferred = gifUnit.TransferGSPacketData(GIF_TRANS_DMA, src, firstTransQWC * 16) / 16; // First part
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}
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else {
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else
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{
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transferred = gif_fifo.write((u32*)src, firstTransQWC);
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}
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incGifChAddr(transferred);
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gifch.madr = dmacRegs.rbor.ADDR + (gifch.madr & dmacRegs.rbsr.RMSK);
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gifch.tadr = dmacRegs.rbor.ADDR + (gifch.tadr & dmacRegs.rbsr.RMSK);
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if (needWrap && transferred == MFIFOUntilEnd) { // Need to do second transfer to wrap around
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//DevCon.Warning("mfifoGIFrbTransfer() - Wrap");
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if (needWrap && transferred == MFIFOUntilEnd)
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{ // Need to do second transfer to wrap around
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u32 transferred2;
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uint secondTransQWC = qwc - MFIFOUntilEnd;
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@ -528,16 +536,13 @@ static __fi bool mfifoGIFrbTransfer()
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}
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incGifChAddr(transferred2);
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mfifocycles += (transferred2 + transferred) * 2; // guessing
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gif.mfifocycles += (transferred2 + transferred) * 2; // guessing
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}
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else {
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mfifocycles += transferred * 2; // guessing
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else
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{
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gif.mfifocycles += transferred * 2; // guessing
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}
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QWCinGIFMFIFO(gifch.madr);
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return true;
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}
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@ -545,11 +550,20 @@ static __fi bool mfifoGIFchain()
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{
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/* Is QWC = 0? if so there is nothing to transfer */
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if (gifch.qwc == 0) return true;
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//if (gifch.madr == (dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK + 16u)) DevCon.Warning("Edge Case?");
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if ((gifch.madr & ~dmacRegs.rbsr.RMSK) == dmacRegs.rbor.ADDR)
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{
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bool ret = true;
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if (QWCinGIFMFIFO(gifch.madr) == 0) {
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SPR_LOG("GIF FIFO EMPTY before transfer");
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gif.gifstate = GIF_STATE_EMPTY;
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gif.mfifocycles += 4;
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if (CHECK_GIFFIFOHACK)
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GifDMAInt(128);
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return true;
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}
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if (!mfifoGIFrbTransfer()) ret = false;
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//This ends up being done more often but it's safer :P
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@ -561,12 +575,12 @@ static __fi bool mfifoGIFchain()
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}
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else {
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int mfifoqwc;
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GIF_LOG("Non-MFIFO Location transfer doing %x Total QWC", gifch.qwc);
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SPR_LOG("Non-MFIFO Location transfer doing %x Total QWC", gifch.qwc);
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tDMA_TAG *pMem = dmaGetAddr(gifch.madr, false);
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if (pMem == NULL) return false;
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mfifoqwc = WRITERING_DMA((u32*)pMem, gifch.qwc);
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mfifocycles += (mfifoqwc) * 2; /* guessing */
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gif.mfifocycles += (mfifoqwc) * 2; /* guessing */
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}
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return true;
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@ -587,12 +601,12 @@ void mfifoGifMaskMem(int id)
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case TAG_END:
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if(gifch.madr < dmacRegs.rbor.ADDR) //probably not needed but we will check anyway.
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{
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//DevCon.Warning("GIF MFIFO MADR below bottom of ring buffer, wrapping GIF MADR = %x Ring Bottom %x", gifch.madr, dmacRegs.rbor.ADDR);
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SPR_LOG("GIF MFIFO MADR below bottom of ring buffer, wrapping GIF MADR = %x Ring Bottom %x", gifch.madr, dmacRegs.rbor.ADDR);
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gifch.madr = qwctag(gifch.madr);
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} else
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if(gifch.madr > (dmacRegs.rbor.ADDR + (u32)dmacRegs.rbsr.RMSK)) //Usual scenario is the tag is near the end (Front Mission 4)
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{
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//DevCon.Warning("GIF MFIFO MADR outside top of ring buffer, wrapping GIF MADR = %x Ring Top %x", gifch.madr, (dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK)+16);
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SPR_LOG("GIF MFIFO MADR outside top of ring buffer, wrapping GIF MADR = %x Ring Top %x", gifch.madr, (dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK)+16);
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gifch.madr = qwctag(gifch.madr);
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}
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break;
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@ -602,24 +616,11 @@ void mfifoGifMaskMem(int id)
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}
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}
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void mfifoGIFtransfer(int qwc)
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void mfifoGIFtransfer()
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{
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tDMA_TAG *ptag;
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mfifocycles = 0;
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gifmfifoirq = false;
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//DevCon.Warning("GIF MFIFO");
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if (qwc > 0 ) {
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if ((gifstate & GIF_STATE_EMPTY)) {
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GifDMAInt(4);
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gifstate &= ~GIF_STATE_EMPTY;
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}
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if (!CHECK_GIFFIFOHACK)
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{
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gifRegs.stat.FQC = 16;
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clearFIFOstuff(true);
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}
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return;
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}
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gif.mfifocycles = 0;
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if (gifRegs.ctrl.PSE) { // temporarily stop
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Console.WriteLn("Gif dma temp paused?");
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@ -628,23 +629,27 @@ void mfifoGIFtransfer(int qwc)
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}
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if (gifch.qwc == 0) {
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gifch.madr = dmacRegs.rbor.ADDR + (gifch.madr & dmacRegs.rbsr.RMSK);
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gifch.tadr = dmacRegs.rbor.ADDR + (gifch.tadr & dmacRegs.rbsr.RMSK); //Front Mission 4 tag increments to end of ring
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gifch.tadr = qwctag(gifch.tadr);
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if (QWCinGIFMFIFO(gifch.tadr) == 0) {
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SPR_LOG("GIF FIFO EMPTY before tag read");
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gif.gifstate = GIF_STATE_EMPTY;
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GifDMAInt(4);
|
||||
if (CHECK_GIFFIFOHACK)
|
||||
GifDMAInt(128);
|
||||
return;
|
||||
}
|
||||
|
||||
ptag = dmaGetAddr(gifch.tadr, false);
|
||||
gifch.unsafeTransfer(ptag);
|
||||
gifch.madr = ptag[1]._u32;
|
||||
|
||||
mfifocycles += 2;
|
||||
gif.mfifocycles += 2;
|
||||
|
||||
GIF_LOG("dmaChain %8.8x_%8.8x size=%d, id=%d, madr=%lx, tadr=%lx mfifo qwc = %x spr0 madr = %x",
|
||||
ptag[1]._u32, ptag[0]._u32, gifch.qwc, ptag->ID, gifch.madr, gifch.tadr, gifqwc, spr0ch.madr);
|
||||
|
||||
gspath3done = hwDmacSrcChainWithStack(gifch, ptag->ID);
|
||||
|
||||
ptag[1]._u32, ptag[0]._u32, gifch.qwc, ptag->ID, gifch.madr, gifch.tadr, gif.gifqwc, spr0ch.madr);
|
||||
|
||||
gif.gspath3done = hwDmacSrcChainWithStack(gifch, ptag->ID);
|
||||
|
||||
if (dmacRegs.ctrl.STD == STD_GIF && (ptag->ID == TAG_REFS))
|
||||
{
|
||||
|
|
@ -652,24 +657,21 @@ void mfifoGIFtransfer(int qwc)
|
|||
}
|
||||
mfifoGifMaskMem(ptag->ID);
|
||||
|
||||
if(gspath3done) gifstate = GIF_STATE_DONE;
|
||||
else gifstate = GIF_STATE_READY;
|
||||
gifch.tadr = qwctag(gifch.tadr);
|
||||
|
||||
if ((gifch.chcr.TIE) && (ptag->IRQ)) {
|
||||
SPR_LOG("dmaIrq Set");
|
||||
gifstate = GIF_STATE_DONE;
|
||||
gifmfifoirq = true;
|
||||
gif.gspath3done = true;
|
||||
}
|
||||
QWCinGIFMFIFO(gifch.tadr);
|
||||
}
|
||||
|
||||
if (!mfifoGIFchain()) {
|
||||
Console.WriteLn("GIF dmaChain error size=%d, madr=%lx, tadr=%lx", gifch.qwc, gifch.madr, gifch.tadr);
|
||||
gifstate = GIF_STATE_STALL;
|
||||
Console.WriteLn("mfifoGIF dmaChain error size=%d, madr=%lx, tadr=%lx", gifch.qwc, gifch.madr, gifch.tadr);
|
||||
gif.gspath3done = true;
|
||||
gifch.qwc = 0; //Sanity
|
||||
}
|
||||
|
||||
if ((gifch.qwc == 0) && (gifstate & GIF_STATE_DONE)) gifstate |= GIF_STATE_STALL;
|
||||
GifDMAInt(mfifocycles);
|
||||
GifDMAInt(std::max(gif.mfifocycles, (u32)4));
|
||||
|
||||
SPR_LOG("mfifoGIFtransfer end %x madr %x, tadr %x", gifch.chcr._u32, gifch.madr, gifch.tadr);
|
||||
}
|
||||
|
|
@ -677,7 +679,13 @@ void mfifoGIFtransfer(int qwc)
|
|||
void gifMFIFOInterrupt()
|
||||
{
|
||||
GIF_LOG("gifMFIFOInterrupt");
|
||||
mfifocycles = 0;
|
||||
gif.mfifocycles = 0;
|
||||
|
||||
if (dmacRegs.ctrl.MFD != MFD_GIF) { // GIF not in MFIFO anymore, come out.
|
||||
DevCon.WriteLn("GIF Leaving MFIFO - Report if any errors");
|
||||
gifInterrupt();
|
||||
return;
|
||||
}
|
||||
|
||||
gifCheckPathStatus();
|
||||
|
||||
|
|
@ -700,20 +708,24 @@ void gifMFIFOInterrupt()
|
|||
|
||||
}
|
||||
|
||||
if (CHECK_GIFFIFOHACK) {
|
||||
|
||||
if (int amtRead = gif_fifo.read(true)) {
|
||||
if (gifUnit.gsSIGNAL.queued) {
|
||||
GifDMAInt(128);
|
||||
return;
|
||||
}
|
||||
|
||||
if (CHECK_GIFFIFOHACK)
|
||||
{
|
||||
if (int amtRead = gif_fifo.read(true))
|
||||
{
|
||||
if (!gifUnit.Path3Masked() || gifRegs.stat.FQC < 16) {
|
||||
GifDMAInt(amtRead * BIAS);
|
||||
return;
|
||||
}
|
||||
}
|
||||
else {
|
||||
|
||||
if (!gifUnit.CanDoPath3() && gifRegs.stat.FQC == 16)
|
||||
{
|
||||
if (gifch.qwc > 0 || gspath3done == false) {
|
||||
if (gifch.qwc > 0 || gif.gspath3done == false) {
|
||||
if (!gifUnit.Path3Masked()) {
|
||||
GifDMAInt(128);
|
||||
}
|
||||
|
|
@ -740,74 +752,38 @@ void gifMFIFOInterrupt()
|
|||
}
|
||||
return;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if (!gifch.chcr.STR) {
|
||||
Console.WriteLn("WTF GIFMFIFO");
|
||||
cpuRegs.interrupt &= ~(1 << 11);
|
||||
return;
|
||||
}
|
||||
|
||||
if (gifch.qwc > 0 || !gspath3done) {
|
||||
if (dmacRegs.ctrl.MFD != MFD_GIF) {
|
||||
DevCon.Warning("Not in GIF MFIFO mode! Stopping GIF MFIFO");
|
||||
return;
|
||||
}
|
||||
|
||||
if (gifUnit.gsSIGNAL.queued) {
|
||||
//DevCon.WriteLn("Path 3 Paused");
|
||||
GifDMAInt(128);
|
||||
return;
|
||||
}
|
||||
|
||||
if ((gifstate & GIF_STATE_EMPTY)) {
|
||||
if ((gif.gifstate & GIF_STATE_EMPTY)) {
|
||||
FireMFIFOEmpty();
|
||||
if (CHECK_GIFFIFOHACK)
|
||||
GifDMAInt(128);
|
||||
if (!(gifstate & GIF_STATE_STALL)) return;
|
||||
return;
|
||||
}
|
||||
|
||||
if (gifch.qwc > 0 || !gif.gspath3done) {
|
||||
|
||||
if (!CheckPaths()) return;
|
||||
|
||||
if (!(gifstate & GIF_STATE_STALL)) {
|
||||
|
||||
if (QWCinGIFMFIFO(gifch.tadr) == 0) {
|
||||
GifDMAInt(4);
|
||||
if (CHECK_GIFFIFOHACK)
|
||||
GifDMAInt(128);
|
||||
mfifoGIFtransfer();
|
||||
return;
|
||||
}
|
||||
mfifoGIFtransfer(0);
|
||||
return;
|
||||
}
|
||||
|
||||
if ((gifstate == GIF_STATE_READY) || (gifch.qwc > 0)) {
|
||||
DevCon.Error("gifMFIFO Panic > Shouldn't go here!");
|
||||
return;
|
||||
}
|
||||
|
||||
if (gifRegs.stat.FQC > 0) {
|
||||
//DevCon.Warning("GIF Ending with stuff still in it?");
|
||||
GifDMAInt(16);
|
||||
return;
|
||||
}
|
||||
}
|
||||
//if(gifqwc > 0) Console.WriteLn("GIF MFIFO ending with stuff in it %x", gifqwc);
|
||||
|
||||
|
||||
if (!CHECK_GIFFIFOHACK)
|
||||
{
|
||||
gifRegs.stat.FQC = 0;
|
||||
clearFIFOstuff(false);
|
||||
}
|
||||
//vif1Regs.stat.VGW = false; // old code had this
|
||||
|
||||
if (!gifmfifoirq) gifqwc = 0;
|
||||
|
||||
gscycles = 0;
|
||||
gif.gscycles = 0;
|
||||
|
||||
gifch.chcr.STR = false;
|
||||
gifstate = GIF_STATE_READY;
|
||||
gif.gifstate = GIF_STATE_READY;
|
||||
hwDmacIrq(DMAC_GIF);
|
||||
DMA_LOG("GIF MFIFO DMA End");
|
||||
}
|
||||
|
|
@ -815,9 +791,9 @@ void gifMFIFOInterrupt()
|
|||
void SaveStateBase::gifDmaFreeze() {
|
||||
// Note: mfifocycles is not a persistent var, so no need to save it here.
|
||||
FreezeTag("GIFdma");
|
||||
Freeze(gifstate);
|
||||
Freeze(gifqwc);
|
||||
Freeze(gspath3done);
|
||||
Freeze(gscycles);
|
||||
Freeze(gif.gifstate);
|
||||
Freeze(gif.gifqwc);
|
||||
Freeze(gif.gspath3done);
|
||||
Freeze(gif.gscycles);
|
||||
Freeze(gif_fifo);
|
||||
}
|
||||
|
|
|
|||
18
pcsx2/Gif.h
18
pcsx2/Gif.h
|
|
@ -87,11 +87,22 @@ enum GIF_REG {
|
|||
|
||||
enum gifstate_t {
|
||||
GIF_STATE_READY = 0,
|
||||
GIF_STATE_STALL = 1,
|
||||
GIF_STATE_DONE = 2,
|
||||
GIF_STATE_EMPTY = 0x10
|
||||
};
|
||||
|
||||
struct gifStruct {
|
||||
int gifstate;
|
||||
bool gspath3done;
|
||||
|
||||
u32 gscycles;
|
||||
u32 prevcycles;
|
||||
u32 mfifocycles;
|
||||
u32 gifqwc;
|
||||
bool gifmfifoirq;
|
||||
};
|
||||
|
||||
extern __aligned16 gifStruct gif;
|
||||
|
||||
struct GIF_Fifo
|
||||
{
|
||||
unsigned int data[64]; //16 QW FIFO
|
||||
|
|
@ -300,5 +311,6 @@ extern void gifInterrupt();
|
|||
extern int _GIFchain();
|
||||
extern void GIFdma();
|
||||
extern void dmaGIF();
|
||||
extern void mfifoGIFtransfer(int qwc);
|
||||
extern void mfifoGIFtransfer();
|
||||
extern void gifMFIFOInterrupt();
|
||||
extern void clearFIFOstuff(bool full);
|
||||
|
|
|
|||
48
pcsx2/Hw.cpp
48
pcsx2/Hw.cpp
|
|
@ -174,6 +174,54 @@ __ri bool hwMFIFOWrite(u32 addr, const u128* data, uint qwc)
|
|||
return true;
|
||||
}
|
||||
|
||||
__ri void hwMFIFOResume(u32 transferred) {
|
||||
|
||||
if (transferred == 0)
|
||||
{
|
||||
return; //Nothing got put in the MFIFO, we don't care
|
||||
}
|
||||
|
||||
switch (dmacRegs.ctrl.MFD)
|
||||
{
|
||||
case MFD_VIF1: // Most common case.
|
||||
{
|
||||
SPR_LOG("Added %x qw to mfifo, Vif CHCR %x Stalled %x done %x", transferred, vif1ch.chcr._u32, vif1.vifstalled.enabled, vif1.done);
|
||||
if (vif1.inprogress & 0x10)
|
||||
{
|
||||
vif1.inprogress &= ~0x10;
|
||||
//Don't resume if stalled or already looping
|
||||
if (vif1ch.chcr.STR && !(cpuRegs.interrupt & (1 << DMAC_MFIFO_VIF)) && !vif1Regs.stat.INT)
|
||||
{
|
||||
SPR_LOG("Data Added, Resuming");
|
||||
//Need to simulate the time it takes to copy here, if the VIF resumes before the SPR has finished, it isn't happy.
|
||||
CPU_INT(DMAC_MFIFO_VIF, transferred * BIAS);
|
||||
}
|
||||
|
||||
//Apparently this is bad, i guess so, the data is going to memory rather than the FIFO
|
||||
//vif1Regs.stat.FQC = 0x10; // FQC=16
|
||||
}
|
||||
break;
|
||||
}
|
||||
case MFD_GIF:
|
||||
{
|
||||
SPR_LOG("Added %x qw to mfifo, Gif CHCR %x done %x", transferred, gifch.chcr._u32, gif.gspath3done);
|
||||
if ((gif.gifstate & GIF_STATE_EMPTY)) {
|
||||
CPU_INT(DMAC_MFIFO_GIF, transferred * BIAS);
|
||||
gif.gifstate = GIF_STATE_READY;
|
||||
}
|
||||
if (!CHECK_GIFFIFOHACK)
|
||||
{
|
||||
gifRegs.stat.FQC = 16;
|
||||
//GIF FIFO
|
||||
clearFIFOstuff(true);
|
||||
}
|
||||
break;
|
||||
}
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
__ri bool hwDmacSrcChainWithStack(DMACh& dma, int id) {
|
||||
switch (id) {
|
||||
case TAG_REFE: // Refe - Transfer Packet According to ADDR field
|
||||
|
|
|
|||
|
|
@ -20,8 +20,6 @@
|
|||
#include "VUmicro.h"
|
||||
#include "MTVU.h"
|
||||
|
||||
extern void mfifoGIFtransfer(int);
|
||||
|
||||
static bool spr0finished = false;
|
||||
static bool spr1finished = false;
|
||||
static bool spr0lastqwc = false;
|
||||
|
|
@ -297,20 +295,12 @@ void SPRFROMinterrupt()
|
|||
switch (dmacRegs.ctrl.MFD)
|
||||
{
|
||||
case MFD_VIF1: // Most common case.
|
||||
{
|
||||
if ((spr0ch.madr & ~dmacRegs.rbsr.RMSK) != dmacRegs.rbor.ADDR) Console.WriteLn("VIF MFIFO Write outside MFIFO area");
|
||||
spr0ch.madr = dmacRegs.rbor.ADDR + (spr0ch.madr & dmacRegs.rbsr.RMSK);
|
||||
//Console.WriteLn("mfifoVIF1transfer %x madr %x, tadr %x", vif1ch.chcr._u32, vif1ch.madr, vif1ch.tadr);
|
||||
mfifoVIF1transfer(mfifotransferred);
|
||||
mfifotransferred = 0;
|
||||
break;
|
||||
}
|
||||
case MFD_GIF:
|
||||
{
|
||||
if ((spr0ch.madr & ~dmacRegs.rbsr.RMSK) != dmacRegs.rbor.ADDR) Console.WriteLn("GIF MFIFO Write outside MFIFO area");
|
||||
spr0ch.madr = dmacRegs.rbor.ADDR + (spr0ch.madr & dmacRegs.rbsr.RMSK);
|
||||
//Console.WriteLn("mfifoGIFtransfer %x madr %x, tadr %x", gif->chcr._u32, gif->madr, gif->tadr);
|
||||
mfifoGIFtransfer(mfifotransferred);
|
||||
hwMFIFOResume(mfifotransferred);
|
||||
mfifotransferred = 0;
|
||||
break;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -245,7 +245,7 @@ static VIFregisters& vif1Regs = (VIFregisters&)eeHw[0x3C00];
|
|||
|
||||
extern void dmaVIF0();
|
||||
extern void dmaVIF1();
|
||||
extern void mfifoVIF1transfer(int qwc);
|
||||
extern void mfifoVIF1transfer();
|
||||
extern bool VIF0transfer(u32 *data, int size, bool TTE=0);
|
||||
extern bool VIF1transfer(u32 *data, int size, bool TTE=0);
|
||||
extern void vifMFIFOInterrupt();
|
||||
|
|
|
|||
|
|
@ -30,7 +30,6 @@ static u16 QWCinVIFMFIFO(u32 DrainADDR)
|
|||
{
|
||||
u32 ret;
|
||||
|
||||
|
||||
SPR_LOG("VIF MFIFO Requesting %x QWC from the MFIFO Base %x MFIFO Top %x, SPR MADR %x Drain %x", vif1ch.qwc, dmacRegs.rbor.ADDR, dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK + 16, spr0ch.madr, DrainADDR);
|
||||
//Calculate what we have in the fifo.
|
||||
if(DrainADDR <= spr0ch.madr)
|
||||
|
|
@ -57,7 +56,10 @@ static __fi bool mfifoVIF1rbTransfer()
|
|||
u32 *src;
|
||||
bool ret;
|
||||
|
||||
if(mfifoqwc == 0) return true; //Cant do anything, lets forget it
|
||||
if (mfifoqwc == 0) {
|
||||
DevCon.Warning("VIF MFIFO no QWC before transfer (in transfer function, bit late really)");
|
||||
return true; //Cant do anything, lets forget it
|
||||
}
|
||||
|
||||
/* Check if the transfer should wrap around the ring buffer */
|
||||
if ((vif1ch.madr + (mfifoqwc << 4)) > (msize))
|
||||
|
|
@ -81,13 +83,14 @@ static __fi bool mfifoVIF1rbTransfer()
|
|||
{
|
||||
if(vif1.irqoffset.value != 0) DevCon.Warning("VIF1 MFIFO Offest != 0! vifoffset=%x", vif1.irqoffset.value);
|
||||
/* and second copy 's2' bytes from 'maddr' to '&data[s1]' */
|
||||
vif1ch.madr = maddr;
|
||||
//DevCon.Warning("Loopyloop");
|
||||
vif1ch.tadr = qwctag(vif1ch.tadr);
|
||||
vif1ch.madr = qwctag(vif1ch.madr);
|
||||
|
||||
src = (u32*)PSM(maddr);
|
||||
src = (u32*)PSM(vif1ch.madr);
|
||||
if (src == NULL) return false;
|
||||
VIF1transfer(src, ((mfifoqwc << 2) - s1));
|
||||
}
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -101,7 +104,6 @@ static __fi bool mfifoVIF1rbTransfer()
|
|||
ret = VIF1transfer(src + vif1.irqoffset.value, mfifoqwc * 4 - vif1.irqoffset.value);
|
||||
else
|
||||
ret = VIF1transfer(src, mfifoqwc << 2);
|
||||
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -119,14 +121,16 @@ static __fi void mfifo_VIF1chain()
|
|||
vif1ch.madr < (dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK + 16u))
|
||||
{
|
||||
//if(vif1ch.madr == (dmacRegs.rbor.ADDR + dmacRegs.rbsr.RMSK + 16)) DevCon.Warning("Edge VIF1");
|
||||
if (QWCinVIFMFIFO(vif1ch.madr) == 0) {
|
||||
SPR_LOG("VIF MFIFO Empty before transfer");
|
||||
vif1.inprogress |= 0x10;
|
||||
g_vif1Cycles += 4;
|
||||
return;
|
||||
}
|
||||
|
||||
vif1ch.madr = qwctag(vif1ch.madr);
|
||||
mfifoVIF1rbTransfer();
|
||||
vif1ch.tadr = qwctag(vif1ch.tadr);
|
||||
vif1ch.madr = qwctag(vif1ch.madr);
|
||||
if(QWCinVIFMFIFO(vif1ch.madr) == 0) vif1.inprogress |= 0x10;
|
||||
|
||||
//vifqwc -= startqwc - vif1ch.qwc;
|
||||
|
||||
}
|
||||
else
|
||||
|
|
@ -171,36 +175,21 @@ void mfifoVifMaskMem(int id)
|
|||
}
|
||||
}
|
||||
|
||||
void mfifoVIF1transfer(int qwc)
|
||||
void mfifoVIF1transfer()
|
||||
{
|
||||
tDMA_TAG *ptag;
|
||||
|
||||
g_vif1Cycles = 0;
|
||||
|
||||
if (qwc > 0)
|
||||
if (vif1ch.qwc == 0)
|
||||
{
|
||||
//vifqwc += qwc;
|
||||
SPR_LOG("Added %x qw to mfifo,Vif CHCR %x Stalled %x done %x", qwc, vif1ch.chcr._u32, vif1.vifstalled.enabled, vif1.done);
|
||||
if (vif1.inprogress & 0x10)
|
||||
{
|
||||
//Don't resume if stalled or already looping
|
||||
if(vif1ch.chcr.STR && !(cpuRegs.interrupt & (1<<DMAC_MFIFO_VIF)) && !vif1Regs.stat.INT)
|
||||
{
|
||||
SPR_LOG("Data Added, Resuming");
|
||||
//Need to simulate the time it takes to copy here, if the VIF resumes before the SPR has finished, it isn't happy.
|
||||
CPU_INT(DMAC_MFIFO_VIF, qwc * BIAS);
|
||||
}
|
||||
|
||||
//Apparently this is bad, i guess so, the data is going to memory rather than the FIFO
|
||||
//vif1Regs.stat.FQC = 0x10; // FQC=16
|
||||
}
|
||||
vif1.inprogress &= ~0x10;
|
||||
|
||||
if (QWCinVIFMFIFO(vif1ch.tadr) == 0) {
|
||||
SPR_LOG("VIF MFIFO Empty before tag");
|
||||
vif1.inprogress |= 0x10;
|
||||
g_vif1Cycles += 4;
|
||||
return;
|
||||
}
|
||||
|
||||
if (vif1ch.qwc == 0)
|
||||
{
|
||||
vif1ch.tadr = qwctag(vif1ch.tadr);
|
||||
ptag = dmaGetAddr(vif1ch.tadr, false);
|
||||
|
||||
|
|
@ -230,7 +219,6 @@ void mfifoVIF1transfer(int qwc)
|
|||
vif1.irqoffset.value = 2;
|
||||
vif1.irqoffset.enabled = true;
|
||||
ret = VIF1transfer((u32*)&masked_tag + 2, 2, true); //Transfer Tag
|
||||
//ret = VIF1transfer((u32*)ptag + 2, 2); //Transfer Tag
|
||||
}
|
||||
|
||||
if (!ret && vif1.irqoffset.enabled)
|
||||
|
|
@ -238,7 +226,7 @@ void mfifoVIF1transfer(int qwc)
|
|||
vif1.inprogress &= ~1;
|
||||
return; //IRQ set by VIFTransfer
|
||||
|
||||
} //else vif1.vifstalled.enabled = false;
|
||||
}
|
||||
g_vif1Cycles += 2;
|
||||
}
|
||||
|
||||
|
|
@ -249,8 +237,6 @@ void mfifoVIF1transfer(int qwc)
|
|||
|
||||
vif1ch.madr = ptag[1]._u32;
|
||||
|
||||
//vifqwc--;
|
||||
|
||||
SPR_LOG("dmaChain %8.8x_%8.8x size=%d, id=%d, madr=%lx, tadr=%lx mfifo qwc = %x spr0 madr = %x",
|
||||
ptag[1]._u32, ptag[0]._u32, vif1ch.qwc, ptag->ID, vif1ch.madr, vif1ch.tadr, vifqwc, spr0ch.madr);
|
||||
|
||||
|
|
@ -264,12 +250,9 @@ void mfifoVIF1transfer(int qwc)
|
|||
vif1.done = true;
|
||||
}
|
||||
|
||||
|
||||
if(vif1ch.qwc > 0) vif1.inprogress |= 1;
|
||||
|
||||
vif1ch.tadr = qwctag(vif1ch.tadr);
|
||||
|
||||
if(QWCinVIFMFIFO(vif1ch.tadr) == 0) vif1.inprogress |= 0x10;
|
||||
if(vif1ch.qwc > 0) vif1.inprogress |= 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -285,6 +268,11 @@ void vifMFIFOInterrupt()
|
|||
g_vif1Cycles = 0;
|
||||
VIF_LOG("vif mfifo interrupt");
|
||||
|
||||
if (dmacRegs.ctrl.MFD != MFD_VIF1) {
|
||||
vif1Interrupt();
|
||||
return;
|
||||
}
|
||||
|
||||
if( gifRegs.stat.APATH == 2 && gifUnit.gifPath[1].isDone())
|
||||
{
|
||||
gifRegs.stat.APATH = 0;
|
||||
|
|
@ -293,11 +281,6 @@ void vifMFIFOInterrupt()
|
|||
if(gifUnit.checkPaths(1,0,1)) gifUnit.Execute(false, true);
|
||||
}
|
||||
|
||||
if (dmacRegs.ctrl.MFD != MFD_VIF1) {
|
||||
DevCon.Warning("Not in VIF MFIFO mode! Stopping VIF MFIFO");
|
||||
return;
|
||||
}
|
||||
|
||||
if (vif1ch.chcr.DIR) {
|
||||
bool isDirect = (vif1.cmd & 0x7f) == 0x50;
|
||||
bool isDirectHL = (vif1.cmd & 0x7f) == 0x51;
|
||||
|
|
@ -354,7 +337,7 @@ void vifMFIFOInterrupt()
|
|||
|
||||
if(vif1.inprogress & 0x10) {
|
||||
FireMFIFOEmpty();
|
||||
if(!(vif1.done && vif1ch.qwc == 0))return;
|
||||
return;
|
||||
}
|
||||
|
||||
vif1.vifstalled.enabled = false;
|
||||
|
|
@ -362,13 +345,7 @@ void vifMFIFOInterrupt()
|
|||
if (!vif1.done || vif1ch.qwc) {
|
||||
switch(vif1.inprogress & 1) {
|
||||
case 0: //Set up transfer
|
||||
if (QWCinVIFMFIFO(vif1ch.tadr) == 0) {
|
||||
vif1.inprogress |= 0x10;
|
||||
CPU_INT(DMAC_MFIFO_VIF, 4 );
|
||||
return;
|
||||
}
|
||||
|
||||
mfifoVIF1transfer(0);
|
||||
mfifoVIF1transfer();
|
||||
vif1Regs.stat.FQC = std::min((u16)0x10, vif1ch.qwc);
|
||||
|
||||
case 1: //Transfer data
|
||||
|
|
|
|||
Loading…
Reference in New Issue