diff --git a/pcsx2/Vif_Unpack.cpp b/pcsx2/Vif_Unpack.cpp
index 76bc1f60fa..6aabf00139 100644
--- a/pcsx2/Vif_Unpack.cpp
+++ b/pcsx2/Vif_Unpack.cpp
@@ -188,7 +188,7 @@ _vifT void vifUnpackSetup(const u32 *data) {
 	vifStruct& vifX = GetVifX;
 
 	if ((vifXRegs.cycle.wl == 0) && (vifXRegs.cycle.wl < vifXRegs.cycle.cl)) {
-        Console.WriteLn("Vif%d CL %d, WL %d", idx, vifXRegs.cycle.cl, vifXRegs.cycle.wl);
+        DevCon.WriteLn("Vif%d CL %d, WL %d", idx, vifXRegs.cycle.cl, vifXRegs.cycle.wl);
 		vifX.cmd = 0;
         return; // Skipping write and 0 write-cycles, so do nothing!
 	}
diff --git a/pcsx2/x86/microVU_Analyze.inl b/pcsx2/x86/microVU_Analyze.inl
index 1e4f8c6301..c91d8a3bfe 100644
--- a/pcsx2/x86/microVU_Analyze.inl
+++ b/pcsx2/x86/microVU_Analyze.inl
@@ -383,7 +383,7 @@ static void analyzeBranchVI(mV, int xReg, bool &infoVar) {
 			infoVar = 1;
 		}
 		iPC = bPC;
-		Console.WriteLn(Color_Green, "microVU%d: Branch VI-Delay (%d) [%04x]", getIndex, j+1, xPC);
+		DevCon.WriteLn(Color_Green, "microVU%d: Branch VI-Delay (%d) [%04x]", getIndex, j+1, xPC);
 	}
 	else iPC = bPC;
 }
@@ -420,7 +420,7 @@ __fi void analyzeBranchVI(mV, int xReg, bool &infoVar) {
 			infoVar = 1;
 		}
 		iPC = bPC;
-		Console.WriteLn( Color_Green, "microVU%d: Branch VI-Delay (%d) [%04x]", getIndex, i, xPC);
+		DevCon.WriteLn( Color_Green, "microVU%d: Branch VI-Delay (%d) [%04x]", getIndex, i, xPC);
 	}
 	else iPC = bPC;
 }
@@ -436,7 +436,7 @@ __ri int mVUbranchCheck(mV) {
 		mVUlow.evilBranch = 1;
 		mVUregs.blockType = 2;
 		mVUregs.needExactMatch |= 7; // This might not be necessary, but w/e...
-		Console.Warning("microVU%d Warning: Branch in Branch delay slot! [%04x]", mVU->index, xPC);
+		DevCon.Warning("microVU%d Warning: Branch in Branch delay slot! [%04x]", mVU->index, xPC);
 		return 1;
 	}
 	incPC(2);
diff --git a/pcsx2/x86/microVU_Compile.inl b/pcsx2/x86/microVU_Compile.inl
index aa08b473f8..2805856ab7 100644
--- a/pcsx2/x86/microVU_Compile.inl
+++ b/pcsx2/x86/microVU_Compile.inl
@@ -109,7 +109,7 @@ static void doIbit(mV) {
 		mVU->regAlloc->clearRegVF(33);
 
 		if (CHECK_VU_OVERFLOW && ((curI & 0x7fffffff) >= 0x7f800000)) {
-			Console.WriteLn(Color_Green,"microVU%d: Clamping I Reg", mVU->index);
+			DevCon.WriteLn(Color_Green,"microVU%d: Clamping I Reg", mVU->index);
 			tempI = (0x80000000 & curI) | 0x7f7fffff; // Clamp I Reg
 		}
 		else tempI = curI;
@@ -372,7 +372,7 @@ static void mVUtestCycles(microVU* mVU) {
 
 // This gets run at the start of every loop of mVU's first pass
 static __fi void startLoop(mV) {
-	if (curI & _Mbit_)	{ Console.WriteLn(Color_Green, "microVU%d: M-bit set!", getIndex); }
+	if (curI & _Mbit_)	{ DevCon.WriteLn (Color_Green, "microVU%d: M-bit set!", getIndex); }
 	if (curI & _Dbit_)	{ DevCon.WriteLn (Color_Green, "microVU%d: D-bit set!", getIndex); }
 	if (curI & _Tbit_)	{ DevCon.WriteLn (Color_Green, "microVU%d: T-bit set!", getIndex); }
 	memzero(mVUinfo);