mirror of https://github.com/PCSX2/pcsx2.git
Fixed bugs in LDL/LDR instructions; fixing various TLB Miss errors in assorted games (namely ones that worked in the old VM builds). The instructions were not sign-extending values into the upper 32 bits of the target register. (LDR in particular has odd rules for sign extension)
Some minor cleanups / correctness fixes to the IPU's register Read/Write functions. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@600 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine
parent
795152e7e1
commit
c46ef87c89
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@ -236,11 +236,17 @@ bool ipuCanFreeze()
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__forceinline u32 ipuRead32(u32 mem)
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{
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// Note: It's assumed that mem's input value is always in the 0x10002000 page
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// of memory (if not, it's probably bad code).
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jASSUME( ( mem & ~0xff ) == 0x10002000 );
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mem &= 0xff; // ipu repeats every 0x100
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IPUProcessInterrupt();
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switch (mem){
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case 0x10002010: // IPU_CTRL
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switch( mem )
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{
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case 0x10: // IPU_CTRL
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ipuRegs->ctrl.IFC = g_BP.IFC;
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//ipuRegs->ctrl.OFC = min(g_nIPU0Data, 8); // check if transfering to ipu0
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ipuRegs->ctrl.CBP = coded_block_pattern;
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@ -250,7 +256,7 @@ __forceinline u32 ipuRead32(u32 mem)
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return ipuRegs->ctrl._u32;
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case 0x10002020: // IPU_BP
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case 0x20: // IPU_BP
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ipuRegs->ipubp = g_BP.BP & 0x7f;
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ipuRegs->ipubp |= g_BP.IFC<<8;
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@ -260,23 +266,22 @@ __forceinline u32 ipuRead32(u32 mem)
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return ipuRegs->ipubp;
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}
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return *(u32*)(((u8*)ipuRegs)+(mem&0xff)); // ipu repeats every 0x100
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return *(u32*)(((u8*)ipuRegs)+mem);
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}
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__forceinline u64 ipuRead64(u32 mem)
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{
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// Note: It's assumed that mem's input value is always in the 0x10002000 page
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// of memory (if not, it's probably bad code).
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jASSUME( ( mem & ~0xff ) == 0x10002000 );
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mem &= 0xff; // ipu repeats every 0x100
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IPUProcessInterrupt();
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#ifdef PCSX2_DEVBUILD
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if( mem == 0x10002010 ) {
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Console::Notice("reading 64bit IPU ctrl");
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}
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if( mem == 0x10002020 ) {
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Console::Notice("reading 64bit IPU top");
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}
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#endif
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switch (mem){
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case 0x10002000: // IPU_CMD
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switch( mem )
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{
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case 0x00: // IPU_CMD
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//if(!ipuRegs->cmd.BUSY){
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if( ipuRegs->cmd.DATA&0xffffff )
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@ -284,6 +289,14 @@ __forceinline u64 ipuRead64(u32 mem)
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//return *(u64*)&ipuRegs->cmd;
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break;
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case 0x10:
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DevCon::Notice("reading 64bit IPU ctrl");
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break;
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case 0x20:
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DevCon::Notice("reading 64bit IPU top");
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break;
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case 0x10002030: // IPU_TOP
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IPU_LOG("Ipu read64: IPU_TOP=%x, bp = %d\n",ipuRegs->top,g_BP.BP);
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@ -293,9 +306,8 @@ __forceinline u64 ipuRead64(u32 mem)
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default:
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IPU_LOG("Ipu read64: Unknown=%x\n", mem);
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break;
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}
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return *(u64*)(((u8*)ipuRegs)+(mem&0xff));
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return *(u64*)(((u8*)ipuRegs)+mem);
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}
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void ipuSoftReset()
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@ -332,8 +344,13 @@ void ipuSoftReset()
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g_nCmdPos[0] = 0; g_nCmdPos[1] = 0;
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}
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__forceinline void ipuWrite32(u32 mem,u32 value)
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__forceinline void ipuWrite32(u32 mem, u32 value)
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{
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// Note: It's assumed that mem's input value is always in the 0x10002000 page
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// of memory (if not, it's probably bad code).
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jASSUME( ( mem & ~0xfff ) == 0x10002000 );
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IPUProcessInterrupt();
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switch (mem){
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@ -356,13 +373,18 @@ __forceinline void ipuWrite32(u32 mem,u32 value)
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break;
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default:
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IPU_LOG("Ipu write32: Unknown=%x\n", mem);
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*(u32*)((u8*)ipuRegs + (mem&0xfff)) = value;
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*(u32*)((u8*)ipuRegs + mem) = value;
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break;
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}
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}
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__forceinline void ipuWrite64(u32 mem, u64 value)
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{
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// Note: It's assumed that mem's input value is always in the 0x10002000 page
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// of memory (if not, it's probably bad code).
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jASSUME( ( mem & ~0xfff ) == 0x10002000 );
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IPUProcessInterrupt();
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switch (mem){
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@ -373,7 +395,7 @@ __forceinline void ipuWrite64(u32 mem, u64 value)
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default:
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IPU_LOG("Ipu write64: Unknown=%x\n", mem);
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*(u64*)((u8*)ipuRegs + (mem&0xfff)) = value;
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*(u64*)((u8*)ipuRegs + mem) = value;
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break;
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}
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}
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@ -315,8 +315,11 @@ void LWU() {
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}
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}
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u32 LWL_MASK[4] = { 0xffffff, 0xffff, 0xff, 0 };
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u32 LWL_SHIFT[4] = { 24, 16, 8, 0 };
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static const s32 LWL_MASK[4] = { 0xffffff, 0x0000ffff, 0x000000ff, 0x00000000 };
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static const s32 LWR_MASK[4] = { 0x000000, 0xff000000, 0xffff0000, 0xffffff00 };
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static const u8 LWL_SHIFT[4] = { 24, 16, 8, 0 };
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static const u8 LWR_SHIFT[4] = { 0, 8, 16, 24 };
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void LWL() {
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s32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
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@ -325,11 +328,14 @@ void LWL() {
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if (!_Rt_) return;
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memRead32(addr & ~3, &mem);
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cpuRegs.GPR.r[_Rt_].UD[0] = (cpuRegs.GPR.r[_Rt_].UL[0] & LWL_MASK[shift]) |
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// Reassignment note: ensure the compiler does sign extension into 64 bits, by using (s32).
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cpuRegs.GPR.r[_Rt_].UD[0] = (s32)(cpuRegs.GPR.r[_Rt_].SL[0] & LWL_MASK[shift]) |
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(mem << LWL_SHIFT[shift]);
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/*
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Mem = 1234. Reg = abcd
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(result is always sign extended into the upper 32 bits of the Rt)
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0 4bcd (mem << 24) | (reg & 0x00ffffff)
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1 34cd (mem << 16) | (reg & 0x0000ffff)
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@ -338,23 +344,35 @@ void LWL() {
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*/
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}
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u32 LWR_MASK[4] = { 0, 0xff000000, 0xffff0000, 0xffffff00 };
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u32 LWR_SHIFT[4] = { 0, 8, 16, 24 };
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void LWR() {
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s32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
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u32 shift = addr & 3;
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u32 mem;
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if (!_Rt_) return;
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memRead32(addr & ~3, &mem);
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cpuRegs.GPR.r[_Rt_].UD[0] = (cpuRegs.GPR.r[_Rt_].UL[0] & LWR_MASK[shift]) |
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(mem >> LWR_SHIFT[shift]);
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u32 mem;
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memRead32(addr & ~3, &mem);
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mem = (cpuRegs.GPR.r[_Rt_].SL[0] & LWR_MASK[shift]) |
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(mem >> LWR_SHIFT[shift]);
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if( shift == 0 )
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{
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// This special case requires sign extension into the full 64 bit dest.
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cpuRegs.GPR.r[_Rt_].SD[0] = (s32)mem;
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}
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else
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{
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// This case can simply set the lower 32 bits of the target register. Upper
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// 32 bits are always preserved.
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cpuRegs.GPR.r[_Rt_].UL[0] = mem;
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}
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/*
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Mem = 1234. Reg = abcd
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0 1234 (mem ) | (reg & 0x00000000)
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0 1234 (mem ) | (reg & 0x00000000) [sign extend into upper 32 bits!]
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1 a123 (mem >> 8) | (reg & 0xff000000)
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2 ab12 (mem >> 16) | (reg & 0xffff0000)
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3 abc1 (mem >> 24) | (reg & 0xffffff00)
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}
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}
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u64 LDL_MASK[8] = { 0x00ffffffffffffffLL, 0x0000ffffffffffffLL, 0x000000ffffffffffLL, 0x00000000ffffffffLL,
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0x0000000000ffffffLL, 0x000000000000ffffLL, 0x00000000000000ffLL, 0x0000000000000000LL };
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u32 LDL_SHIFT[8] = { 56, 48, 40, 32, 24, 16, 8, 0 };
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static const u64 LDL_MASK[8] =
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{ 0x00ffffffffffffffLL, 0x0000ffffffffffffLL, 0x000000ffffffffffLL, 0x00000000ffffffffLL,
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0x0000000000ffffffLL, 0x000000000000ffffLL, 0x00000000000000ffLL, 0x0000000000000000LL
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};
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static const u64 LDR_MASK[8] =
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{ 0x0000000000000000LL, 0xff00000000000000LL, 0xffff000000000000LL, 0xffffff0000000000LL,
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0xffffffff00000000LL, 0xffffffffff000000LL, 0xffffffffffff0000LL, 0xffffffffffffff00LL
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};
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static const u8 LDR_SHIFT[8] = { 0, 8, 16, 24, 32, 40, 48, 56 };
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static const u8 LDL_SHIFT[8] = { 56, 48, 40, 32, 24, 16, 8, 0 };
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void LDL() {
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u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
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(mem << LDL_SHIFT[shift]);
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}
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u64 LDR_MASK[8] = { 0x0000000000000000LL, 0xff00000000000000LL, 0xffff000000000000LL, 0xffffff0000000000LL,
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0xffffffff00000000LL, 0xffffffffff000000LL, 0xffffffffffff0000LL, 0xffffffffffffff00LL };
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u32 LDR_SHIFT[8] = { 0, 8, 16, 24, 32, 40, 48, 56 };
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void LDR() {
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u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
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u32 shift = addr & 7;
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@ -438,8 +461,11 @@ void SW(){
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memWrite32(addr, cpuRegs.GPR.r[_Rt_].UL[0]);
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}
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u32 SWL_MASK[4] = { 0xffffff00, 0xffff0000, 0xff000000, 0x00000000 };
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u32 SWL_SHIFT[4] = { 24, 16, 8, 0 };
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static const u32 SWL_MASK[4] = { 0xffffff00, 0xffff0000, 0xff000000, 0x00000000 };
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static const u32 SWR_MASK[4] = { 0x00000000, 0x000000ff, 0x0000ffff, 0x00ffffff };
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static const u8 SWR_SHIFT[4] = { 0, 8, 16, 24 };
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static const u8 SWL_SHIFT[4] = { 24, 16, 8, 0 };
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void SWL() {
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u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
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@ -448,8 +474,10 @@ void SWL() {
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memRead32(addr & ~3, &mem);
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memWrite32(addr & ~3, (cpuRegs.GPR.r[_Rt_].UL[0] >> SWL_SHIFT[shift]) |
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( mem & SWL_MASK[shift]) );
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memWrite32( addr & ~3,
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(cpuRegs.GPR.r[_Rt_].UL[0] >> SWL_SHIFT[shift]) |
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(mem & SWL_MASK[shift])
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);
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/*
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Mem = 1234. Reg = abcd
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@ -460,9 +488,6 @@ void SWL() {
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*/
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}
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u32 SWR_MASK[4] = { 0x00000000, 0x000000ff, 0x0000ffff, 0x00ffffff };
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u32 SWR_SHIFT[4] = { 0, 8, 16, 24 };
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void SWR() {
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u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
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u32 shift = addr & 3;
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@ -470,8 +495,10 @@ void SWR() {
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memRead32(addr & ~3, &mem);
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memWrite32(addr & ~3, (cpuRegs.GPR.r[_Rt_].UL[0] << SWR_SHIFT[shift]) |
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( mem & SWR_MASK[shift]) );
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memWrite32( addr & ~3,
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(cpuRegs.GPR.r[_Rt_].UL[0] << SWR_SHIFT[shift]) |
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(mem & SWR_MASK[shift])
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);
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/*
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Mem = 1234. Reg = abcd
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@ -490,9 +517,17 @@ void SD() {
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memWrite64(addr,&cpuRegs.GPR.r[_Rt_].UD[0]);
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}
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u64 SDL_MASK[8] = { 0xffffffffffffff00LL, 0xffffffffffff0000LL, 0xffffffffff000000LL, 0xffffffff00000000LL,
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0xffffff0000000000LL, 0xffff000000000000LL, 0xff00000000000000LL, 0x0000000000000000LL };
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u32 SDL_SHIFT[8] = { 56, 48, 40, 32, 24, 16, 8, 0 };
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static const u64 SDL_MASK[8] =
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{ 0xffffffffffffff00LL, 0xffffffffffff0000LL, 0xffffffffff000000LL, 0xffffffff00000000LL,
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0xffffff0000000000LL, 0xffff000000000000LL, 0xff00000000000000LL, 0x0000000000000000LL
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};
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static const u64 SDR_MASK[8] =
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{ 0x0000000000000000LL, 0x00000000000000ffLL, 0x000000000000ffffLL, 0x0000000000ffffffLL,
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0x00000000ffffffffLL, 0x000000ffffffffffLL, 0x0000ffffffffffffLL, 0x00ffffffffffffffLL
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};
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static const u8 SDL_SHIFT[8] = { 56, 48, 40, 32, 24, 16, 8, 0 };
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static const u8 SDR_SHIFT[8] = { 0, 8, 16, 24, 32, 40, 48, 56 };
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void SDL() {
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u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
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@ -500,14 +535,11 @@ void SDL() {
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u64 mem;
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memRead64(addr & ~7, &mem);
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mem =(cpuRegs.GPR.r[_Rt_].UD[0] >> SDL_SHIFT[shift]) |
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( mem & SDL_MASK[shift]);
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mem = (cpuRegs.GPR.r[_Rt_].UD[0] >> SDL_SHIFT[shift]) |
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(mem & SDL_MASK[shift]);
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memWrite64(addr & ~7, &mem);
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}
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u64 SDR_MASK[8] = { 0x0000000000000000LL, 0x00000000000000ffLL, 0x000000000000ffffLL, 0x0000000000ffffffLL,
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0x00000000ffffffffLL, 0x000000ffffffffffLL, 0x0000ffffffffffffLL, 0x00ffffffffffffffLL };
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u32 SDR_SHIFT[8] = { 0, 8, 16, 24, 32, 40, 48, 56 };
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void SDR() {
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u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
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@ -515,8 +547,8 @@ void SDR() {
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u64 mem;
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memRead64(addr & ~7, &mem);
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mem=(cpuRegs.GPR.r[_Rt_].UD[0] << SDR_SHIFT[shift]) |
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( mem & SDR_MASK[shift]);
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mem = (cpuRegs.GPR.r[_Rt_].UD[0] << SDR_SHIFT[shift]) |
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(mem & SDR_MASK[shift]);
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memWrite64(addr & ~7, &mem );
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}
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@ -1,10 +1,16 @@
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; DEV9null.def : Declares the module parameters for the DLL.
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; DEV9null.def : Declares the module parameters for the DLL.
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LIBRARY "DEV9null"
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DESCRIPTION 'DEV9null Driver'
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EXPORTS
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; Explicit exports can go here
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;DESCRIPTION 'DEV9null Driver'
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EXPORTS
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; Explicit exports can go here
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PS2EgetLibType @2
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PS2EgetLibName @3
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PS2EgetLibVersion2 @4
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Reference in New Issue