mirror of https://github.com/PCSX2/pcsx2.git
almost done with the vu div opcode :p
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@29 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
cottonvibes
Gregory Hainaut
parent
495db3a47c
commit
c3a6c3316d
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@ -1338,7 +1338,7 @@ void vuFloat3(uptr x86ptr)
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void CheckForOverflow(VURegs *VU, int info, int regd)
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{
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//testWhenOverflow(info, regd, EEREC_TEMP);
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testWhenOverflow(info, regd, EEREC_TEMP);
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//CheckForOverflow_(regd, EEREC_TEMP, _X_Y_Z_W);
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if (EEREC_TEMP != regd) {
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//testWhenOverflow(info, regd, EEREC_TEMP);
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@ -3610,21 +3610,18 @@ void recVUMI_ITOF0( VURegs *VU, int info )
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VU_MERGE_REGS(EEREC_T, EEREC_TEMP);
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xmmregs[EEREC_T].mode |= MODE_WRITE;
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if (CHECK_EXTRA_OVERFLOW)
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vuFloat2(EEREC_T, EEREC_TEMP, _X_Y_Z_W); // Clamp infinities
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vuFloat2(EEREC_T, EEREC_TEMP, _X_Y_Z_W); // Clamp infinities
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}
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else {
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if( cpucaps.hasStreamingSIMD2Extensions ) {
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SSE2_CVTDQ2PS_XMM_to_XMM(EEREC_T, EEREC_S);
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if (CHECK_EXTRA_OVERFLOW)
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vuFloat2(EEREC_T, EEREC_TEMP, 15); // Clamp infinities
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vuFloat2(EEREC_T, EEREC_TEMP, 15); // Clamp infinities
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}
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else {
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_deleteVFtoXMMreg(_Fs_, VU==&VU1, 1);
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SSE2EMU_CVTDQ2PS_M128_to_XMM(EEREC_T, VU_VFx_ADDR( _Fs_ ));
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xmmregs[EEREC_T].mode |= MODE_WRITE;
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if (CHECK_EXTRA_OVERFLOW)
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vuFloat2(EEREC_T, EEREC_TEMP, 15); // Clamp infinities
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vuFloat2(EEREC_T, EEREC_TEMP, 15); // Clamp infinities
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}
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}
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}
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@ -3643,8 +3640,7 @@ void recVUMI_ITOFX(VURegs *VU, int addr, int info)
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SSE_MULPS_M128_to_XMM(EEREC_TEMP, addr);
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VU_MERGE_REGS(EEREC_T, EEREC_TEMP);
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xmmregs[EEREC_T].mode |= MODE_WRITE;
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if (CHECK_EXTRA_OVERFLOW)
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vuFloat2(EEREC_T, EEREC_TEMP, _X_Y_Z_W); // Clamp infinities
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vuFloat2(EEREC_T, EEREC_TEMP, _X_Y_Z_W); // Clamp infinities
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} else {
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if(cpucaps.hasStreamingSIMD2Extensions) SSE2_CVTDQ2PS_XMM_to_XMM(EEREC_T, EEREC_S);
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else {
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@ -3654,8 +3650,7 @@ void recVUMI_ITOFX(VURegs *VU, int addr, int info)
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}
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SSE_MULPS_M128_to_XMM(EEREC_T, addr);
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if (CHECK_EXTRA_OVERFLOW)
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vuFloat2(EEREC_T, EEREC_TEMP, 15); // Clamp infinities
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vuFloat2(EEREC_T, EEREC_TEMP, 15); // Clamp infinities
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}
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}
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@ -3733,10 +3728,11 @@ void recVUMI_CLIP(VURegs *VU, int info)
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/* VU Lower instructions */
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/******************************/
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PCSX2_ALIGNED16(u64 DIV_TEMP_XMM[2];)
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PCSX2_ALIGNED16(u64 DIV_TEMP_XMM2[2];)
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void recVUMI_DIV(VURegs *VU, int info)
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{
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int t1reg;
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int t1reg, t2reg;
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u8* pjmp;
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if( _Fs_ == 0 ) {
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@ -3824,30 +3820,46 @@ void recVUMI_DIV(VURegs *VU, int info)
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SSE_DIVSS_M32_to_XMM(EEREC_TEMP, (uptr)&VU->VF[_Ft_].UL[_Ftf_]);
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}
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}
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else { // = 0 So result is -MAX/+MAX
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else { // = 0 So result is +/- 0, or +/- Fmax if (FT == 0)
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//SysPrintf("FS = 0, FT != 0\n");
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_unpackVFSS_xyzw(EEREC_TEMP, EEREC_T, _Ftf_); // EEREC_TEMP.x <- EEREC_T.ftf
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t1reg = (EEREC_TEMP == 0) ? (EEREC_TEMP + 1) : (EEREC_TEMP - 1);
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t2reg = (EEREC_TEMP <= 1) ? (EEREC_TEMP + 2) : (EEREC_TEMP - 2);
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SSE_MOVAPS_XMM_to_M128( (uptr)DIV_TEMP_XMM, t1reg ); // backup data in t1reg to a temp address
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SSE_MOVAPS_XMM_to_M128( (uptr)DIV_TEMP_XMM2, t2reg ); // backup data in t2reg to a temp address
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// FT can still be zero here! so we need to check if its zero and set the correct flag.
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SSE_XORPS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP); // Clear EEREC_TEMP
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SSE_XORPS_XMM_to_XMM(t1reg, t1reg); // Clear t1reg
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XOR32RtoR( EAX, EAX ); // Clear EAX
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SSE_CMPEQPS_XMM_to_XMM(EEREC_TEMP, EEREC_T); // Set all F's if each vector is zero
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SSE_CMPEQSS_XMM_to_XMM(t1reg, EEREC_TEMP); // Set all F's if each vector is zero
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SSE_MOVMSKPS_XMM_to_R32(EAX, EEREC_TEMP); // Move the sign bits of the previous calculation
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SSE_MOVMSKPS_XMM_to_R32(EAX, t1reg); // Move the sign bits of the previous calculation
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AND32ItoR( EAX, 0x0000000f & ( 1 << _Ftf_ ) ); // Grab "Is Zero" bits from the previous calculation
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AND32ItoR( EAX, 0x00000001 ); // Grab "Is Zero" bits from the previous calculation
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pjmp = JZ8(0); // Skip if none are
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OR32ItoR(EAX, 0x410); // Set invalid flag they are
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x86SetJ8(pjmp);
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OR32RtoM( VU_VI_ADDR(REG_STATUS_FLAG, 2), EAX );
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// Now that we've finished the 0/0 flag checking, we can just set Q to +/- Fmax
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_unpackVFSS_xyzw(EEREC_TEMP, EEREC_T, _Ftf_);
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SSE_MOVAPS_XMM_to_XMM(t2reg, t1reg);
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SSE_ANDPS_M128_to_XMM(EEREC_TEMP, (uptr)&VU_Signed_Zero_Mask[0]);
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SSE_ORPS_M128_to_XMM(EEREC_TEMP, (uptr)&g_maxvals[0]);
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), EEREC_TEMP);
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SSE_ANDPS_XMM_to_XMM(t1reg, EEREC_TEMP);
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SSE_ANDPS_M128_to_XMM(t1reg, (uptr)&VU_Signed_Zero_Mask[0]);
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SSE_ORPS_M128_to_XMM(t1reg, (uptr)&g_maxvals[0]); // If 0, then t1reg = +/- fmax
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SSE_ANDNPS_XMM_to_XMM(t2reg, EEREC_TEMP);
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SSE_ANDPS_M128_to_XMM(t2reg, (uptr)&VU_Signed_Zero_Mask[0]); // If != 0, then t2reg = +/- 0
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SSE_ORPS_XMM_to_XMM(t1reg, t2reg); // t1reg = 0 or fmax
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), t1reg);
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SSE_MOVAPS_M128_to_XMM( (uptr)DIV_TEMP_XMM, t1reg ); // restore t1reg data
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SSE_MOVAPS_M128_to_XMM( (uptr)DIV_TEMP_XMM2, t2reg ); // restore t2reg data
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return;
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}
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@ -3857,7 +3869,8 @@ void recVUMI_DIV(VURegs *VU, int info)
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if( _Ftf_ < 3 ) {
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//SysPrintf("FS != 0, FT == 0\n");
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OR32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0x820); //Zero divide (only when not 0/0)
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MOV32ItoM(VU_VI_ADDR(REG_Q, 0), 0x7f7fffff);
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AND32ItoM(VU_VI_ADDR(REG_Q, 0), 0x80000000);
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OR32ItoM(VU_VI_ADDR(REG_Q, 0), 0x7f7fffff);
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} else {
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//SysPrintf("FS != 0, FT == 1\n");
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@ -3896,8 +3909,8 @@ void recVUMI_DIV(VURegs *VU, int info)
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SSE_DIVSS_XMM_to_XMM(EEREC_TEMP, EEREC_T);
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}
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}
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if (CHECK_EXTRA_OVERFLOW)
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vuFloat2(EEREC_TEMP, EEREC_TEMP, 0x8);
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vuFloat2(EEREC_TEMP, EEREC_TEMP, 0x8);
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), EEREC_TEMP);
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}
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@ -3937,9 +3950,8 @@ void recVUMI_SQRT( VURegs *VU, int info )
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//SSE_ANDPS_M128_to_XMM(EEREC_TEMP, (u32)const_clip);
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SSE_SQRTSS_XMM_to_XMM(EEREC_TEMP, EEREC_TEMP);
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if (CHECK_EXTRA_OVERFLOW)
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vuFloat2(EEREC_TEMP, EEREC_TEMP, 0x8);
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vuFloat2(EEREC_TEMP, EEREC_TEMP, 0x8);
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), EEREC_TEMP);
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_freeX86reg(vftemp);
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@ -4052,9 +4064,8 @@ void recVUMI_RSQRT(VURegs *VU, int info)
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SSE_DIVSS_M32_to_XMM(EEREC_TEMP, VU_VI_ADDR(REG_Q, 0));
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}
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}
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if (CHECK_EXTRA_OVERFLOW)
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vuFloat2(EEREC_TEMP, EEREC_TEMP, 0x8);
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vuFloat2(EEREC_TEMP, EEREC_TEMP, 0x8);
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_Q, 0), EEREC_TEMP);
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_freeX86reg(vftemp);
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@ -5495,8 +5506,7 @@ void recVUMI_ESADD( VURegs *VU, int info)
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SSE_ADDSS_XMM_to_XMM(EEREC_D, EEREC_TEMP);
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}
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}
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if (CHECK_EXTRA_OVERFLOW)
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vuFloat2(EEREC_TEMP, EEREC_D, 0x8);
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_P, 0), EEREC_TEMP);
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@ -5534,8 +5544,7 @@ void recVUMI_ERSADD( VURegs *VU, int info )
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// don't use RCPSS (very bad precision)
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SSE_DIVSS_XMM_to_XMM(EEREC_TEMP, EEREC_D);
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if (CHECK_EXTRA_OVERFLOW)
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vuFloat2(EEREC_TEMP, EEREC_D, 0x8);
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vuFloat2(EEREC_TEMP, EEREC_D, 0x8);
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SSE_MOVSS_XMM_to_M32(VU_VI_ADDR(REG_P, 0), EEREC_TEMP);
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}
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