diff --git a/pcsx2/Gif.cpp b/pcsx2/Gif.cpp
index f8fb7ecbd1..804fe9ea72 100644
--- a/pcsx2/Gif.cpp
+++ b/pcsx2/Gif.cpp
@@ -166,7 +166,7 @@ __fi void gsInterrupt()
 	gifRegs.stat.clear_flags(GIF_STAT_FQC);
 	clearFIFOstuff(false);
 	hwDmacIrq(DMAC_GIF);
-	//DevCon.Warning("GIF DMA end");
+	DMA_LOG("GIF DMA End");
 }
 
 static u32 WRITERING_DMA(u32 *pMem, u32 qwc)
@@ -683,7 +683,7 @@ void gifMFIFOInterrupt()
 	gifch.chcr.STR = false;
 	gifstate = GIF_STATE_READY;
 	hwDmacIrq(DMAC_GIF);
-	GIF_LOG("gifMFIFO End");
+	DMA_LOG("GIF MFIFO DMA End");
 	clearFIFOstuff(false);
 }
 
diff --git a/pcsx2/IPU/IPUdma.cpp b/pcsx2/IPU/IPUdma.cpp
index 3060b771a6..9c1d0c2d77 100644
--- a/pcsx2/IPU/IPUdma.cpp
+++ b/pcsx2/IPU/IPUdma.cpp
@@ -152,7 +152,6 @@ int IPU1dma()
 	int totalqwc = 0;
 
 	//We need to make sure GIF has flushed before sending IPU data, it seems to REALLY screw FFX videos
-    //if(!WaitGSPaths()) return totalqwc;
 
 	if(ipu1dma.chcr.STR == false || IPU1Status.DMAMode == 2)
 	{
@@ -169,11 +168,6 @@ int IPU1dma()
 	{
 		case DMA_MODE_NORMAL:
 			{
-				if(!WaitGSPaths())
-				{ // legacy WaitGSPaths() for now
-					IPU_INT_TO(32); //Give it a short wait.
-					return totalqwc;
-				}
 				IPU_LOG("Processing Normal QWC left %x Finished %d In Progress %d", ipu1dma.qwc, IPU1Status.DMAFinished, IPU1Status.InProgress);
 				if(IPU1Status.InProgress == true) totalqwc += IPU1chain();
 			}
@@ -183,11 +177,6 @@ int IPU1dma()
 			{
 				if(IPU1Status.InProgress == true) //No transfer is ready to go so we need to set one up
 				{
-					if(!WaitGSPaths())
-					{ // legacy WaitGSPaths() for now
-						IPU_INT_TO(32); //Give it a short wait.
-						return totalqwc;
-					}
 					IPU_LOG("Processing Chain QWC left %x Finished %d In Progress %d", ipu1dma.qwc, IPU1Status.DMAFinished, IPU1Status.InProgress);
 					totalqwc += IPU1chain();
 					//Set the TADR forward
@@ -263,12 +252,6 @@ int IPU1dma()
 					if (ipu1dma.chcr.TIE && ptag->IRQ) //Tag Interrupt is set, so schedule the end/interrupt
 						IPU1Status.DMAFinished = true;
 
-
-					if(!WaitGSPaths() && ipu1dma.qwc > 0)
-					{ // legacy WaitGSPaths() for now
-						IPU_INT_TO(32); //Give it a short wait.
-						return totalqwc;
-					}
 					IPU_LOG("Processing Start Chain QWC left %x Finished %d In Progress %d", ipu1dma.qwc, IPU1Status.DMAFinished, IPU1Status.InProgress);
 					totalqwc += IPU1chain();
 					//Set the TADR forward
@@ -490,6 +473,7 @@ void ipu0Interrupt()
 
 	ipu0dma.chcr.STR = false;
 	hwDmacIrq(DMAC_FROM_IPU);
+	DMA_LOG("IPU0 DMA End");
 }
 
 IPU_FORCEINLINE void ipu1Interrupt()
@@ -502,7 +486,7 @@ IPU_FORCEINLINE void ipu1Interrupt()
 		return;
 	}
 
-	IPU_LOG("ipu1 finish %x:", cpuRegs.cycle);
+	DMA_LOG("IPU1 DMA End");
 	ipu1dma.chcr.STR = false;
 	IPU1Status.DMAMode = 2;
 	hwDmacIrq(DMAC_TO_IPU);
diff --git a/pcsx2/SPR.cpp b/pcsx2/SPR.cpp
index 7543fd5979..b2405d1b62 100644
--- a/pcsx2/SPR.cpp
+++ b/pcsx2/SPR.cpp
@@ -264,6 +264,7 @@ void SPRFROMinterrupt()
 
 	spr0ch.chcr.STR = false;
 	hwDmacIrq(DMAC_FROM_SPR);
+	DMA_LOG("SPR0 DMA End");
 }
 
 void dmaSPR0()   // fromSPR
@@ -317,7 +318,15 @@ int  _SPR1chain()
 
 __fi void SPR1chain()
 {
-	CPU_INT(DMAC_TO_SPR, _SPR1chain() * BIAS);
+	if(!CHECK_IPUWAITHACK) 
+	{
+		CPU_INT(DMAC_TO_SPR, _SPR1chain() * BIAS);
+	}
+	else 
+	{
+		 _SPR1chain();
+		CPU_INT(DMAC_TO_SPR, 8);
+	}
 }
 
 void _SPR1interleave()
@@ -444,7 +453,7 @@ void SPRTOinterrupt()
 		return;
 	}
 
-	SPR_LOG("SPR1 End");
+	DMA_LOG("SPR1 DMA End");
 	spr1ch.chcr.STR = false;
 	hwDmacIrq(DMAC_TO_SPR);
 }
diff --git a/pcsx2/Sif0.cpp b/pcsx2/Sif0.cpp
index 7bae2e53df..2b376545d0 100644
--- a/pcsx2/Sif0.cpp
+++ b/pcsx2/Sif0.cpp
@@ -288,7 +288,7 @@ static __fi void Sif0End()
 	psHu32(SBUS_F240) &= ~0x20;
 	psHu32(SBUS_F240) &= ~0x2000;
 
-	SIF_LOG("SIF0 DMA end...");
+	DMA_LOG("SIF0 DMA End");
 }
 
 // Transfer IOP to EE, putting data in the fifo as an intermediate step.
diff --git a/pcsx2/Sif1.cpp b/pcsx2/Sif1.cpp
index 03854ad3b3..b845869eaf 100644
--- a/pcsx2/Sif1.cpp
+++ b/pcsx2/Sif1.cpp
@@ -281,7 +281,7 @@ static __fi void Sif1End()
 	psHu32(SBUS_F240) &= ~0x40;
 	psHu32(SBUS_F240) &= ~0x4000;
 
-	SIF_LOG("SIF1 DMA end...");
+	DMA_LOG("SIF1 DMA End");
 }
 
 // Transfer EE to IOP, putting data in the fifo as an intermediate step.
diff --git a/pcsx2/Vif0_Dma.cpp b/pcsx2/Vif0_Dma.cpp
index 543a319a5a..43243dacdb 100644
--- a/pcsx2/Vif0_Dma.cpp
+++ b/pcsx2/Vif0_Dma.cpp
@@ -236,6 +236,7 @@ __fi void vif0Interrupt()
 	g_vifCycles = 0;
 	hwDmacIrq(DMAC_VIF0);
 	vif0Regs.stat.FQC = 0;
+	DMA_LOG("VIF0 DMA End");
 }
 
 void dmaVIF0()
diff --git a/pcsx2/Vif1_Dma.cpp b/pcsx2/Vif1_Dma.cpp
index 8bc9098902..7aa62fdaf8 100644
--- a/pcsx2/Vif1_Dma.cpp
+++ b/pcsx2/Vif1_Dma.cpp
@@ -457,7 +457,7 @@ __fi void vif1Interrupt()
 	vif1.vifstalled = false;
 	g_vifCycles = 0;
 	g_vu1Cycles = 0;
-	VIF_LOG("VIF1 End");
+	DMA_LOG("VIF1 DMA End");
 	hwDmacIrq(DMAC_VIF1);
 
 }
diff --git a/pcsx2/Vif1_MFIFO.cpp b/pcsx2/Vif1_MFIFO.cpp
index 6986d39e6c..0b532abb8b 100644
--- a/pcsx2/Vif1_MFIFO.cpp
+++ b/pcsx2/Vif1_MFIFO.cpp
@@ -356,7 +356,7 @@ void vifMFIFOInterrupt()
 	vif1Regs.stat.FQC = min((u16)0x10, vif1ch.qwc);
 	vif1ch.chcr.STR = false;
 	hwDmacIrq(DMAC_VIF1);
-	VIF_LOG("vif mfifo dma end");
+	DMA_LOG("VIF1 MFIFO DMA End");
 
 	vif1Regs.stat.FQC = 0;
 }