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EE: fix shift constant propagation in new SSE code 

It seems constant must be flushed before any call to _allocGPRtoXMMreg
This commit is contained in:
Gregory Hainaut 2016-02-06 16:46:59 +01:00
parent fd4bc63854
commit c2aa56ac38
1 changed files with 9 additions and 8 deletions
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17
pcsx2/x86/ix86-32/iR5900Shift.cpp
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@ -424,6 +424,12 @@ void recSetShiftV(int info, int* rsreg, int* rtreg, int* rdreg, int* rstemp)
void recSetConstShiftV(int info, int* rsreg, int* rdreg, int* rstemp) void recSetConstShiftV(int info, int* rsreg, int* rdreg, int* rstemp)
{ {
// Note: do it first.
// 1/ It doesn't work in SSE if you did it in the end (I suspect
// a conflict with _allocGPRtoXMMreg when rt==rd)
// 2/ CPU has minimum cycle delay between read/write
_flushConstReg(_Rt_);
#if NO_MMX #if NO_MMX
_addNeededGPRtoXMMreg(_Rd_); _addNeededGPRtoXMMreg(_Rd_);
*rdreg = _allocGPRtoXMMreg(-1, _Rd_, MODE_WRITE); *rdreg = _allocGPRtoXMMreg(-1, _Rd_, MODE_WRITE);
@ -433,9 +439,6 @@ void recSetConstShiftV(int info, int* rsreg, int* rdreg, int* rstemp)
xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]); xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]);
xAND(eax, 0x3f); xAND(eax, 0x3f);
xMOVDZX(xRegisterSSE(*rstemp), eax); xMOVDZX(xRegisterSSE(*rstemp), eax);
*rsreg = *rstemp;
_flushConstReg(_Rt_);
#else #else
_addNeededMMXreg(MMX_GPR+_Rd_); _addNeededMMXreg(MMX_GPR+_Rd_);
*rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE); *rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
@ -445,10 +448,8 @@ void recSetConstShiftV(int info, int* rsreg, int* rdreg, int* rstemp)
xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]); xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]);
xAND(eax, 0x3f); xAND(eax, 0x3f);
xMOVDZX(xRegisterMMX(*rstemp), eax); xMOVDZX(xRegisterMMX(*rstemp), eax);
*rsreg = *rstemp;
_flushConstReg(_Rt_);
#endif #endif
*rsreg = *rstemp;
} }
//// SLLV //// SLLV
@ -591,7 +592,7 @@ void recDSLLV_constt(int info)
// The others possibility could be a read back of the upper 64 bits // The others possibility could be a read back of the upper 64 bits
// (better use of register but code will likely be flushed after anyway) // (better use of register but code will likely be flushed after anyway)
xMOVL.PD(ptr64[&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ]] , xRegisterSSE(rdreg)); xMOVL.PD(ptr64[&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ]] , xRegisterSSE(rdreg));
_deleteGPRtoXMMreg(_Rt_, 3); //_deleteGPRtoXMMreg(_Rt_, 3);
_deleteGPRtoXMMreg(_Rd_, 3); _deleteGPRtoXMMreg(_Rd_, 3);
#else #else
@ -651,7 +652,7 @@ void recDSRLV_constt(int info)
// The others possibility could be a read back of the upper 64 bits // The others possibility could be a read back of the upper 64 bits
// (better use of register but code will likely be flushed after anyway) // (better use of register but code will likely be flushed after anyway)
xMOVL.PD(ptr64[&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ]] , xRegisterSSE(rdreg)); xMOVL.PD(ptr64[&cpuRegs.GPR.r[ _Rd_ ].UD[ 0 ]] , xRegisterSSE(rdreg));
_deleteGPRtoXMMreg(_Rt_, 3); //_deleteGPRtoXMMreg(_Rt_, 3);
_deleteGPRtoXMMreg(_Rd_, 3); _deleteGPRtoXMMreg(_Rd_, 3);
#else #else
xMOVQ(xRegisterMMX(rdreg), ptr[&cpuRegs.GPR.r[_Rt_]]); xMOVQ(xRegisterMMX(rdreg), ptr[&cpuRegs.GPR.r[_Rt_]]);