From c0e65d9a36268fef7baebf5805bb5a79d5e4c0e3 Mon Sep 17 00:00:00 2001
From: Connor McLaughlin <stenzek@gmail.com>
Date: Tue, 19 Apr 2022 00:06:35 +1000
Subject: [PATCH] vtlb: Add RAM accessors which avoid hw access

---
 pcsx2/vtlb.cpp | 37 +++++++++++++++++++++++++++++++++++++
 pcsx2/vtlb.h   |  8 ++++++++
 2 files changed, 45 insertions(+)

diff --git a/pcsx2/vtlb.cpp b/pcsx2/vtlb.cpp
index 30586c7c50..030f0b627c 100644
--- a/pcsx2/vtlb.cpp
+++ b/pcsx2/vtlb.cpp
@@ -315,6 +315,43 @@ template void vtlb_memWrite<mem8_t>(u32 mem, mem8_t data);
 template void vtlb_memWrite<mem16_t>(u32 mem, mem16_t data);
 template void vtlb_memWrite<mem32_t>(u32 mem, mem32_t data);
 
+template <typename DataType>
+bool vtlb_ramRead(u32 addr, DataType* value)
+{
+	const auto vmv = vtlbdata.vmap[addr >> VTLB_PAGE_BITS];
+	if (vmv.isHandler(addr))
+	{
+		std::memset(value, 0, sizeof(DataType));
+		return false;
+	}
+
+	std::memcpy(value, reinterpret_cast<DataType*>(vmv.assumePtr(addr)), sizeof(DataType));
+	return true;
+}
+
+template <typename DataType>
+bool vtlb_ramWrite(u32 addr, const DataType& data)
+{
+	const auto vmv = vtlbdata.vmap[addr >> VTLB_PAGE_BITS];
+	if (vmv.isHandler(addr))
+		return false;
+
+	std::memcpy(reinterpret_cast<DataType*>(vmv.assumePtr(addr)), &data, sizeof(DataType));
+	return true;
+}
+
+
+template bool vtlb_ramRead<mem8_t>(u32 mem, mem8_t* value);
+template bool vtlb_ramRead<mem16_t>(u32 mem, mem16_t* value);
+template bool vtlb_ramRead<mem32_t>(u32 mem, mem32_t* value);
+template bool vtlb_ramRead<mem64_t>(u32 mem, mem64_t* value);
+template bool vtlb_ramRead<mem128_t>(u32 mem, mem128_t* value);
+template bool vtlb_ramWrite<mem8_t>(u32 mem, const mem8_t& data);
+template bool vtlb_ramWrite<mem16_t>(u32 mem, const mem16_t& data);
+template bool vtlb_ramWrite<mem32_t>(u32 mem, const mem32_t& data);
+template bool vtlb_ramWrite<mem64_t>(u32 mem, const mem64_t& data);
+template bool vtlb_ramWrite<mem128_t>(u32 mem, const mem128_t& data);
+
 // --------------------------------------------------------------------------------------
 //  TLB Miss / BusError Handlers
 // --------------------------------------------------------------------------------------
diff --git a/pcsx2/vtlb.h b/pcsx2/vtlb.h
index baa6a3109b..1b4c72890b 100644
--- a/pcsx2/vtlb.h
+++ b/pcsx2/vtlb.h
@@ -96,6 +96,14 @@ extern void vtlb_memWrite(u32 mem, DataType value);
 extern void vtlb_memWrite64(u32 mem, const mem64_t* value);
 extern void vtlb_memWrite128(u32 mem, const mem128_t* value);
 
+// "Safe" variants of vtlb, designed for external tools.
+// These routines only access the various RAM, and will not call handlers
+// which has the potential to change hardware state.
+template <typename DataType>
+extern DataType vtlb_ramRead(u32 mem);
+template <typename DataType>
+extern bool vtlb_ramWrite(u32 mem, const DataType& value);
+
 extern void vtlb_DynGenWrite(u32 sz);
 extern void vtlb_DynGenRead32(u32 bits, bool sign);
 extern int  vtlb_DynGenRead64(u32 sz, int gpr);