mirror of https://github.com/PCSX2/pcsx2.git
This is still faster, please do some benches before recklessly reverting, k? :)
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@90 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
ramapcsx2
Gregory Hainaut
parent
bf2a2c132a
commit
bffda0b646
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@ -1132,20 +1132,174 @@ void testWhenOverflow(int info, int regd, int t0reg) {
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// Clamps infinities to max/min non-infinity number (uses a temp reg)
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void vuFloat2(int regd, int regTemp, int XYZW) {
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//if( CHECK_OVERFLOW ) {
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// if (XYZW == 8) {
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// SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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// SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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// }
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// else if (XYZW != 0xf) { // here we use a temp reg because not all xyzw are being modified
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// SSE_MOVAPS_XMM_to_XMM(regTemp, regd);
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// SSE_MINPS_M128_to_XMM(regTemp, (uptr)g_maxvals);
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// SSE_MAXPS_M128_to_XMM(regTemp, (uptr)g_minvals);
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// VU_MERGE_REGS_CUSTOM(regd, regTemp, XYZW);
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// }
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// else { // all xyzw are being modified, so no need to use temp reg
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// SSE_MINPS_M128_to_XMM(regd, (uptr)g_maxvals);
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// SSE_MAXPS_M128_to_XMM(regd, (uptr)g_minvals);
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// }
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//}
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// THIS IS STILL FASTER ><
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if( CHECK_OVERFLOW ) {
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if (XYZW == 8) {
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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}
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else if (XYZW != 0xf) { // here we use a temp reg because not all xyzw are being modified
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SSE_MOVAPS_XMM_to_XMM(regTemp, regd);
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SSE_MINPS_M128_to_XMM(regTemp, (uptr)g_maxvals);
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SSE_MAXPS_M128_to_XMM(regTemp, (uptr)g_minvals);
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VU_MERGE_REGS_CUSTOM(regd, regTemp, XYZW);
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}
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else { // all xyzw are being modified, so no need to use temp reg
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SSE_MINPS_M128_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXPS_M128_to_XMM(regd, (uptr)g_minvals);
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/*if ( (XYZW != 0) && (XYZW != 8) && (XYZW != 0xF) ) {
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int t1reg = _vuGetTempXMMreg2(info, regd);
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if (t1reg >= 0) {
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vuFloat2( regd, t1reg, XYZW );
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_freeXMMreg( t1reg );
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return;
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}
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}*/
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switch (XYZW) {
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case 0: // Don't do anything if no vectors are being modified.
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break;
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case 15: //1111 //15 and 14 happen most often
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SSE_MINPS_M128_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXPS_M128_to_XMM(regd, (uptr)g_minvals);
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break;
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case 14: //0111 //15 and 14 happen most often
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xe1);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xc6);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xc9);
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break;
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case 1: //1000
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0x27);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0x27);
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break;
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case 2: //0100
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xc6);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xc6);
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break;
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case 3://1100
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xc6);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0x27);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0x36);
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break;
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case 4: //0010
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xe1);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xe1);
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break;
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case 5://1010
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xe1);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0x27);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0x2d);
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break;
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case 6: //0110
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xe1);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xc6);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xc9);
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break;
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case 7: //1110
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xe1);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xc6);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0x27);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0x39);
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break;
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case 8: //0001
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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break;
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case 9: //1001
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0x27);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0x27);
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break;
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case 10: //0101
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xc6);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xc6);
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break;
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case 11: //1101
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xc6);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0x27);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0x36);
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break;
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case 12: //0011
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xe1);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xe1);
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break;
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case 13: //1011
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0xe1);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0x27);
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SSE_MINSS_M32_to_XMM(regd, (uptr)g_maxvals);
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SSE_MAXSS_M32_to_XMM(regd, (uptr)g_minvals);
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SSE_SHUFPS_XMM_to_XMM(regd, regd, 0x2d);
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break;
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}
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}
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}
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