ShuriZma
/
pcsx2
mirror of https://github.com/PCSX2/pcsx2.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Switched the emitter over to using Thread-Local storage (TLS), which removes all the templates and brings us back to a more traditional-looking, macro-free, and intellisense-friendly implementation. Plus it's a lot less prone to errors and will make debugging easier down the road. (next commit will rename the files back to .cpp and get them out of the header includes) 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@919 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine 2009-04-07 16:54:02 +00:00
parent 5f35577543
commit bf3d124e23
17 changed files with 2281 additions and 2331 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
pcsx2/PrecompiledHeader.h
View File

@ -155,24 +155,3 @@ static __forceinline u32 timeGetTime()
# define __releaseinline __forceinline # define __releaseinline __forceinline
#endif #endif
//////////////////////////////////////////////////////////////////////////////////////////
// Emitter Instance Identifiers. If you add a new emitter, do it here also.
// Note: Currently most of the instances map back to 0, since existing dynarec code all
// shares iCore and must therefore all share the same emitter instance.
// (note: these don't really belong here per-se, but it's an easy spot to use for now)
enum
{
EmitterId_R5900 = 0,
EmitterId_R3000a = EmitterId_R5900,
EmitterId_VU0micro = EmitterId_R5900,
EmitterId_VU1micro = EmitterId_R5900,
// Cotton's new microVU, which is iCore-free
EmitterId_microVU0,
EmitterId_microVU1,
// Air's eventual IopRec, which will also be iCore-free
EmitterId_R3000air,
EmitterId_Count // must always be last!
};

4
pcsx2/windows/VCprojects/pcsx2_2008.vcproj
View File

@ -2986,10 +2986,6 @@
RelativePath="..\..\x86\ix86\ix86_group1.inl" RelativePath="..\..\x86\ix86\ix86_group1.inl"
> >
</File> </File>
<File
RelativePath="..\..\x86\ix86\ix86_macros.h"
>
</File>
<File <File
RelativePath="..\..\x86\ix86\ix86_mmx.inl" RelativePath="..\..\x86\ix86\ix86_mmx.inl"
> >

6
pcsx2/x86/iMMI.cpp
View File

@ -1956,14 +1956,14 @@ CPU_SSE_XMMCACHE_END
// Both Macros are 16 bytes so we can use a shift instead of a Mul instruction // Both Macros are 16 bytes so we can use a shift instead of a Mul instruction
#define QFSRVhelper0() { \ #define QFSRVhelper0() { \
ajmp[0] = JMP32(0); \ ajmp[0] = JMP32(0); \
x86Ptr[0] += 11; \ x86Ptr += 11; \
} }
#define QFSRVhelper(shift1, shift2) { \ #define QFSRVhelper(shift1, shift2) { \
SSE2_PSRLDQ_I8_to_XMM(EEREC_D, shift1); \ SSE2_PSRLDQ_I8_to_XMM(EEREC_D, shift1); \
SSE2_PSLLDQ_I8_to_XMM(t0reg, shift2); \ SSE2_PSLLDQ_I8_to_XMM(t0reg, shift2); \
ajmp[shift1] = JMP32(0); \ ajmp[shift1] = JMP32(0); \
x86Ptr[0] += 1; \ x86Ptr += 1; \
} }
void recQFSRV() void recQFSRV()
@ -1983,7 +1983,7 @@ void recQFSRV()
MOV32MtoR(EAX, (uptr)&cpuRegs.sa); MOV32MtoR(EAX, (uptr)&cpuRegs.sa);
SHL32ItoR(EAX, 4); // Multiply SA bytes by 16 bytes (the amount of bytes in QFSRVhelper() macros) SHL32ItoR(EAX, 4); // Multiply SA bytes by 16 bytes (the amount of bytes in QFSRVhelper() macros)
AND32ItoR(EAX, 0xf0); // This can possibly be removed but keeping it incase theres garbage in SA (cottonvibes) AND32ItoR(EAX, 0xf0); // This can possibly be removed but keeping it incase theres garbage in SA (cottonvibes)
ADD32ItoR(EAX, (uptr)x86Ptr[0] + 7); // ADD32 = 5 bytes, JMPR = 2 bytes ADD32ItoR(EAX, (uptr)x86Ptr + 7); // ADD32 = 5 bytes, JMPR = 2 bytes
JMPR(EAX); // Jumps to a QFSRVhelper() case below (a total of 16 different cases) JMPR(EAX); // Jumps to a QFSRVhelper() case below (a total of 16 different cases)
// Case 0: // Case 0:

24
pcsx2/x86/iR3000A.cpp
View File

@ -171,7 +171,7 @@ static void iIopDumpBlock( int startpc, u8 * ptr )
#ifdef __LINUX__ #ifdef __LINUX__
// dump the asm // dump the asm
f = fopen( "mydump1", "wb" ); f = fopen( "mydump1", "wb" );
fwrite( ptr, 1, (uptr)x86Ptr[0] - (uptr)ptr, f ); fwrite( ptr, 1, (uptr)x86Ptr - (uptr)ptr, f );
fclose( f ); fclose( f );
sprintf( command, "objdump -D --target=binary --architecture=i386 -M intel mydump1 | cat %s - > tempdump", filename ); sprintf( command, "objdump -D --target=binary --architecture=i386 -M intel mydump1 | cat %s - > tempdump", filename );
system( command ); system( command );
@ -772,7 +772,7 @@ void psxSetBranchReg(u32 reg)
_psxFlushCall(FLUSH_EVERYTHING); _psxFlushCall(FLUSH_EVERYTHING);
iPsxBranchTest(0xffffffff, 1); iPsxBranchTest(0xffffffff, 1);
JMP32((uptr)iopDispatcherReg - ( (uptr)x86Ptr[0] + 5 )); JMP32((uptr)iopDispatcherReg - ( (uptr)x86Ptr + 5 ));
} }
void psxSetBranchImm( u32 imm ) void psxSetBranchImm( u32 imm )
@ -828,7 +828,7 @@ static void iPsxBranchTest(u32 newpc, u32 cpuBranch)
if( newpc != 0xffffffff ) if( newpc != 0xffffffff )
{ {
CMP32ItoM((uptr)&psxRegs.pc, newpc); CMP32ItoM((uptr)&psxRegs.pc, newpc);
JNE32((uptr)iopDispatcherReg - ( (uptr)x86Ptr[0] + 6 )); JNE32((uptr)iopDispatcherReg - ( (uptr)x86Ptr + 6 ));
} }
// Skip branch jump target here: // Skip branch jump target here:
@ -864,7 +864,7 @@ void rpsxSYSCALL()
ADD32ItoM((uptr)&psxRegs.cycle, psxScaleBlockCycles() ); ADD32ItoM((uptr)&psxRegs.cycle, psxScaleBlockCycles() );
SUB32ItoM((uptr)&psxCycleEE, psxScaleBlockCycles()*8 ); SUB32ItoM((uptr)&psxCycleEE, psxScaleBlockCycles()*8 );
JMP32((uptr)iopDispatcherReg - ( (uptr)x86Ptr[0] + 5 )); JMP32((uptr)iopDispatcherReg - ( (uptr)x86Ptr + 5 ));
// jump target for skipping blockCycle updates // jump target for skipping blockCycle updates
x86SetJ8(j8Ptr[0]); x86SetJ8(j8Ptr[0]);
@ -884,7 +884,7 @@ void rpsxBREAK()
j8Ptr[0] = JE8(0); j8Ptr[0] = JE8(0);
ADD32ItoM((uptr)&psxRegs.cycle, psxScaleBlockCycles() ); ADD32ItoM((uptr)&psxRegs.cycle, psxScaleBlockCycles() );
SUB32ItoM((uptr)&psxCycleEE, psxScaleBlockCycles()*8 ); SUB32ItoM((uptr)&psxCycleEE, psxScaleBlockCycles()*8 );
JMP32((uptr)iopDispatcherReg - ( (uptr)x86Ptr[0] + 5 )); JMP32((uptr)iopDispatcherReg - ( (uptr)x86Ptr + 5 ));
x86SetJ8(j8Ptr[0]); x86SetJ8(j8Ptr[0]);
//if (!psxbranch) psxbranch = 2; //if (!psxbranch) psxbranch = 2;
@ -1004,7 +1004,7 @@ void iopRecRecompile(u32 startpc)
x86SetPtr( recPtr ); x86SetPtr( recPtr );
x86Align(16); x86Align(16);
recPtr = x86Ptr[_EmitterId_]; recPtr = x86Ptr;
s_pCurBlock = PSX_GETBLOCK(startpc); s_pCurBlock = PSX_GETBLOCK(startpc);
@ -1025,7 +1025,7 @@ void iopRecRecompile(u32 startpc)
psxbranch = 0; psxbranch = 0;
s_pCurBlock->SetFnptr( (uptr)x86Ptr[0] ); s_pCurBlock->SetFnptr( (uptr)x86Ptr );
s_psxBlockCycles = 0; s_psxBlockCycles = 0;
// reset recomp state variables // reset recomp state variables
@ -1160,7 +1160,7 @@ StartRecomp:
iPsxBranchTest(0xffffffff, 1); iPsxBranchTest(0xffffffff, 1);
JMP32((uptr)iopDispatcherReg - ( (uptr)x86Ptr[0] + 5 )); JMP32((uptr)iopDispatcherReg - ( (uptr)x86Ptr + 5 ));
} }
else { else {
if( psxbranch ) assert( !willbranch3 ); if( psxbranch ) assert( !willbranch3 );
@ -1180,12 +1180,12 @@ StartRecomp:
} }
} }
assert( x86Ptr[0] < recMem+RECMEM_SIZE ); assert( x86Ptr < recMem+RECMEM_SIZE );
assert(x86Ptr[_EmitterId_] - recPtr < 0x10000); assert(x86Ptr - recPtr < 0x10000);
s_pCurBlockEx->x86size = x86Ptr[_EmitterId_] - recPtr; s_pCurBlockEx->x86size = x86Ptr - recPtr;
recPtr = x86Ptr[0]; recPtr = x86Ptr;
assert( (g_psxHasConstReg&g_psxFlushedConstReg) == g_psxHasConstReg ); assert( (g_psxHasConstReg&g_psxFlushedConstReg) == g_psxHasConstReg );

34
pcsx2/x86/iR3000Atables.cpp
View File

@ -1258,7 +1258,7 @@ void rpsxJALR()
static void* s_pbranchjmp; static void* s_pbranchjmp;
static u32 s_do32 = 0; static u32 s_do32 = 0;
#define JUMPVALID(pjmp) (( x86Ptr[0] - (u8*)pjmp ) <= 0x80) #define JUMPVALID(pjmp) (( x86Ptr - (u8*)pjmp ) <= 0x80)
void rpsxSetBranchEQ(int info, int process) void rpsxSetBranchEQ(int info, int process)
{ {
@ -1305,7 +1305,7 @@ void rpsxBEQ_process(int info, int process)
else else
{ {
_psxFlushAllUnused(); _psxFlushAllUnused();
u8* prevx86 = x86Ptr[0]; u8* prevx86 = x86Ptr;
s_do32 = 0; s_do32 = 0;
psxSaveBranchState(); psxSaveBranchState();
@ -1318,7 +1318,7 @@ void rpsxBEQ_process(int info, int process)
x86SetJ8A( (u8*)s_pbranchjmp ); x86SetJ8A( (u8*)s_pbranchjmp );
} }
else { else {
x86Ptr[0] = prevx86; x86SetPtr( prevx86 );
s_do32 = 1; s_do32 = 1;
psxpc -= 4; psxpc -= 4;
psxRegs.code = iopMemRead32( psxpc - 4 ); psxRegs.code = iopMemRead32( psxpc - 4 );
@ -1369,7 +1369,7 @@ void rpsxBNE_process(int info, int process)
} }
_psxFlushAllUnused(); _psxFlushAllUnused();
u8* prevx86 = x86Ptr[0]; u8* prevx86 = x86Ptr;
s_do32 = 0; s_do32 = 0;
rpsxSetBranchEQ(info, process); rpsxSetBranchEQ(info, process);
@ -1381,7 +1381,7 @@ void rpsxBNE_process(int info, int process)
x86SetJ8A( (u8*)s_pbranchjmp ); x86SetJ8A( (u8*)s_pbranchjmp );
} }
else { else {
x86Ptr[0] = prevx86; x86SetPtr( prevx86 );
s_do32 = 1; s_do32 = 1;
psxpc -= 4; psxpc -= 4;
psxRegs.code = iopMemRead32( psxpc - 4 ); psxRegs.code = iopMemRead32( psxpc - 4 );
@ -1423,7 +1423,7 @@ void rpsxBLTZ()
} }
CMP32ItoM((uptr)&psxRegs.GPR.r[_Rs_], 0); CMP32ItoM((uptr)&psxRegs.GPR.r[_Rs_], 0);
u8* prevx86 = x86Ptr[0]; u8* prevx86 = x86Ptr;
u8* pjmp = JL8(0); u8* pjmp = JL8(0);
psxSaveBranchState(); psxSaveBranchState();
@ -1435,7 +1435,7 @@ void rpsxBLTZ()
x86SetJ8A( pjmp ); x86SetJ8A( pjmp );
} }
else { else {
x86Ptr[0] = prevx86; x86SetPtr( prevx86 );
psxpc -= 4; psxpc -= 4;
psxRegs.code = iopMemRead32( psxpc - 4 ); psxRegs.code = iopMemRead32( psxpc - 4 );
psxLoadBranchState(); psxLoadBranchState();
@ -1470,7 +1470,7 @@ void rpsxBGEZ()
} }
CMP32ItoM((uptr)&psxRegs.GPR.r[_Rs_], 0); CMP32ItoM((uptr)&psxRegs.GPR.r[_Rs_], 0);
u8* prevx86 = x86Ptr[0]; u8* prevx86 = x86Ptr;
u8* pjmp = JGE8(0); u8* pjmp = JGE8(0);
psxSaveBranchState(); psxSaveBranchState();
@ -1482,7 +1482,7 @@ void rpsxBGEZ()
x86SetJ8A( pjmp ); x86SetJ8A( pjmp );
} }
else { else {
x86Ptr[0] = prevx86; x86SetPtr( prevx86 );
psxpc -= 4; psxpc -= 4;
psxRegs.code = iopMemRead32( psxpc - 4 ); psxRegs.code = iopMemRead32( psxpc - 4 );
psxLoadBranchState(); psxLoadBranchState();
@ -1524,7 +1524,7 @@ void rpsxBLTZAL()
} }
CMP32ItoM((uptr)&psxRegs.GPR.r[_Rs_], 0); CMP32ItoM((uptr)&psxRegs.GPR.r[_Rs_], 0);
u8* prevx86 = x86Ptr[0]; u8* prevx86 = x86Ptr;
u8* pjmp = JL8(0); u8* pjmp = JL8(0);
psxSaveBranchState(); psxSaveBranchState();
@ -1538,7 +1538,7 @@ void rpsxBLTZAL()
x86SetJ8A( pjmp ); x86SetJ8A( pjmp );
} }
else { else {
x86Ptr[0] = prevx86; x86SetPtr( prevx86 );
psxpc -= 4; psxpc -= 4;
psxRegs.code = iopMemRead32( psxpc - 4 ); psxRegs.code = iopMemRead32( psxpc - 4 );
psxLoadBranchState(); psxLoadBranchState();
@ -1577,7 +1577,7 @@ void rpsxBGEZAL()
} }
CMP32ItoM((uptr)&psxRegs.GPR.r[_Rs_], 0); CMP32ItoM((uptr)&psxRegs.GPR.r[_Rs_], 0);
u8* prevx86 = x86Ptr[0]; u8* prevx86 = x86Ptr;
u8* pjmp = JGE8(0); u8* pjmp = JGE8(0);
MOV32ItoM((uptr)&psxRegs.GPR.r[31], psxpc+4); MOV32ItoM((uptr)&psxRegs.GPR.r[31], psxpc+4);
@ -1591,7 +1591,7 @@ void rpsxBGEZAL()
x86SetJ8A( pjmp ); x86SetJ8A( pjmp );
} }
else { else {
x86Ptr[0] = prevx86; x86SetPtr( prevx86 );
psxpc -= 4; psxpc -= 4;
psxRegs.code = iopMemRead32( psxpc - 4 ); psxRegs.code = iopMemRead32( psxpc - 4 );
psxLoadBranchState(); psxLoadBranchState();
@ -1631,7 +1631,7 @@ void rpsxBLEZ()
_clearNeededX86regs(); _clearNeededX86regs();
CMP32ItoM((uptr)&psxRegs.GPR.r[_Rs_], 0); CMP32ItoM((uptr)&psxRegs.GPR.r[_Rs_], 0);
u8* prevx86 = x86Ptr[0]; u8* prevx86 = x86Ptr;
u8* pjmp = JLE8(0); u8* pjmp = JLE8(0);
psxSaveBranchState(); psxSaveBranchState();
@ -1642,7 +1642,7 @@ void rpsxBLEZ()
x86SetJ8A( pjmp ); x86SetJ8A( pjmp );
} }
else { else {
x86Ptr[0] = prevx86; x86SetPtr( prevx86 );
psxpc -= 4; psxpc -= 4;
psxRegs.code = iopMemRead32( psxpc - 4 ); psxRegs.code = iopMemRead32( psxpc - 4 );
psxLoadBranchState(); psxLoadBranchState();
@ -1679,7 +1679,7 @@ void rpsxBGTZ()
_clearNeededX86regs(); _clearNeededX86regs();
CMP32ItoM((uptr)&psxRegs.GPR.r[_Rs_], 0); CMP32ItoM((uptr)&psxRegs.GPR.r[_Rs_], 0);
u8* prevx86 = x86Ptr[0]; u8* prevx86 = x86Ptr;
u8* pjmp = JG8(0); u8* pjmp = JG8(0);
psxSaveBranchState(); psxSaveBranchState();
@ -1690,7 +1690,7 @@ void rpsxBGTZ()
x86SetJ8A( pjmp ); x86SetJ8A( pjmp );
} }
else { else {
x86Ptr[0] = prevx86; x86SetPtr( prevx86 );
psxpc -= 4; psxpc -= 4;
psxRegs.code = iopMemRead32( psxpc - 4 ); psxRegs.code = iopMemRead32( psxpc - 4 );
psxLoadBranchState(); psxLoadBranchState();

26
pcsx2/x86/iVUzerorec.cpp
View File

@ -833,7 +833,7 @@ static VuFunctionHeader* SuperVURecompileProgram(u32 startpc, int vuindex)
SuperVURecompile(); SuperVURecompile();
s_recVUPtr = x86Ptr[0]; s_recVUPtr = x86Ptr;
// set the function's range // set the function's range
VuFunctionHeader::RANGE r; VuFunctionHeader::RANGE r;
@ -1889,7 +1889,7 @@ void VuBaseBlock::AssignVFRegs()
if( i == XMMREGS ) return; // nothing changed if( i == XMMREGS ) return; // nothing changed
} }
u8* oldX86 = x86Ptr[0]; u8* oldX86 = x86Ptr;
FORIT(itinst, insts) { FORIT(itinst, insts) {
@ -2078,7 +2078,7 @@ void VuBaseBlock::AssignVFRegs()
} }
} }
assert( x86Ptr[0] == oldX86 ); assert( x86Ptr == oldX86 );
u32 analyzechildren = !(type&BLOCKTYPE_ANALYZED); u32 analyzechildren = !(type&BLOCKTYPE_ANALYZED);
type |= BLOCKTYPE_ANALYZED; type |= BLOCKTYPE_ANALYZED;
@ -2466,7 +2466,7 @@ static void SuperVURecompile()
AND32ItoM( (uptr)&VU->vifRegs->stat, ~0x4 ); AND32ItoM( (uptr)&VU->vifRegs->stat, ~0x4 );
MOV32ItoM((uptr)&VU->VI[REG_TPC], pchild->endpc); MOV32ItoM((uptr)&VU->VI[REG_TPC], pchild->endpc);
JMP32( (uptr)SuperVUEndProgram - ( (uptr)x86Ptr[0] + 5 )); JMP32( (uptr)SuperVUEndProgram - ( (uptr)x86Ptr + 5 ));
} }
// only other case is when there are two branches // only other case is when there are two branches
else assert( (*itblock)->insts.back().regs[0].pipe == VUPIPE_BRANCH ); else assert( (*itblock)->insts.back().regs[0].pipe == VUPIPE_BRANCH );
@ -2606,11 +2606,11 @@ void SuperVUTestVU0Condition(u32 incstack)
ADD32ItoR(ESP, incstack); ADD32ItoR(ESP, incstack);
//CALLFunc((u32)timeout); //CALLFunc((u32)timeout);
JMP32( (uptr)SuperVUEndProgram - ( (uptr)x86Ptr[0] + 5 )); JMP32( (uptr)SuperVUEndProgram - ( (uptr)x86Ptr + 5 ));
x86SetJ8(ptr); x86SetJ8(ptr);
} }
else JAE32( (uptr)SuperVUEndProgram - ( (uptr)x86Ptr[0] + 6 ) ); else JAE32( (uptr)SuperVUEndProgram - ( (uptr)x86Ptr + 6 ) );
} }
void VuBaseBlock::Recompile() void VuBaseBlock::Recompile()
@ -2618,7 +2618,7 @@ void VuBaseBlock::Recompile()
if( type & BLOCKTYPE_ANALYZED ) return; if( type & BLOCKTYPE_ANALYZED ) return;
x86Align(16); x86Align(16);
pcode = x86Ptr[0]; pcode = x86Ptr;
#ifdef _DEBUG #ifdef _DEBUG
MOV32ItoM((uptr)&s_vufnheader, s_pFnHeader->startpc); MOV32ItoM((uptr)&s_vufnheader, s_pFnHeader->startpc);
@ -2726,7 +2726,7 @@ void VuBaseBlock::Recompile()
AND32ItoM( (uptr)&VU0.VI[ REG_VPU_STAT ].UL, s_vu?~0x100:~0x001 ); // E flag AND32ItoM( (uptr)&VU0.VI[ REG_VPU_STAT ].UL, s_vu?~0x100:~0x001 ); // E flag
AND32ItoM( (uptr)&VU->vifRegs->stat, ~0x4 ); AND32ItoM( (uptr)&VU->vifRegs->stat, ~0x4 );
if( !branch ) MOV32ItoM((uptr)&VU->VI[REG_TPC], endpc); if( !branch ) MOV32ItoM((uptr)&VU->VI[REG_TPC], endpc);
JMP32( (uptr)SuperVUEndProgram - ( (uptr)x86Ptr[0] + 5 )); JMP32( (uptr)SuperVUEndProgram - ( (uptr)x86Ptr + 5 ));
} }
else { else {
@ -2868,7 +2868,7 @@ void VuBaseBlock::Recompile()
} }
} }
pendcode = x86Ptr[0]; pendcode = x86Ptr;
type |= BLOCKTYPE_ANALYZED; type |= BLOCKTYPE_ANALYZED;
LISTBLOCKS::iterator itchild; LISTBLOCKS::iterator itchild;
@ -3569,7 +3569,7 @@ void recVUMI_BranchHandle()
if( (s_pCurBlock->type & BLOCKTYPE_HASEOP) || s_vu == 0 || SUPERVU_CHECKCONDITION) if( (s_pCurBlock->type & BLOCKTYPE_HASEOP) || s_vu == 0 || SUPERVU_CHECKCONDITION)
MOV32ItoM(SuperVUGetVIAddr(REG_TPC, 0), bpc); MOV32ItoM(SuperVUGetVIAddr(REG_TPC, 0), bpc);
MOV32ItoR(s_JumpX86, 0); MOV32ItoR(s_JumpX86, 0);
s_pCurBlock->pChildJumps[curjump] = (u32*)x86Ptr[0]-1; s_pCurBlock->pChildJumps[curjump] = (u32*)x86Ptr-1;
if( !(s_pCurInst->type & INST_BRANCH_DELAY) ) { if( !(s_pCurInst->type & INST_BRANCH_DELAY) ) {
j8Ptr[1] = JMP8(0); j8Ptr[1] = JMP8(0);
@ -3578,7 +3578,7 @@ void recVUMI_BranchHandle()
if( (s_pCurBlock->type & BLOCKTYPE_HASEOP) || s_vu == 0 || SUPERVU_CHECKCONDITION ) if( (s_pCurBlock->type & BLOCKTYPE_HASEOP) || s_vu == 0 || SUPERVU_CHECKCONDITION )
MOV32ItoM(SuperVUGetVIAddr(REG_TPC, 0), pc+8); MOV32ItoM(SuperVUGetVIAddr(REG_TPC, 0), pc+8);
MOV32ItoR(s_JumpX86, 0); MOV32ItoR(s_JumpX86, 0);
s_pCurBlock->pChildJumps[curjump+1] = (u32*)x86Ptr[0]-1; s_pCurBlock->pChildJumps[curjump+1] = (u32*)x86Ptr-1;
x86SetJ8( j8Ptr[ 1 ] ); x86SetJ8( j8Ptr[ 1 ] );
} }
@ -3815,7 +3815,7 @@ void recVUMI_B( VURegs* vuu, s32 info )
if( s_pCurBlock->blocks.size() > 1 ) { if( s_pCurBlock->blocks.size() > 1 ) {
s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE); s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE);
MOV32ItoR(s_JumpX86, 0); MOV32ItoR(s_JumpX86, 0);
s_pCurBlock->pChildJumps[(s_pCurInst->type & INST_BRANCH_DELAY)?1:0] = (u32*)x86Ptr[0]-1; s_pCurBlock->pChildJumps[(s_pCurInst->type & INST_BRANCH_DELAY)?1:0] = (u32*)x86Ptr-1;
s_UnconditionalDelay = 1; s_UnconditionalDelay = 1;
} }
@ -3841,7 +3841,7 @@ void recVUMI_BAL( VURegs* vuu, s32 info )
if( s_pCurBlock->blocks.size() > 1 ) { if( s_pCurBlock->blocks.size() > 1 ) {
s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE); s_JumpX86 = _allocX86reg(-1, X86TYPE_VUJUMP, 0, MODE_WRITE);
MOV32ItoR(s_JumpX86, 0); MOV32ItoR(s_JumpX86, 0);
s_pCurBlock->pChildJumps[(s_pCurInst->type & INST_BRANCH_DELAY)?1:0] = (u32*)x86Ptr[0]-1; s_pCurBlock->pChildJumps[(s_pCurInst->type & INST_BRANCH_DELAY)?1:0] = (u32*)x86Ptr-1;
s_UnconditionalDelay = 1; s_UnconditionalDelay = 1;
} }

4
pcsx2/x86/ix86-32/iCore-32.cpp
View File

@ -161,7 +161,7 @@ void _flushConstRegs()
zero_cnt++; zero_cnt++;
} }
rewindPtr = x86Ptr[_EmitterId_]; rewindPtr = x86Ptr;
for (i = 1, j = 0; i < 32; j++ && ++i, j %= 2) { for (i = 1, j = 0; i < 32; j++ && ++i, j %= 2) {
if (!GPR_IS_CONST1(i) || g_cpuFlushedConstReg & (1<<i)) if (!GPR_IS_CONST1(i) || g_cpuFlushedConstReg & (1<<i))
@ -178,7 +178,7 @@ void _flushConstRegs()
} }
if (minusone_cnt == 1 && !zero_cnt) { // not worth it for one byte if (minusone_cnt == 1 && !zero_cnt) { // not worth it for one byte
x86Ptr[_EmitterId_] = rewindPtr; x86SetPtr( rewindPtr );
} else { } else {
done[0] |= done[2]; done[0] |= done[2];
done[1] |= done[3]; done[1] |= done[3];

22
pcsx2/x86/ix86-32/iR5900-32.cpp
View File

@ -132,7 +132,7 @@ static void iDumpBlock( int startpc, u8 * ptr )
fflush( stdout ); fflush( stdout );
// f = fopen( "dump1", "wb" ); // f = fopen( "dump1", "wb" );
// fwrite( ptr, 1, (u32)x86Ptr[0] - (u32)ptr, f ); // fwrite( ptr, 1, (u32)x86Ptr - (u32)ptr, f );
// fclose( f ); // fclose( f );
// //
// sprintf( command, "objdump -D --target=binary --architecture=i386 dump1 > %s", filename ); // sprintf( command, "objdump -D --target=binary --architecture=i386 dump1 > %s", filename );
@ -579,8 +579,8 @@ void recResetEE( void )
// so a fix will have to wait until later. -_- (air) // so a fix will have to wait until later. -_- (air)
//x86SetPtr(recMem+REC_CACHEMEM); //x86SetPtr(recMem+REC_CACHEMEM);
//dyna_block_discard_recmem=(u8*)x86Ptr[0]; //dyna_block_discard_recmem=(u8*)x86Ptr;
//JMP32( (uptr)&dyna_block_discard - ( (u32)x86Ptr[0] + 5 )); //JMP32( (uptr)&dyna_block_discard - ( (u32)x86Ptr + 5 ));
x86SetPtr(recMem); x86SetPtr(recMem);
@ -791,7 +791,7 @@ void recSYSCALL( void ) {
CMP32ItoM((uptr)&cpuRegs.pc, pc); CMP32ItoM((uptr)&cpuRegs.pc, pc);
j8Ptr[0] = JE8(0); j8Ptr[0] = JE8(0);
ADD32ItoM((uptr)&cpuRegs.cycle, eeScaleBlockCycles()); ADD32ItoM((uptr)&cpuRegs.cycle, eeScaleBlockCycles());
JMP32((uptr)DispatcherReg - ( (uptr)x86Ptr[0] + 5 )); JMP32((uptr)DispatcherReg - ( (uptr)x86Ptr + 5 ));
x86SetJ8(j8Ptr[0]); x86SetJ8(j8Ptr[0]);
//branch = 2; //branch = 2;
} }
@ -1148,7 +1148,7 @@ static void iBranchTest(u32 newpc, bool noDispatch)
if (!noDispatch) { if (!noDispatch) {
if (newpc == 0xffffffff) if (newpc == 0xffffffff)
JS32((uptr)DispatcherReg - ( (uptr)x86Ptr[0] + 6 )); JS32((uptr)DispatcherReg - ( (uptr)x86Ptr + 6 ));
else else
iBranch(newpc, 1); iBranch(newpc, 1);
} }
@ -1375,7 +1375,7 @@ void recRecompile( const u32 startpc )
x86SetPtr( recPtr ); x86SetPtr( recPtr );
x86Align(16); x86Align(16);
recPtr = x86Ptr[_EmitterId_]; recPtr = x86Ptr;
s_pCurBlock = PC_GETBLOCK(startpc); s_pCurBlock = PC_GETBLOCK(startpc);
@ -1714,7 +1714,7 @@ StartRecomp:
{ {
// was dyna_block_discard_recmem. See note in recResetEE for details. // was dyna_block_discard_recmem. See note in recResetEE for details.
CMP32ItoM((uptr)PSM(lpc),*(u32*)PSM(lpc)); CMP32ItoM((uptr)PSM(lpc),*(u32*)PSM(lpc));
JNE32(((u32)&dyna_block_discard)- ( (u32)x86Ptr[0] + 6 )); JNE32(((u32)&dyna_block_discard)- ( (u32)x86Ptr + 6 ));
stg-=4; stg-=4;
lpc+=4; lpc+=4;
@ -1800,14 +1800,14 @@ StartRecomp:
} }
} }
assert( x86Ptr[0] < recMem+REC_CACHEMEM ); assert( x86Ptr < recMem+REC_CACHEMEM );
assert( recStackPtr < recStack+RECSTACK_SIZE ); assert( recStackPtr < recStack+RECSTACK_SIZE );
assert( x86FpuState == 0 ); assert( x86FpuState == 0 );
assert(x86Ptr[_EmitterId_] - recPtr < 0x10000); assert(x86Ptr - recPtr < 0x10000);
s_pCurBlockEx->x86size = x86Ptr[_EmitterId_] - recPtr; s_pCurBlockEx->x86size = x86Ptr - recPtr;
recPtr = x86Ptr[0]; recPtr = x86Ptr;
assert( (g_cpuHasConstReg&g_cpuFlushedConstReg) == g_cpuHasConstReg ); assert( (g_cpuHasConstReg&g_cpuFlushedConstReg) == g_cpuHasConstReg );

8
pcsx2/x86/ix86-32/iR5900LoadStore.cpp
View File

@ -1930,7 +1930,7 @@ void recLQC2( void )
dohw = recSetMemLocation(_Rs_, _Imm_, mmregs, 2, 0); dohw = recSetMemLocation(_Rs_, _Imm_, mmregs, 2, 0);
if( _Ft_ ) { if( _Ft_ ) {
u8* rawreadptr = x86Ptr[0]; u8* rawreadptr = x86Ptr;
if( mmreg >= 0 ) { if( mmreg >= 0 ) {
SSEX_MOVDQARmtoROffset(mmreg, ECX, PS2MEM_BASE_+s_nAddMemOffset); SSEX_MOVDQARmtoROffset(mmreg, ECX, PS2MEM_BASE_+s_nAddMemOffset);
@ -1945,7 +1945,7 @@ void recLQC2( void )
// check if writing to VUs // check if writing to VUs
CMP32ItoR(ECX, 0x11000000); CMP32ItoR(ECX, 0x11000000);
JAE8(rawreadptr - (x86Ptr[0]+2)); JAE8(rawreadptr - (x86Ptr+2));
PUSH32I( (int)&VU0.VF[_Ft_].UD[0] ); PUSH32I( (int)&VU0.VF[_Ft_].UD[0] );
CALLFunc( (int)recMemRead128 ); CALLFunc( (int)recMemRead128 );
@ -1999,7 +1999,7 @@ void recSQC2( void )
mmregs = _eePrepareReg(_Rs_); mmregs = _eePrepareReg(_Rs_);
dohw = recSetMemLocation(_Rs_, _Imm_, mmregs, 2, 0); dohw = recSetMemLocation(_Rs_, _Imm_, mmregs, 2, 0);
rawreadptr = x86Ptr[0]; rawreadptr = x86Ptr;
if( (mmreg = _checkXMMreg(XMMTYPE_VFREG, _Ft_, MODE_READ)) >= 0) { if( (mmreg = _checkXMMreg(XMMTYPE_VFREG, _Ft_, MODE_READ)) >= 0) {
SSEX_MOVDQARtoRmOffset(ECX, mmreg, PS2MEM_BASE_+s_nAddMemOffset); SSEX_MOVDQARtoRmOffset(ECX, mmreg, PS2MEM_BASE_+s_nAddMemOffset);
@ -2039,7 +2039,7 @@ void recSQC2( void )
// check if writing to VUs // check if writing to VUs
CMP32ItoR(ECX, 0x11000000); CMP32ItoR(ECX, 0x11000000);
JAE8(rawreadptr - (x86Ptr[0]+2)); JAE8(rawreadptr - (x86Ptr+2));
// some type of hardware write // some type of hardware write
if( (mmreg = _checkXMMreg(XMMTYPE_VFREG, _Ft_, MODE_READ)) >= 0) { if( (mmreg = _checkXMMreg(XMMTYPE_VFREG, _Ft_, MODE_READ)) >= 0) {

7
pcsx2/x86/ix86/ix86.cpp
View File

@ -29,10 +29,9 @@
#include "System.h" #include "System.h"
#include "ix86.h" #include "ix86.h"
u8 *x86Ptr[EmitterId_Count]; __threadlocal u8 *x86Ptr;
__threadlocal u8 *j8Ptr[32];
u8 *j8Ptr[32]; __threadlocal u32 *j32Ptr[32];
u32 *j32Ptr[32];
PCSX2_ALIGNED16(u32 p[4]); PCSX2_ALIGNED16(u32 p[4]);
PCSX2_ALIGNED16(u32 p2[4]); PCSX2_ALIGNED16(u32 p2[4]);

73
pcsx2/x86/ix86/ix86.h
View File

@ -32,7 +32,7 @@
//------------------------------------------------------------------ //------------------------------------------------------------------
// Helper Macros // Helper Macros
//------------------------------------------------------------------ //------------------------------------------------------------------
#define emitterT template<int I/*Emitter Index*/> #define emitterT static __forceinline
#define MEMADDR(addr, oplen) (addr) #define MEMADDR(addr, oplen) (addr)
@ -46,57 +46,62 @@
// This helps catch programmer errors better than using an auto-truncated s8 parameter. // This helps catch programmer errors better than using an auto-truncated s8 parameter.
#define assertOffset8(ofs) assert( ofs < 128 && ofs >= -128 ) #define assertOffset8(ofs) assert( ofs < 128 && ofs >= -128 )
#ifdef _MSC_VER
#define __threadlocal __declspec(thread)
#else
#define __threadlocal __thread
#endif
//------------------------------------------------------------------ //------------------------------------------------------------------
// write functions // write functions
//------------------------------------------------------------------ //------------------------------------------------------------------
extern u8 *x86Ptr[EmitterId_Count]; extern __threadlocal u8 *x86Ptr;
extern u8 *j8Ptr[32]; extern __threadlocal u8 *j8Ptr[32];
extern u32 *j32Ptr[32]; extern __threadlocal u32 *j32Ptr[32];
emitterT void write8( u8 val ) emitterT void write8( u8 val )
{ {
*x86Ptr[I] = (u8)val; *x86Ptr = (u8)val;
x86Ptr[I]++; x86Ptr++;
} }
emitterT void write16( u16 val ) emitterT void write16( u16 val )
{ {
*(u16*)x86Ptr[I] = val; *(u16*)x86Ptr = val;
x86Ptr[I] += 2; x86Ptr += 2;
} }
emitterT void write24( u32 val ) emitterT void write24( u32 val )
{ {
*x86Ptr[I]++ = (u8)(val & 0xff); *x86Ptr++ = (u8)(val & 0xff);
*x86Ptr[I]++ = (u8)((val >> 8) & 0xff); *x86Ptr++ = (u8)((val >> 8) & 0xff);
*x86Ptr[I]++ = (u8)((val >> 16) & 0xff); *x86Ptr++ = (u8)((val >> 16) & 0xff);
} }
emitterT void write32( u32 val ) emitterT void write32( u32 val )
{ {
*(u32*)x86Ptr[I] = val; *(u32*)x86Ptr = val;
x86Ptr[I] += 4; x86Ptr += 4;
} }
emitterT void write64( u64 val ){ emitterT void write64( u64 val ){
*(u64*)x86Ptr[I] = val; *(u64*)x86Ptr = val;
x86Ptr[I] += 8; x86Ptr += 8;
} }
//------------------------------------------------------------------ //------------------------------------------------------------------
//------------------------------------------------------------------ //------------------------------------------------------------------
// jump/align functions // jump/align functions
//------------------------------------------------------------------ //------------------------------------------------------------------
emitterT void ex86SetPtr( u8 *ptr ); emitterT void x86SetPtr( u8 *ptr );
emitterT void ex86SetJ8( u8 *j8 ); emitterT void x86SetJ8( u8 *j8 );
emitterT void ex86SetJ8A( u8 *j8 ); emitterT void x86SetJ8A( u8 *j8 );
emitterT void ex86SetJ16( u16 *j16 ); emitterT void x86SetJ16( u16 *j16 );
emitterT void ex86SetJ16A( u16 *j16 ); emitterT void x86SetJ16A( u16 *j16 );
emitterT void ex86SetJ32( u32 *j32 ); emitterT void x86SetJ32( u32 *j32 );
emitterT void ex86SetJ32A( u32 *j32 ); emitterT void x86SetJ32A( u32 *j32 );
emitterT void ex86Align( int bytes ); emitterT void x86Align( int bytes );
emitterT void ex86AlignExecutable( int align ); emitterT void x86AlignExecutable( int align );
//------------------------------------------------------------------ //------------------------------------------------------------------
//------------------------------------------------------------------ //------------------------------------------------------------------
@ -113,23 +118,21 @@ emitterT u32* J32Rel( int cc, u32 to );
emitterT u64 GetCPUTick( void ); emitterT u64 GetCPUTick( void );
//------------------------------------------------------------------ //------------------------------------------------------------------
emitterT void eMOV32RtoR( x86IntRegType to, x86IntRegType from ); emitterT void MOV32RtoR( x86IntRegType to, x86IntRegType from );
emitterT u32* eJMP32( uptr to ); emitterT u32* JMP32( uptr to );
emitterT u8* eJMP8( u8 to ); emitterT u8* JMP8( u8 to );
emitterT void eCALL32( u32 to ); emitterT void CALL32( u32 to );
emitterT void eLEA32RtoR(x86IntRegType to, x86IntRegType from, u32 offset); emitterT void LEA32RStoR(x86IntRegType to, x86IntRegType from, u32 scale);
emitterT void eLEA32RStoR(x86IntRegType to, x86IntRegType from, u32 scale); emitterT void NOP( void );
emitterT void eNOP( void ); emitterT void AND32ItoM( uptr to, u32 from );
emitterT void eAND32ItoM( uptr to, u32 from ); emitterT void LEA32RRtoR(x86IntRegType to, x86IntRegType from0, x86IntRegType from1);
emitterT void eLEA32RRtoR(x86IntRegType to, x86IntRegType from0, x86IntRegType from1); emitterT void LEA32RStoR(x86IntRegType to, x86IntRegType from, u32 scale);
emitterT void eLEA32RStoR(x86IntRegType to, x86IntRegType from, u32 scale);
#define MMXONLY(code) code #define MMXONLY(code) code
#define _MM_MK_INSERTPS_NDX(srcField, dstField, zeroMask) (((srcField)<<6) | ((dstField)<<4) | (zeroMask)) #define _MM_MK_INSERTPS_NDX(srcField, dstField, zeroMask) (((srcField)<<6) | ((dstField)<<4) | (zeroMask))
#include "ix86_macros.h"
#include "ix86.inl" #include "ix86.inl"
#include "ix86_3dnow.inl" #include "ix86_3dnow.inl"
#include "ix86_fpu.inl" #include "ix86_fpu.inl"

1924
pcsx2/x86/ix86/ix86.inl
View File

File diff suppressed because it is too large Load Diff

210
pcsx2/x86/ix86/ix86_3dnow.inl
View File

@ -23,179 +23,179 @@
//------------------------------------------------------------------ //------------------------------------------------------------------
/* femms */ /* femms */
emitterT void eFEMMS( void ) emitterT void FEMMS( void )
{ {
write16<I>( 0x0E0F ); write16( 0x0E0F );
} }
emitterT void ePFCMPEQMtoR( x86IntRegType to, uptr from ) emitterT void PFCMPEQMtoR( x86IntRegType to, uptr from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( from ); write32( from );
write8<I>( 0xB0 ); write8( 0xB0 );
} }
emitterT void ePFCMPGTMtoR( x86IntRegType to, uptr from ) emitterT void PFCMPGTMtoR( x86IntRegType to, uptr from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( from ); write32( from );
write8<I>( 0xA0 ); write8( 0xA0 );
} }
emitterT void ePFCMPGEMtoR( x86IntRegType to, uptr from ) emitterT void PFCMPGEMtoR( x86IntRegType to, uptr from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( from ); write32( from );
write8<I>( 0x90 ); write8( 0x90 );
} }
emitterT void ePFADDMtoR( x86IntRegType to, uptr from ) emitterT void PFADDMtoR( x86IntRegType to, uptr from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( from ); write32( from );
write8<I>( 0x9E ); write8( 0x9E );
} }
emitterT void ePFADDRtoR( x86IntRegType to, x86IntRegType from ) emitterT void PFADDRtoR( x86IntRegType to, x86IntRegType from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
write8<I>( 0x9E ); write8( 0x9E );
} }
emitterT void ePFSUBMtoR( x86IntRegType to, uptr from ) emitterT void PFSUBMtoR( x86IntRegType to, uptr from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( from ); write32( from );
write8<I>( 0x9A ); write8( 0x9A );
} }
emitterT void ePFSUBRtoR( x86IntRegType to, x86IntRegType from ) emitterT void PFSUBRtoR( x86IntRegType to, x86IntRegType from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
write8<I>( 0x9A ); write8( 0x9A );
} }
emitterT void ePFMULMtoR( x86IntRegType to, uptr from ) emitterT void PFMULMtoR( x86IntRegType to, uptr from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( from ); write32( from );
write8<I>( 0xB4 ); write8( 0xB4 );
} }
emitterT void ePFMULRtoR( x86IntRegType to, x86IntRegType from ) emitterT void PFMULRtoR( x86IntRegType to, x86IntRegType from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
write8<I>( 0xB4 ); write8( 0xB4 );
} }
emitterT void ePFRCPMtoR( x86IntRegType to, uptr from ) emitterT void PFRCPMtoR( x86IntRegType to, uptr from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( from ); write32( from );
write8<I>( 0x96 ); write8( 0x96 );
} }
emitterT void ePFRCPRtoR( x86IntRegType to, x86IntRegType from ) emitterT void PFRCPRtoR( x86IntRegType to, x86IntRegType from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
write8<I>( 0x96 ); write8( 0x96 );
} }
emitterT void ePFRCPIT1RtoR( x86IntRegType to, x86IntRegType from ) emitterT void PFRCPIT1RtoR( x86IntRegType to, x86IntRegType from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
write8<I>( 0xA6 ); write8( 0xA6 );
} }
emitterT void ePFRCPIT2RtoR( x86IntRegType to, x86IntRegType from ) emitterT void PFRCPIT2RtoR( x86IntRegType to, x86IntRegType from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
write8<I>( 0xB6 ); write8( 0xB6 );
} }
emitterT void ePFRSQRTRtoR( x86IntRegType to, x86IntRegType from ) emitterT void PFRSQRTRtoR( x86IntRegType to, x86IntRegType from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
write8<I>( 0x97 ); write8( 0x97 );
} }
emitterT void ePFRSQIT1RtoR( x86IntRegType to, x86IntRegType from ) emitterT void PFRSQIT1RtoR( x86IntRegType to, x86IntRegType from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
write8<I>( 0xA7 ); write8( 0xA7 );
} }
emitterT void ePF2IDMtoR( x86IntRegType to, uptr from ) emitterT void PF2IDMtoR( x86IntRegType to, uptr from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( from ); write32( from );
write8<I>( 0x1D ); write8( 0x1D );
} }
emitterT void ePF2IDRtoR( x86IntRegType to, x86IntRegType from ) emitterT void PF2IDRtoR( x86IntRegType to, x86IntRegType from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
write8<I>( 0x1D ); write8( 0x1D );
} }
emitterT void ePI2FDMtoR( x86IntRegType to, uptr from ) emitterT void PI2FDMtoR( x86IntRegType to, uptr from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( from ); write32( from );
write8<I>( 0x0D ); write8( 0x0D );
} }
emitterT void ePI2FDRtoR( x86IntRegType to, x86IntRegType from ) emitterT void PI2FDRtoR( x86IntRegType to, x86IntRegType from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
write8<I>( 0x0D ); write8( 0x0D );
} }
emitterT void ePFMAXMtoR( x86IntRegType to, uptr from ) emitterT void PFMAXMtoR( x86IntRegType to, uptr from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( from ); write32( from );
write8<I>( 0xA4 ); write8( 0xA4 );
} }
emitterT void ePFMAXRtoR( x86IntRegType to, x86IntRegType from ) emitterT void PFMAXRtoR( x86IntRegType to, x86IntRegType from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
write8<I>( 0xA4 ); write8( 0xA4 );
} }
emitterT void ePFMINMtoR( x86IntRegType to, uptr from ) emitterT void PFMINMtoR( x86IntRegType to, uptr from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( from ); write32( from );
write8<I>( 0x94 ); write8( 0x94 );
} }
emitterT void ePFMINRtoR( x86IntRegType to, x86IntRegType from ) emitterT void PFMINRtoR( x86IntRegType to, x86IntRegType from )
{ {
write16<I>( 0x0F0F ); write16( 0x0F0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
write8<I>( 0x94 ); write8( 0x94 );
} }

246
pcsx2/x86/ix86/ix86_fpu.inl
View File

@ -24,253 +24,253 @@
//------------------------------------------------------------------ //------------------------------------------------------------------
/* fild m32 to fpu reg stack */ /* fild m32 to fpu reg stack */
emitterT void eFILD32( u32 from ) emitterT void FILD32( u32 from )
{ {
write8<I>( 0xDB ); write8( 0xDB );
ModRM<I>( 0, 0x0, DISP32 ); ModRM( 0, 0x0, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
/* fistp m32 from fpu reg stack */ /* fistp m32 from fpu reg stack */
emitterT void eFISTP32( u32 from ) emitterT void FISTP32( u32 from )
{ {
write8<I>( 0xDB ); write8( 0xDB );
ModRM<I>( 0, 0x3, DISP32 ); ModRM( 0, 0x3, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
/* fld m32 to fpu reg stack */ /* fld m32 to fpu reg stack */
emitterT void eFLD32( u32 from ) emitterT void FLD32( u32 from )
{ {
write8<I>( 0xD9 ); write8( 0xD9 );
ModRM<I>( 0, 0x0, DISP32 ); ModRM( 0, 0x0, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
// fld st(i) // fld st(i)
emitterT void eFLD(int st) { write16<I>(0xc0d9+(st<<8)); } emitterT void FLD(int st) { write16(0xc0d9+(st<<8)); }
emitterT void eFLD1() { write16<I>(0xe8d9); } emitterT void FLD1() { write16(0xe8d9); }
emitterT void eFLDL2E() { write16<I>(0xead9); } emitterT void FLDL2E() { write16(0xead9); }
/* fst m32 from fpu reg stack */ /* fst m32 from fpu reg stack */
emitterT void eFST32( u32 to ) emitterT void FST32( u32 to )
{ {
write8<I>( 0xD9 ); write8( 0xD9 );
ModRM<I>( 0, 0x2, DISP32 ); ModRM( 0, 0x2, DISP32 );
write32<I>( MEMADDR(to, 4) ); write32( MEMADDR(to, 4) );
} }
/* fstp m32 from fpu reg stack */ /* fstp m32 from fpu reg stack */
emitterT void eFSTP32( u32 to ) emitterT void FSTP32( u32 to )
{ {
write8<I>( 0xD9 ); write8( 0xD9 );
ModRM<I>( 0, 0x3, DISP32 ); ModRM( 0, 0x3, DISP32 );
write32<I>( MEMADDR(to, 4) ); write32( MEMADDR(to, 4) );
} }
// fstp st(i) // fstp st(i)
emitterT void eFSTP(int st) { write16<I>(0xd8dd+(st<<8)); } emitterT void FSTP(int st) { write16(0xd8dd+(st<<8)); }
/* fldcw fpu control word from m16 */ /* fldcw fpu control word from m16 */
emitterT void eFLDCW( u32 from ) emitterT void FLDCW( u32 from )
{ {
write8<I>( 0xD9 ); write8( 0xD9 );
ModRM<I>( 0, 0x5, DISP32 ); ModRM( 0, 0x5, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
/* fnstcw fpu control word to m16 */ /* fnstcw fpu control word to m16 */
emitterT void eFNSTCW( u32 to ) emitterT void FNSTCW( u32 to )
{ {
write8<I>( 0xD9 ); write8( 0xD9 );
ModRM<I>( 0, 0x7, DISP32 ); ModRM( 0, 0x7, DISP32 );
write32<I>( MEMADDR(to, 4) ); write32( MEMADDR(to, 4) );
} }
emitterT void eFNSTSWtoAX() { write16<I>(0xE0DF); } emitterT void FNSTSWtoAX() { write16(0xE0DF); }
emitterT void eFXAM() { write16<I>(0xe5d9); } emitterT void FXAM() { write16(0xe5d9); }
emitterT void eFDECSTP() { write16<I>(0xf6d9); } emitterT void FDECSTP() { write16(0xf6d9); }
emitterT void eFRNDINT() { write16<I>(0xfcd9); } emitterT void FRNDINT() { write16(0xfcd9); }
emitterT void eFXCH(int st) { write16<I>(0xc8d9+(st<<8)); } emitterT void FXCH(int st) { write16(0xc8d9+(st<<8)); }
emitterT void eF2XM1() { write16<I>(0xf0d9); } emitterT void F2XM1() { write16(0xf0d9); }
emitterT void eFSCALE() { write16<I>(0xfdd9); } emitterT void FSCALE() { write16(0xfdd9); }
emitterT void eFPATAN(void) { write16<I>(0xf3d9); } emitterT void FPATAN(void) { write16(0xf3d9); }
emitterT void eFSIN(void) { write16<I>(0xfed9); } emitterT void FSIN(void) { write16(0xfed9); }
/* fadd ST(src) to fpu reg stack ST(0) */ /* fadd ST(src) to fpu reg stack ST(0) */
emitterT void eFADD32Rto0( x86IntRegType src ) emitterT void FADD32Rto0( x86IntRegType src )
{ {
write8<I>( 0xD8 ); write8( 0xD8 );
write8<I>( 0xC0 + src ); write8( 0xC0 + src );
} }
/* fadd ST(0) to fpu reg stack ST(src) */ /* fadd ST(0) to fpu reg stack ST(src) */
emitterT void eFADD320toR( x86IntRegType src ) emitterT void FADD320toR( x86IntRegType src )
{ {
write8<I>( 0xDC ); write8( 0xDC );
write8<I>( 0xC0 + src ); write8( 0xC0 + src );
} }
/* fsub ST(src) to fpu reg stack ST(0) */ /* fsub ST(src) to fpu reg stack ST(0) */
emitterT void eFSUB32Rto0( x86IntRegType src ) emitterT void FSUB32Rto0( x86IntRegType src )
{ {
write8<I>( 0xD8 ); write8( 0xD8 );
write8<I>( 0xE0 + src ); write8( 0xE0 + src );
} }
/* fsub ST(0) to fpu reg stack ST(src) */ /* fsub ST(0) to fpu reg stack ST(src) */
emitterT void eFSUB320toR( x86IntRegType src ) emitterT void FSUB320toR( x86IntRegType src )
{ {
write8<I>( 0xDC ); write8( 0xDC );
write8<I>( 0xE8 + src ); write8( 0xE8 + src );
} }
/* fsubp -> substract ST(0) from ST(1), store in ST(1) and POP stack */ /* fsubp -> substract ST(0) from ST(1), store in ST(1) and POP stack */
emitterT void eFSUBP( void ) emitterT void FSUBP( void )
{ {
write8<I>( 0xDE ); write8( 0xDE );
write8<I>( 0xE9 ); write8( 0xE9 );
} }
/* fmul ST(src) to fpu reg stack ST(0) */ /* fmul ST(src) to fpu reg stack ST(0) */
emitterT void eFMUL32Rto0( x86IntRegType src ) emitterT void FMUL32Rto0( x86IntRegType src )
{ {
write8<I>( 0xD8 ); write8( 0xD8 );
write8<I>( 0xC8 + src ); write8( 0xC8 + src );
} }
/* fmul ST(0) to fpu reg stack ST(src) */ /* fmul ST(0) to fpu reg stack ST(src) */
emitterT void eFMUL320toR( x86IntRegType src ) emitterT void FMUL320toR( x86IntRegType src )
{ {
write8<I>( 0xDC ); write8( 0xDC );
write8<I>( 0xC8 + src ); write8( 0xC8 + src );
} }
/* fdiv ST(src) to fpu reg stack ST(0) */ /* fdiv ST(src) to fpu reg stack ST(0) */
emitterT void eFDIV32Rto0( x86IntRegType src ) emitterT void FDIV32Rto0( x86IntRegType src )
{ {
write8<I>( 0xD8 ); write8( 0xD8 );
write8<I>( 0xF0 + src ); write8( 0xF0 + src );
} }
/* fdiv ST(0) to fpu reg stack ST(src) */ /* fdiv ST(0) to fpu reg stack ST(src) */
emitterT void eFDIV320toR( x86IntRegType src ) emitterT void FDIV320toR( x86IntRegType src )
{ {
write8<I>( 0xDC ); write8( 0xDC );
write8<I>( 0xF8 + src ); write8( 0xF8 + src );
} }
emitterT void eFDIV320toRP( x86IntRegType src ) emitterT void FDIV320toRP( x86IntRegType src )
{ {
write8<I>( 0xDE ); write8( 0xDE );
write8<I>( 0xF8 + src ); write8( 0xF8 + src );
} }
/* fadd m32 to fpu reg stack */ /* fadd m32 to fpu reg stack */
emitterT void eFADD32( u32 from ) emitterT void FADD32( u32 from )
{ {
write8<I>( 0xD8 ); write8( 0xD8 );
ModRM<I>( 0, 0x0, DISP32 ); ModRM( 0, 0x0, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
/* fsub m32 to fpu reg stack */ /* fsub m32 to fpu reg stack */
emitterT void eFSUB32( u32 from ) emitterT void FSUB32( u32 from )
{ {
write8<I>( 0xD8 ); write8( 0xD8 );
ModRM<I>( 0, 0x4, DISP32 ); ModRM( 0, 0x4, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
/* fmul m32 to fpu reg stack */ /* fmul m32 to fpu reg stack */
emitterT void eFMUL32( u32 from ) emitterT void FMUL32( u32 from )
{ {
write8<I>( 0xD8 ); write8( 0xD8 );
ModRM<I>( 0, 0x1, DISP32 ); ModRM( 0, 0x1, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
/* fdiv m32 to fpu reg stack */ /* fdiv m32 to fpu reg stack */
emitterT void eFDIV32( u32 from ) emitterT void FDIV32( u32 from )
{ {
write8<I>( 0xD8 ); write8( 0xD8 );
ModRM<I>( 0, 0x6, DISP32 ); ModRM( 0, 0x6, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
/* fabs fpu reg stack */ /* fabs fpu reg stack */
emitterT void eFABS( void ) emitterT void FABS( void )
{ {
write16<I>( 0xE1D9 ); write16( 0xE1D9 );
} }
/* fsqrt fpu reg stack */ /* fsqrt fpu reg stack */
emitterT void eFSQRT( void ) emitterT void FSQRT( void )
{ {
write16<I>( 0xFAD9 ); write16( 0xFAD9 );
} }
/* fchs fpu reg stack */ /* fchs fpu reg stack */
emitterT void eFCHS( void ) emitterT void FCHS( void )
{ {
write16<I>( 0xE0D9 ); write16( 0xE0D9 );
} }
/* fcomi st, st(i) */ /* fcomi st, st(i) */
emitterT void eFCOMI( x86IntRegType src ) emitterT void FCOMI( x86IntRegType src )
{ {
write8<I>( 0xDB ); write8( 0xDB );
write8<I>( 0xF0 + src ); write8( 0xF0 + src );
} }
/* fcomip st, st(i) */ /* fcomip st, st(i) */
emitterT void eFCOMIP( x86IntRegType src ) emitterT void FCOMIP( x86IntRegType src )
{ {
write8<I>( 0xDF ); write8( 0xDF );
write8<I>( 0xF0 + src ); write8( 0xF0 + src );
} }
/* fucomi st, st(i) */ /* fucomi st, st(i) */
emitterT void eFUCOMI( x86IntRegType src ) emitterT void FUCOMI( x86IntRegType src )
{ {
write8<I>( 0xDB ); write8( 0xDB );
write8<I>( 0xE8 + src ); write8( 0xE8 + src );
} }
/* fucomip st, st(i) */ /* fucomip st, st(i) */
emitterT void eFUCOMIP( x86IntRegType src ) emitterT void FUCOMIP( x86IntRegType src )
{ {
write8<I>( 0xDF ); write8( 0xDF );
write8<I>( 0xE8 + src ); write8( 0xE8 + src );
} }
/* fcom m32 to fpu reg stack */ /* fcom m32 to fpu reg stack */
emitterT void eFCOM32( u32 from ) emitterT void FCOM32( u32 from )
{ {
write8<I>( 0xD8 ); write8( 0xD8 );
ModRM<I>( 0, 0x2, DISP32 ); ModRM( 0, 0x2, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
/* fcomp m32 to fpu reg stack */ /* fcomp m32 to fpu reg stack */
emitterT void eFCOMP32( u32 from ) emitterT void FCOMP32( u32 from )
{ {
write8<I>( 0xD8 ); write8( 0xD8 );
ModRM<I>( 0, 0x3, DISP32 ); ModRM( 0, 0x3, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
#define FCMOV32( low, high ) \ #define FCMOV32( low, high ) \
{ \ { \
write8<I>( low ); \ write8( low ); \
write8<I>( high + from ); \ write8( high + from ); \
} }
emitterT void eFCMOVB32( x86IntRegType from ) { FCMOV32( 0xDA, 0xC0 ); } emitterT void FCMOVB32( x86IntRegType from ) { FCMOV32( 0xDA, 0xC0 ); }
emitterT void eFCMOVE32( x86IntRegType from ) { FCMOV32( 0xDA, 0xC8 ); } emitterT void FCMOVE32( x86IntRegType from ) { FCMOV32( 0xDA, 0xC8 ); }
emitterT void eFCMOVBE32( x86IntRegType from ) { FCMOV32( 0xDA, 0xD0 ); } emitterT void FCMOVBE32( x86IntRegType from ) { FCMOV32( 0xDA, 0xD0 ); }
emitterT void eFCMOVU32( x86IntRegType from ) { FCMOV32( 0xDA, 0xD8 ); } emitterT void FCMOVU32( x86IntRegType from ) { FCMOV32( 0xDA, 0xD8 ); }
emitterT void eFCMOVNB32( x86IntRegType from ) { FCMOV32( 0xDB, 0xC0 ); } emitterT void FCMOVNB32( x86IntRegType from ) { FCMOV32( 0xDB, 0xC0 ); }
emitterT void eFCMOVNE32( x86IntRegType from ) { FCMOV32( 0xDB, 0xC8 ); } emitterT void FCMOVNE32( x86IntRegType from ) { FCMOV32( 0xDB, 0xC8 ); }
emitterT void eFCMOVNBE32( x86IntRegType from ) { FCMOV32( 0xDB, 0xD0 ); } emitterT void FCMOVNBE32( x86IntRegType from ) { FCMOV32( 0xDB, 0xD0 ); }
emitterT void eFCMOVNU32( x86IntRegType from ) { FCMOV32( 0xDB, 0xD8 ); } emitterT void FCMOVNU32( x86IntRegType from ) { FCMOV32( 0xDB, 0xD8 ); }

111
pcsx2/x86/ix86/ix86_group1.inl
View File

@ -66,7 +66,7 @@ emitterT void EmitSibMagic( int regfield, const ModSib& info )
int displacement_size = (info.Displacement == 0) ? 0 : int displacement_size = (info.Displacement == 0) ? 0 :
( ( info.IsByteSizeDisp() ) ? 1 : 2 ); ( ( info.IsByteSizeDisp() ) ? 1 : 2 );
if( !NeedsSibMagic<I>( info ) ) if( !NeedsSibMagic( info ) )
{ {
// Use ModRm-only encoding, with the rm field holding an index/base register, if // Use ModRm-only encoding, with the rm field holding an index/base register, if
// one has been specified. If neither register is specified then use Disp32 form, // one has been specified. If neither register is specified then use Disp32 form,
@ -76,26 +76,26 @@ emitterT void EmitSibMagic( int regfield, const ModSib& info )
x86Register basereg = info.GetEitherReg(); x86Register basereg = info.GetEitherReg();
if( basereg.IsEmpty() ) if( basereg.IsEmpty() )
ModRM<I>( 0, regfield, ModRm_UseDisp32 ); ModRM( 0, regfield, ModRm_UseDisp32 );
else else
{ {
if( basereg == ebp && displacement_size == 0 ) if( basereg == ebp && displacement_size == 0 )
displacement_size = 1; // forces [ebp] to be encoded as [ebp+0]! displacement_size = 1; // forces [ebp] to be encoded as [ebp+0]!
ModRM<I>( displacement_size, regfield, basereg.Id ); ModRM( displacement_size, regfield, basereg.Id );
} }
} }
else else
{ {
ModRM<I>( displacement_size, regfield, ModRm_UseSib ); ModRM( displacement_size, regfield, ModRm_UseSib );
SibSB<I>( info.Index.Id, info.Scale, info.Base.Id ); SibSB( info.Index.Id, info.Scale, info.Base.Id );
} }
switch( displacement_size ) switch( displacement_size )
{ {
case 0: break; case 0: break;
case 1: write8<I>( info.Displacement ); break; case 1: write8( info.Displacement ); break;
case 2: write32<I>( info.Displacement ); break; case 2: write32( info.Displacement ); break;
jNO_DEFAULT jNO_DEFAULT
} }
} }
@ -108,7 +108,7 @@ emitterT void EmitSibMagic( int regfield, const ModSib& info )
// //
emitterT void EmitSibMagic( x86Register regfield, const ModSib& info ) emitterT void EmitSibMagic( x86Register regfield, const ModSib& info )
{ {
EmitSibMagic<I>( regfield.Id, info ); EmitSibMagic( regfield.Id, info );
} }
enum Group1InstructionType enum Group1InstructionType
@ -126,82 +126,93 @@ enum Group1InstructionType
emitterT void Group1_32( Group1InstructionType inst, x86Register to, x86Register from ) emitterT void Group1_32( Group1InstructionType inst, x86Register to, x86Register from )
{ {
write8<I>( 0x01 | (inst<<3) ); write8( 0x01 | (inst<<3) );
ModRM<I>( 3, from.Id, to.Id ); ModRM( 3, from.Id, to.Id );
} }
emitterT void Group1_32( Group1InstructionType inst, x86Register to, u32 imm ) emitterT void Group1_32( Group1InstructionType inst, x86Register to, u32 imm )
{ {
if( is_s8( imm ) ) if( is_s8( imm ) )
{ {
write8<I>( 0x83 ); write8( 0x83 );
ModRM<I>( 3, inst, to.Id ); ModRM( 3, inst, to.Id );
write8<I>( (s8)imm ); write8( (s8)imm );
} }
else else
{ {
if( to == eax ) if( to == eax )
write8<I>( 0x05 | (inst<<3) ); write8( 0x05 | (inst<<3) );
else else
{ {
write8<I>( 0x81 ); write8( 0x81 );
ModRM<I>( 3, inst, to.Id ); ModRM( 3, inst, to.Id );
} }
write32<I>( imm ); write32( imm );
} }
} }
emitterT void Group1_32( Group1InstructionType inst, const ModSib& sibdest, u32 imm ) emitterT void Group1_32( Group1InstructionType inst, const ModSib& sibdest, u32 imm )
{ {
write8<I>( is_s8( imm ) ? 0x83 : 0x81 ); write8( is_s8( imm ) ? 0x83 : 0x81 );
EmitSibMagic<I>( inst, sibdest ); EmitSibMagic( inst, sibdest );
if( is_s8( imm ) ) if( is_s8( imm ) )
write8<I>( (s8)imm ); write8( (s8)imm );
else else
write32<I>( imm ); write32( imm );
} }
emitterT void Group1_32( Group1InstructionType inst, const ModSib& sibdest, x86Register from ) emitterT void Group1_32( Group1InstructionType inst, const ModSib& sibdest, x86Register from )
{ {
write8<I>( 0x01 | (inst<<3) ); write8( 0x01 | (inst<<3) );
EmitSibMagic<I>( from, sibdest ); EmitSibMagic( from, sibdest );
} }
/* add m32 to r32 */ /* add m32 to r32 */
emitterT void Group1_32( Group1InstructionType inst, x86Register to, const ModSib& sibsrc ) emitterT void Group1_32( Group1InstructionType inst, x86Register to, const ModSib& sibsrc )
{ {
write8<I>( 0x03 | (inst<<3) ); write8( 0x03 | (inst<<3) );
EmitSibMagic<I>( to, sibsrc ); EmitSibMagic( to, sibsrc );
} }
emitterT void Group1_8( Group1InstructionType inst, x86Register to, s8 imm ) emitterT void Group1_8( Group1InstructionType inst, x86Register to, s8 imm )
{ {
if( to == eax ) if( to == eax )
{ {
write8<I>( 0x04 | (inst<<3) ); write8( 0x04 | (inst<<3) );
write8<I>( imm ); write8( imm );
} }
else else
{ {
write8<I>( 0x80 ); write8( 0x80 );
ModRM<I>( 3, inst, to.Id ); ModRM( 3, inst, to.Id );
write8<I>( imm ); write8( imm );
} }
} }
////////////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////
// //
#define DEFINE_GROUP1_OPCODE( lwr, cod ) \ #define DEFINE_GROUP1_OPCODE( lwr, cod ) \
emitterT void lwr##32( x86Register to, x86Register from ) { Group1_32<I>( G1Type_##cod, to, from ); } \ emitterT void lwr##32( x86Register to, x86Register from ) { Group1_32( G1Type_##cod, to, from ); } \
emitterT void lwr##32( x86Register to, u32 imm ) { Group1_32<I>( G1Type_##cod, to, imm ); } \ emitterT void lwr##32( x86Register to, u32 imm ) { Group1_32( G1Type_##cod, to, imm ); } \
emitterT void lwr##32( x86Register to, void* from ) { Group1_32<I>( G1Type_##cod, to, ptr[from] ); } \ emitterT void lwr##32( x86Register to, void* from ) { Group1_32( G1Type_##cod, to, ptr[from] ); } \
emitterT void lwr##32( void* to, x86Register from ) { Group1_32<I>( G1Type_##cod, ptr[to], from ); } \ emitterT void lwr##32( void* to, x86Register from ) { Group1_32( G1Type_##cod, ptr[to], from ); } \
emitterT void lwr##32( void* to, u32 imm ) { Group1_32<I>( G1Type_##cod, ptr[to], imm ); } \ emitterT void lwr##32( void* to, u32 imm ) { Group1_32( G1Type_##cod, ptr[to], imm ); } \
emitterT void lwr##32( x86Register to, const x86ModRm& from ) { Group1_32<I>( G1Type_##cod, to, ptr[from] ); } \ emitterT void lwr##32( x86Register to, const x86ModRm& from ) { Group1_32( G1Type_##cod, to, ptr[from] ); } \
emitterT void lwr##32( const x86ModRm& to, x86Register from ) { Group1_32<I>( G1Type_##cod, ptr[to], from ); } \ emitterT void lwr##32( const x86ModRm& to, x86Register from ) { Group1_32( G1Type_##cod, ptr[to], from ); } \
emitterT void lwr##32( const x86ModRm& to, u32 imm ) { Group1_32<I>( G1Type_##cod, ptr[to], imm ); } emitterT void lwr##32( const x86ModRm& to, u32 imm ) { Group1_32( G1Type_##cod, ptr[to], imm ); }
/*
emitterT void lwr##16( x86Register16 to, x86Register16 from ) { Group1_32( G1Type_##cod, to, from ); } \
emitterT void lwr##16( x86Register16 to, u16 imm ) { Group1_32( G1Type_##cod, to, imm ); } \
emitterT void lwr##16( x86Register16 to, void* from ) { Group1_32( G1Type_##cod, to, ptr[from] ); } \
emitterT void lwr##16( void* to, x86Register16 from ) { Group1_32( G1Type_##cod, ptr[to], from ); } \
emitterT void lwr##16( void* to, u16 imm ) { Group1_32( G1Type_##cod, ptr[to], imm ); } \
emitterT void lwr##16( x86Register16 to, const x86ModRm& from ){ Group1_32( G1Type_##cod, to, ptr[from] ); } \
emitterT void lwr##16( const x86ModRm& to, x86Register16 from ){ Group1_32( G1Type_##cod, ptr[to], from ); } \
emitterT void lwr##16( const x86ModRm& to, u32 imm ) { Group1_32( G1Type_##cod, ptr[to], imm ); }
*/
DEFINE_GROUP1_OPCODE( add, ADD ); DEFINE_GROUP1_OPCODE( add, ADD );
DEFINE_GROUP1_OPCODE( cmp, CMP ); DEFINE_GROUP1_OPCODE( cmp, CMP );
@ -229,14 +240,14 @@ static __forceinline x86Emitter::x86ModRm _mrmhlp( x86IntRegType src )
////////////////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////////////////
// //
#define DEFINE_GROUP1_OPCODE_LEGACY( lwr, cod ) \ #define DEFINE_GROUP1_OPCODE_LEGACY( lwr, cod ) \
emitterT void e##cod##32RtoR( x86IntRegType to, x86IntRegType from ) { x86Emitter::lwr##32<I>( _reghlp(to), _reghlp(from) ); } \ emitterT void cod##32RtoR( x86IntRegType to, x86IntRegType from ) { x86Emitter::lwr##32( _reghlp(to), _reghlp(from) ); } \
emitterT void e##cod##32ItoR( x86IntRegType to, u32 imm ) { x86Emitter::lwr##32<I>( _reghlp(to), imm ); } \ emitterT void cod##32ItoR( x86IntRegType to, u32 imm ) { x86Emitter::lwr##32( _reghlp(to), imm ); } \
emitterT void e##cod##32MtoR( x86IntRegType to, uptr from ) { x86Emitter::lwr##32<I>( _reghlp(to), (void*)from ); } \ emitterT void cod##32MtoR( x86IntRegType to, uptr from ) { x86Emitter::lwr##32( _reghlp(to), (void*)from ); } \
emitterT void e##cod##32RtoM( uptr to, x86IntRegType from ) { x86Emitter::lwr##32<I>( (void*)to, _reghlp(from) ); } \ emitterT void cod##32RtoM( uptr to, x86IntRegType from ) { x86Emitter::lwr##32( (void*)to, _reghlp(from) ); } \
emitterT void e##cod##32ItoM( uptr to, u32 imm ) { x86Emitter::lwr##32<I>( (void*)to, imm ); } \ emitterT void cod##32ItoM( uptr to, u32 imm ) { x86Emitter::lwr##32( (void*)to, imm ); } \
emitterT void e##cod##32ItoRm( x86IntRegType to, u32 imm, int offset=0 ){ x86Emitter::lwr##32<I>( _mrmhlp(to) + offset, imm ); } \ emitterT void cod##32ItoRm( x86IntRegType to, u32 imm, int offset=0 ){ x86Emitter::lwr##32( _mrmhlp(to) + offset, imm ); } \
emitterT void e##cod##32RmtoR( x86IntRegType to, x86IntRegType from, int offset=0 ) { x86Emitter::lwr##32<I>( _reghlp(to), _mrmhlp(from) + offset ); } \ emitterT void cod##32RmtoR( x86IntRegType to, x86IntRegType from, int offset=0 ) { x86Emitter::lwr##32( _reghlp(to), _mrmhlp(from) + offset ); } \
emitterT void e##cod##32RtoRm( x86IntRegType to, x86IntRegType from, int offset=0 ) { x86Emitter::lwr##32<I>( _mrmhlp(to) + offset, _reghlp(from) ); } emitterT void cod##32RtoRm( x86IntRegType to, x86IntRegType from, int offset=0 ) { x86Emitter::lwr##32( _mrmhlp(to) + offset, _reghlp(from) ); }
DEFINE_GROUP1_OPCODE_LEGACY( add, ADD ); DEFINE_GROUP1_OPCODE_LEGACY( add, ADD );
DEFINE_GROUP1_OPCODE_LEGACY( cmp, CMP ); DEFINE_GROUP1_OPCODE_LEGACY( cmp, CMP );
@ -247,12 +258,12 @@ DEFINE_GROUP1_OPCODE_LEGACY( and, AND );
DEFINE_GROUP1_OPCODE_LEGACY( sub, SUB ); DEFINE_GROUP1_OPCODE_LEGACY( sub, SUB );
DEFINE_GROUP1_OPCODE_LEGACY( xor, XOR ); DEFINE_GROUP1_OPCODE_LEGACY( xor, XOR );
emitterT void eAND32I8toR( x86IntRegType to, s8 from ) emitterT void AND32I8toR( x86IntRegType to, s8 from )
{ {
x86Emitter::and32<I>( _reghlp(to), from ); x86Emitter::and32( _reghlp(to), from );
} }
emitterT void eAND32I8toM( uptr to, s8 from ) emitterT void AND32I8toM( uptr to, s8 from )
{ {
x86Emitter::and32<I>( (void*)to, from ); x86Emitter::and32( (void*)to, from );
} }

608
pcsx2/x86/ix86/ix86_mmx.inl
View File

@ -25,623 +25,623 @@
//------------------------------------------------------------------ //------------------------------------------------------------------
/* movq m64 to r64 */ /* movq m64 to r64 */
emitterT void eMOVQMtoR( x86MMXRegType to, uptr from ) emitterT void MOVQMtoR( x86MMXRegType to, uptr from )
{ {
write16<I>( 0x6F0F ); write16( 0x6F0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
/* movq r64 to m64 */ /* movq r64 to m64 */
emitterT void eMOVQRtoM( uptr to, x86MMXRegType from ) emitterT void MOVQRtoM( uptr to, x86MMXRegType from )
{ {
write16<I>( 0x7F0F ); write16( 0x7F0F );
ModRM<I>( 0, from, DISP32 ); ModRM( 0, from, DISP32 );
write32<I>(MEMADDR(to, 4)); write32(MEMADDR(to, 4));
} }
/* pand r64 to r64 */ /* pand r64 to r64 */
emitterT void ePANDRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PANDRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xDB0F ); write16( 0xDB0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePANDNRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PANDNRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xDF0F ); write16( 0xDF0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
/* por r64 to r64 */ /* por r64 to r64 */
emitterT void ePORRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PORRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xEB0F ); write16( 0xEB0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
/* pxor r64 to r64 */ /* pxor r64 to r64 */
emitterT void ePXORRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PXORRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xEF0F ); write16( 0xEF0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
/* psllq r64 to r64 */ /* psllq r64 to r64 */
emitterT void ePSLLQRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PSLLQRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xF30F ); write16( 0xF30F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
/* psllq m64 to r64 */ /* psllq m64 to r64 */
emitterT void ePSLLQMtoR( x86MMXRegType to, uptr from ) emitterT void PSLLQMtoR( x86MMXRegType to, uptr from )
{ {
write16<I>( 0xF30F ); write16( 0xF30F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
/* psllq imm8 to r64 */ /* psllq imm8 to r64 */
emitterT void ePSLLQItoR( x86MMXRegType to, u8 from ) emitterT void PSLLQItoR( x86MMXRegType to, u8 from )
{ {
write16<I>( 0x730F ); write16( 0x730F );
ModRM<I>( 3, 6, to); ModRM( 3, 6, to);
write8<I>( from ); write8( from );
} }
/* psrlq r64 to r64 */ /* psrlq r64 to r64 */
emitterT void ePSRLQRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PSRLQRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xD30F ); write16( 0xD30F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
/* psrlq m64 to r64 */ /* psrlq m64 to r64 */
emitterT void ePSRLQMtoR( x86MMXRegType to, uptr from ) emitterT void PSRLQMtoR( x86MMXRegType to, uptr from )
{ {
write16<I>( 0xD30F ); write16( 0xD30F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
/* psrlq imm8 to r64 */ /* psrlq imm8 to r64 */
emitterT void ePSRLQItoR( x86MMXRegType to, u8 from ) emitterT void PSRLQItoR( x86MMXRegType to, u8 from )
{ {
write16<I>( 0x730F ); write16( 0x730F );
ModRM<I>( 3, 2, to); ModRM( 3, 2, to);
write8<I>( from ); write8( from );
} }
/* paddusb r64 to r64 */ /* paddusb r64 to r64 */
emitterT void ePADDUSBRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PADDUSBRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xDC0F ); write16( 0xDC0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
/* paddusb m64 to r64 */ /* paddusb m64 to r64 */
emitterT void ePADDUSBMtoR( x86MMXRegType to, uptr from ) emitterT void PADDUSBMtoR( x86MMXRegType to, uptr from )
{ {
write16<I>( 0xDC0F ); write16( 0xDC0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
/* paddusw r64 to r64 */ /* paddusw r64 to r64 */
emitterT void ePADDUSWRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PADDUSWRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xDD0F ); write16( 0xDD0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
/* paddusw m64 to r64 */ /* paddusw m64 to r64 */
emitterT void ePADDUSWMtoR( x86MMXRegType to, uptr from ) emitterT void PADDUSWMtoR( x86MMXRegType to, uptr from )
{ {
write16<I>( 0xDD0F ); write16( 0xDD0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
/* paddb r64 to r64 */ /* paddb r64 to r64 */
emitterT void ePADDBRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PADDBRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xFC0F ); write16( 0xFC0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
/* paddb m64 to r64 */ /* paddb m64 to r64 */
emitterT void ePADDBMtoR( x86MMXRegType to, uptr from ) emitterT void PADDBMtoR( x86MMXRegType to, uptr from )
{ {
write16<I>( 0xFC0F ); write16( 0xFC0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
/* paddw r64 to r64 */ /* paddw r64 to r64 */
emitterT void ePADDWRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PADDWRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xFD0F ); write16( 0xFD0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
/* paddw m64 to r64 */ /* paddw m64 to r64 */
emitterT void ePADDWMtoR( x86MMXRegType to, uptr from ) emitterT void PADDWMtoR( x86MMXRegType to, uptr from )
{ {
write16<I>( 0xFD0F ); write16( 0xFD0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
/* paddd r64 to r64 */ /* paddd r64 to r64 */
emitterT void ePADDDRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PADDDRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xFE0F ); write16( 0xFE0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
/* paddd m64 to r64 */ /* paddd m64 to r64 */
emitterT void ePADDDMtoR( x86MMXRegType to, uptr from ) emitterT void PADDDMtoR( x86MMXRegType to, uptr from )
{ {
write16<I>( 0xFE0F ); write16( 0xFE0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
/* emms */ /* emms */
emitterT void eEMMS() emitterT void EMMS()
{ {
write16<I>( 0x770F ); write16( 0x770F );
} }
emitterT void ePADDSBRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PADDSBRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xEC0F ); write16( 0xEC0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePADDSWRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PADDSWRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xED0F ); write16( 0xED0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
// paddq m64 to r64 (sse2 only?) // paddq m64 to r64 (sse2 only?)
emitterT void ePADDQMtoR( x86MMXRegType to, uptr from ) emitterT void PADDQMtoR( x86MMXRegType to, uptr from )
{ {
write16<I>( 0xD40F ); write16( 0xD40F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
// paddq r64 to r64 (sse2 only?) // paddq r64 to r64 (sse2 only?)
emitterT void ePADDQRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PADDQRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xD40F ); write16( 0xD40F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePSUBSBRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PSUBSBRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xE80F ); write16( 0xE80F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePSUBSWRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PSUBSWRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xE90F ); write16( 0xE90F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePSUBBRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PSUBBRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xF80F ); write16( 0xF80F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePSUBWRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PSUBWRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xF90F ); write16( 0xF90F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePSUBDRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PSUBDRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xFA0F ); write16( 0xFA0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePSUBDMtoR( x86MMXRegType to, uptr from ) emitterT void PSUBDMtoR( x86MMXRegType to, uptr from )
{ {
write16<I>( 0xFA0F ); write16( 0xFA0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
emitterT void ePSUBUSBRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PSUBUSBRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xD80F ); write16( 0xD80F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePSUBUSWRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PSUBUSWRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xD90F ); write16( 0xD90F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
// psubq m64 to r64 (sse2 only?) // psubq m64 to r64 (sse2 only?)
emitterT void ePSUBQMtoR( x86MMXRegType to, uptr from ) emitterT void PSUBQMtoR( x86MMXRegType to, uptr from )
{ {
write16<I>( 0xFB0F ); write16( 0xFB0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
// psubq r64 to r64 (sse2 only?) // psubq r64 to r64 (sse2 only?)
emitterT void ePSUBQRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PSUBQRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xFB0F ); write16( 0xFB0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
// pmuludq m64 to r64 (sse2 only?) // pmuludq m64 to r64 (sse2 only?)
emitterT void ePMULUDQMtoR( x86MMXRegType to, uptr from ) emitterT void PMULUDQMtoR( x86MMXRegType to, uptr from )
{ {
write16<I>( 0xF40F ); write16( 0xF40F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
// pmuludq r64 to r64 (sse2 only?) // pmuludq r64 to r64 (sse2 only?)
emitterT void ePMULUDQRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PMULUDQRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xF40F ); write16( 0xF40F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePCMPEQBRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PCMPEQBRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0x740F ); write16( 0x740F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePCMPEQWRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PCMPEQWRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0x750F ); write16( 0x750F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePCMPEQDRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PCMPEQDRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0x760F ); write16( 0x760F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePCMPEQDMtoR( x86MMXRegType to, uptr from ) emitterT void PCMPEQDMtoR( x86MMXRegType to, uptr from )
{ {
write16<I>( 0x760F ); write16( 0x760F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
emitterT void ePCMPGTBRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PCMPGTBRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0x640F ); write16( 0x640F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePCMPGTWRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PCMPGTWRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0x650F ); write16( 0x650F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePCMPGTDRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PCMPGTDRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0x660F ); write16( 0x660F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePCMPGTDMtoR( x86MMXRegType to, uptr from ) emitterT void PCMPGTDMtoR( x86MMXRegType to, uptr from )
{ {
write16<I>( 0x660F ); write16( 0x660F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
emitterT void ePSRLWItoR( x86MMXRegType to, u8 from ) emitterT void PSRLWItoR( x86MMXRegType to, u8 from )
{ {
write16<I>( 0x710F ); write16( 0x710F );
ModRM<I>( 3, 2 , to ); ModRM( 3, 2 , to );
write8<I>( from ); write8( from );
} }
emitterT void ePSRLDItoR( x86MMXRegType to, u8 from ) emitterT void PSRLDItoR( x86MMXRegType to, u8 from )
{ {
write16<I>( 0x720F ); write16( 0x720F );
ModRM<I>( 3, 2 , to ); ModRM( 3, 2 , to );
write8<I>( from ); write8( from );
} }
emitterT void ePSRLDRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PSRLDRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xD20F ); write16( 0xD20F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePSLLWItoR( x86MMXRegType to, u8 from ) emitterT void PSLLWItoR( x86MMXRegType to, u8 from )
{ {
write16<I>( 0x710F ); write16( 0x710F );
ModRM<I>( 3, 6 , to ); ModRM( 3, 6 , to );
write8<I>( from ); write8( from );
} }
emitterT void ePSLLDItoR( x86MMXRegType to, u8 from ) emitterT void PSLLDItoR( x86MMXRegType to, u8 from )
{ {
write16<I>( 0x720F ); write16( 0x720F );
ModRM<I>( 3, 6 , to ); ModRM( 3, 6 , to );
write8<I>( from ); write8( from );
} }
emitterT void ePSLLDRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PSLLDRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xF20F ); write16( 0xF20F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePSRAWItoR( x86MMXRegType to, u8 from ) emitterT void PSRAWItoR( x86MMXRegType to, u8 from )
{ {
write16<I>( 0x710F ); write16( 0x710F );
ModRM<I>( 3, 4 , to ); ModRM( 3, 4 , to );
write8<I>( from ); write8( from );
} }
emitterT void ePSRADItoR( x86MMXRegType to, u8 from ) emitterT void PSRADItoR( x86MMXRegType to, u8 from )
{ {
write16<I>( 0x720F ); write16( 0x720F );
ModRM<I>( 3, 4 , to ); ModRM( 3, 4 , to );
write8<I>( from ); write8( from );
} }
emitterT void ePSRADRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PSRADRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0xE20F ); write16( 0xE20F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
/* por m64 to r64 */ /* por m64 to r64 */
emitterT void ePORMtoR( x86MMXRegType to, uptr from ) emitterT void PORMtoR( x86MMXRegType to, uptr from )
{ {
write16<I>( 0xEB0F ); write16( 0xEB0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
/* pxor m64 to r64 */ /* pxor m64 to r64 */
emitterT void ePXORMtoR( x86MMXRegType to, uptr from ) emitterT void PXORMtoR( x86MMXRegType to, uptr from )
{ {
write16<I>( 0xEF0F ); write16( 0xEF0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
/* pand m64 to r64 */ /* pand m64 to r64 */
emitterT void ePANDMtoR( x86MMXRegType to, uptr from ) emitterT void PANDMtoR( x86MMXRegType to, uptr from )
{ {
//u64 rip = (u64)x86Ptr[0] + 7; //u64 rip = (u64)x86Ptr + 7;
write16<I>( 0xDB0F ); write16( 0xDB0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
emitterT void ePANDNMtoR( x86MMXRegType to, uptr from ) emitterT void PANDNMtoR( x86MMXRegType to, uptr from )
{ {
write16<I>( 0xDF0F ); write16( 0xDF0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
emitterT void ePUNPCKHDQRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PUNPCKHDQRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0x6A0F ); write16( 0x6A0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePUNPCKHDQMtoR( x86MMXRegType to, uptr from ) emitterT void PUNPCKHDQMtoR( x86MMXRegType to, uptr from )
{ {
write16<I>( 0x6A0F ); write16( 0x6A0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
emitterT void ePUNPCKLDQRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void PUNPCKLDQRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0x620F ); write16( 0x620F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePUNPCKLDQMtoR( x86MMXRegType to, uptr from ) emitterT void PUNPCKLDQMtoR( x86MMXRegType to, uptr from )
{ {
write16<I>( 0x620F ); write16( 0x620F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
emitterT void eMOVQ64ItoR( x86MMXRegType reg, u64 i ) emitterT void MOVQ64ItoR( x86MMXRegType reg, u64 i )
{ {
eMOVQMtoR<I>( reg, ( uptr )(x86Ptr[0]) + 2 + 7 ); MOVQMtoR( reg, ( uptr )(x86Ptr) + 2 + 7 );
eJMP8<I>( 8 ); JMP8( 8 );
write64<I>( i ); write64( i );
} }
emitterT void eMOVQRtoR( x86MMXRegType to, x86MMXRegType from ) emitterT void MOVQRtoR( x86MMXRegType to, x86MMXRegType from )
{ {
write16<I>( 0x6F0F ); write16( 0x6F0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void eMOVQRmtoR( x86MMXRegType to, x86IntRegType from, int offset=0 ) emitterT void MOVQRmtoR( x86MMXRegType to, x86IntRegType from, int offset=0 )
{ {
write16<I>( 0x6F0F ); write16( 0x6F0F );
if( offset < 128 && offset >= -128) { if( offset < 128 && offset >= -128) {
ModRM<I>( 1, to, from ); ModRM( 1, to, from );
write8<I>(offset); write8(offset);
} }
else { else {
ModRM<I>( 2, to, from ); ModRM( 2, to, from );
write32<I>(offset); write32(offset);
} }
} }
emitterT void eMOVQRtoRm( x86IntRegType to, x86MMXRegType from, int offset=0 ) emitterT void MOVQRtoRm( x86IntRegType to, x86MMXRegType from, int offset=0 )
{ {
write16<I>( 0x7F0F ); write16( 0x7F0F );
if( offset < 128 && offset >= -128) { if( offset < 128 && offset >= -128) {
ModRM<I>( 1, from , to ); ModRM( 1, from , to );
write8<I>(offset); write8(offset);
} }
else { else {
ModRM<I>( 2, from, to ); ModRM( 2, from, to );
write32<I>(offset); write32(offset);
} }
} }
/* movd m32 to r64 */ /* movd m32 to r64 */
emitterT void eMOVDMtoMMX( x86MMXRegType to, uptr from ) emitterT void MOVDMtoMMX( x86MMXRegType to, uptr from )
{ {
write16<I>( 0x6E0F ); write16( 0x6E0F );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
} }
/* movd r64 to m32 */ /* movd r64 to m32 */
emitterT void eMOVDMMXtoM( uptr to, x86MMXRegType from ) emitterT void MOVDMMXtoM( uptr to, x86MMXRegType from )
{ {
write16<I>( 0x7E0F ); write16( 0x7E0F );
ModRM<I>( 0, from, DISP32 ); ModRM( 0, from, DISP32 );
write32<I>( MEMADDR(to, 4) ); write32( MEMADDR(to, 4) );
} }
emitterT void eMOVD32RtoMMX( x86MMXRegType to, x86IntRegType from ) emitterT void MOVD32RtoMMX( x86MMXRegType to, x86IntRegType from )
{ {
write16<I>( 0x6E0F ); write16( 0x6E0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void eMOVD32RmtoMMX( x86MMXRegType to, x86IntRegType from ) emitterT void MOVD32RmtoMMX( x86MMXRegType to, x86IntRegType from )
{ {
write16<I>( 0x6E0F ); write16( 0x6E0F );
ModRM<I>( 0, to, from ); ModRM( 0, to, from );
} }
emitterT void eMOVD32RmOffsettoMMX( x86MMXRegType to, x86IntRegType from, u32 offset ) emitterT void MOVD32RmOffsettoMMX( x86MMXRegType to, x86IntRegType from, u32 offset )
{ {
write16<I>( 0x6E0F ); write16( 0x6E0F );
if( offset < 128 ) { if( offset < 128 ) {
ModRM<I>( 1, to, from ); ModRM( 1, to, from );
write8<I>(offset); write8(offset);
} }
else { else {
ModRM<I>( 2, to, from ); ModRM( 2, to, from );
write32<I>(offset); write32(offset);
} }
} }
emitterT void eMOVD32MMXtoR( x86IntRegType to, x86MMXRegType from ) emitterT void MOVD32MMXtoR( x86IntRegType to, x86MMXRegType from )
{ {
write16<I>( 0x7E0F ); write16( 0x7E0F );
ModRM<I>( 3, from, to ); ModRM( 3, from, to );
} }
emitterT void eMOVD32MMXtoRm( x86IntRegType to, x86MMXRegType from ) emitterT void MOVD32MMXtoRm( x86IntRegType to, x86MMXRegType from )
{ {
write16<I>( 0x7E0F ); write16( 0x7E0F );
ModRM<I>( 0, from, to ); ModRM( 0, from, to );
if( to >= 4 ) { if( to >= 4 ) {
// no idea why // no idea why
assert( to == ESP ); assert( to == ESP );
write8<I>(0x24); write8(0x24);
} }
} }
emitterT void eMOVD32MMXtoRmOffset( x86IntRegType to, x86MMXRegType from, u32 offset ) emitterT void MOVD32MMXtoRmOffset( x86IntRegType to, x86MMXRegType from, u32 offset )
{ {
write16<I>( 0x7E0F ); write16( 0x7E0F );
if( offset < 128 ) { if( offset < 128 ) {
ModRM<I>( 1, from, to ); ModRM( 1, from, to );
write8<I>(offset); write8(offset);
} }
else { else {
ModRM<I>( 2, from, to ); ModRM( 2, from, to );
write32<I>(offset); write32(offset);
} }
} }
///* movd r32 to r64 */ ///* movd r32 to r64 */
//emitterT void eMOVD32MMXtoMMX( x86MMXRegType to, x86MMXRegType from ) //emitterT void MOVD32MMXtoMMX( x86MMXRegType to, x86MMXRegType from )
//{ //{
// write16<I>( 0x6E0F ); // write16( 0x6E0F );
// ModRM<I>( 3, to, from ); // ModRM( 3, to, from );
//} //}
// //
///* movq r64 to r32 */ ///* movq r64 to r32 */
//emitterT void eMOVD64MMXtoMMX( x86MMXRegType to, x86MMXRegType from ) //emitterT void MOVD64MMXtoMMX( x86MMXRegType to, x86MMXRegType from )
//{ //{
// write16<I>( 0x7E0F ); // write16( 0x7E0F );
// ModRM<I>( 3, from, to ); // ModRM( 3, from, to );
//} //}
// untested // untested
emitterT void ePACKSSWBMMXtoMMX(x86MMXRegType to, x86MMXRegType from) emitterT void PACKSSWBMMXtoMMX(x86MMXRegType to, x86MMXRegType from)
{ {
write16<I>( 0x630F ); write16( 0x630F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePACKSSDWMMXtoMMX(x86MMXRegType to, x86MMXRegType from) emitterT void PACKSSDWMMXtoMMX(x86MMXRegType to, x86MMXRegType from)
{ {
write16<I>( 0x6B0F ); write16( 0x6B0F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePMOVMSKBMMXtoR(x86IntRegType to, x86MMXRegType from) emitterT void PMOVMSKBMMXtoR(x86IntRegType to, x86MMXRegType from)
{ {
write16<I>( 0xD70F ); write16( 0xD70F );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }
emitterT void ePINSRWRtoMMX( x86MMXRegType to, x86SSERegType from, u8 imm8 ) emitterT void PINSRWRtoMMX( x86MMXRegType to, x86SSERegType from, u8 imm8 )
{ {
if (to > 7 || from > 7) Rex(1, to >> 3, 0, from >> 3); if (to > 7 || from > 7) Rex(1, to >> 3, 0, from >> 3);
write16<I>( 0xc40f ); write16( 0xc40f );
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
write8<I>( imm8 ); write8( imm8 );
} }
emitterT void ePSHUFWRtoR(x86MMXRegType to, x86MMXRegType from, u8 imm8) emitterT void PSHUFWRtoR(x86MMXRegType to, x86MMXRegType from, u8 imm8)
{ {
write16<I>(0x700f); write16(0x700f);
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
write8<I>(imm8); write8(imm8);
} }
emitterT void ePSHUFWMtoR(x86MMXRegType to, uptr from, u8 imm8) emitterT void PSHUFWMtoR(x86MMXRegType to, uptr from, u8 imm8)
{ {
write16<I>( 0x700f ); write16( 0x700f );
ModRM<I>( 0, to, DISP32 ); ModRM( 0, to, DISP32 );
write32<I>( MEMADDR(from, 4) ); write32( MEMADDR(from, 4) );
write8<I>(imm8); write8(imm8);
} }
emitterT void eMASKMOVQRtoR(x86MMXRegType to, x86MMXRegType from) emitterT void MASKMOVQRtoR(x86MMXRegType to, x86MMXRegType from)
{ {
write16<I>(0xf70f); write16(0xf70f);
ModRM<I>( 3, to, from ); ModRM( 3, to, from );
} }

1284
pcsx2/x86/ix86/ix86_sse.inl
View File

File diff suppressed because it is too large Load Diff