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Add a few structs and defines to IopHw.h 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2535 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42 2010-01-29 02:38:31 +00:00
parent c2c48b91c5
commit bc3b572690
2 changed files with 57 additions and 10 deletions
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47
pcsx2/IopHw.h
View File

@ -205,6 +205,53 @@ enum IOPCountRegs
}
#endif
struct dma_mbc
{
u32 madr;
u32 bcr;
u32 chcr;
u16 bcr_lower() const
{
return (u16)(bcr);
}
u16 bcr_upper() const
{
return (bcr >> 16);
}
};
struct dma_mbct
{
u32 madr;
u32 bcr;
u32 chcr;
u32 tadr;
u16 bcr_lower() const
{
return (u16)(bcr);
}
u16 bcr_upper() const
{
return (bcr >> 16);
}
};
#define hw_dma0 (*(dma_mbc*) &psxH[0x1080])
#define hw_dma1 (*(dma_mbc*) &psxH[0x1090])
#define hw_dma2 (*(dma_mbct*)&psxH[0x10a0])
#define hw_dma3 (*(dma_mbc*) &psxH[0x10b0])
#define hw_dma4 (*(dma_mbct*)&psxH[0x10c0])
#define hw_dma6 (*(dma_mbc*) &psxH[0x10e0])
#define hw_dma7 (*(dma_mbc*) &psxH[0x1500])
#define hw_dma8 (*(dma_mbc*) &psxH[0x1510])
#define hw_dma9 (*(dma_mbct*)&psxH[0x1520])
#define hw_dma10 (*(dma_mbc*) &psxH[0x1530])
#define hw_dma11 (*(dma_mbc*) &psxH[0x1540])
#define hw_dma12 (*(dma_mbc*) &psxH[0x1550])
#define hw_dma(x) hw_dma##x
#define HW_DMA0_MADR (psxHu32(0x1080)) // MDEC in DMA
#define HW_DMA0_BCR (psxHu32(0x1084))
#define HW_DMA0_CHCR (psxHu32(0x1088))

20
pcsx2/Sif.cpp
View File

@ -112,8 +112,8 @@ static __forceinline bool SifIOPWrite(int &psxCycles)
//{
SIF_LOG("+++++++++++ %lX of %lX", writeSize, sif0.counter);
sif0.fifo.write((u32*)iopPhysMem(HW_DMA9_MADR), writeSize);
HW_DMA9_MADR += writeSize << 2;
sif0.fifo.write((u32*)iopPhysMem(hw_dma(9).madr), writeSize);
hw_dma(9).madr += writeSize << 2;
psxCycles += (writeSize >> 2) * BIAS; // fixme : should be >> 4
sif0.counter -= writeSize;
//}
@ -133,9 +133,9 @@ static __forceinline bool SifIOPRead(int &psxCycles)
//{
SIF_LOG(" IOP SIF doing transfer %04X to %08X", readSize, HW_DMA10_MADR);
sif1.fifo.read((u32*)iopPhysMem(HW_DMA10_MADR), readSize);
psxCpu->Clear(HW_DMA10_MADR, readSize);
HW_DMA10_MADR += readSize << 2;
sif1.fifo.read((u32*)iopPhysMem(hw_dma(10).madr), readSize);
psxCpu->Clear(hw_dma(10).madr, readSize);
hw_dma(10).madr += readSize << 2;
psxCycles += readSize >> 2; // fixme: should be / 16
sif1.counter -= readSize;
//}
@ -251,12 +251,12 @@ static __forceinline bool SIFEEWriteTag()
static __forceinline bool SIFIOPWriteTag()
{
// Process DMA tag at HW_DMA9_TADR
sif0.data = *(sifData *)iopPhysMem(HW_DMA9_TADR);
sif0.data = *(sifData *)iopPhysMem(hw_dma(9).tadr);
sif0.data.words = (sif0.data.words + 3) & 0xfffffffc; // Round up to nearest 4.
sif0.fifo.write((u32*)iopPhysMem(HW_DMA9_TADR + 8), 4);
sif0.fifo.write((u32*)iopPhysMem(hw_dma(9).tadr + 8), 4);
HW_DMA9_TADR += 16; ///HW_DMA9_MADR + 16 + sif0.sifData.words << 2;
HW_DMA9_MADR = sif0.data.data & 0xFFFFFF;
hw_dma(9).tadr += 16; ///hw_dma(9).madr + 16 + sif0.sifData.words << 2;
hw_dma(9).madr = sif0.data.data & 0xFFFFFF;
sif0.counter = sif0.data.words & 0xFFFFFF;
SIF_LOG(" SIF0 Tag: madr=%lx, tadr=%lx, counter=%lx (%08X_%08X)", HW_DMA9_MADR, HW_DMA9_TADR, sif0.counter, sif0.data.words, sif0.data.data);
@ -272,7 +272,7 @@ static __forceinline bool SIFIOPReadTag()
sif1.data.data & 0xffffff, sif1.data.words, DMA_TAG(sif1.data.data).ID,
DMA_TAG(sif1.data.data).IRQ);
HW_DMA10_MADR = sif1.data.data & 0xffffff;
hw_dma(10).madr = sif1.data.data & 0xffffff;
sif1.counter = sif1.data.words;
return true;
}