mirror of https://github.com/PCSX2/pcsx2.git
Merge pull request #891 from ssakash/MicroVU_branch_addr
MicroVU: Replace BranchAddr macro with an Inline function
This commit is contained in:
refractionpcsx2
commit
bbd74e5a7e
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@ -209,7 +209,7 @@ void normBranch(mV, microFlagCycles& mFC) {
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xForwardJump32 eJMP(Jcc_Zero);
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xOR(ptr32[&VU0.VI[REG_VPU_STAT].UL], (isVU1 ? 0x200 : 0x2));
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xOR(ptr32[&mVU.regs().flags], VUFLAG_INTCINTERRUPT);
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iPC = branchAddr/4;
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iPC = branchAddr(mVU)/4;
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mVUDTendProgram(mVU, &mFC, 1);
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eJMP.SetTarget();
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iPC = tempPC;
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@ -221,7 +221,7 @@ void normBranch(mV, microFlagCycles& mFC) {
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xForwardJump32 eJMP(Jcc_Zero);
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xOR(ptr32[&VU0.VI[REG_VPU_STAT].UL], (isVU1 ? 0x400 : 0x4));
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xOR(ptr32[&mVU.regs().flags], VUFLAG_INTCINTERRUPT);
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iPC = branchAddr/4;
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iPC = branchAddr(mVU)/4;
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mVUDTendProgram(mVU, &mFC, 1);
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eJMP.SetTarget();
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iPC = tempPC;
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@ -230,14 +230,14 @@ void normBranch(mV, microFlagCycles& mFC) {
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if(mVUlow.badBranch)
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DevCon.Warning("End on evil Unconditional branch! - Not implemented! - If game broken report to PCSX2 Team");
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iPC = branchAddr/4;
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iPC = branchAddr(mVU)/4;
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mVUendProgram(mVU, &mFC, 1);
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return;
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}
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if(mVUlow.badBranch)
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{
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u32 badBranchAddr = branchAddr+8;
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u32 badBranchAddr = branchAddr(mVU)+8;
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incPC(3);
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if(mVUlow.branch == 2 || mVUlow.branch == 10) //Delay slot branch needs linking
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{
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@ -252,7 +252,7 @@ void normBranch(mV, microFlagCycles& mFC) {
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// Normal Branch
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mVUsetupBranch(mVU, mFC);
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normBranchCompile(mVU, branchAddr);
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normBranchCompile(mVU, branchAddr(mVU));
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}
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//Messy handler warning!!
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@ -266,7 +266,7 @@ void condJumpProcessingEvil(mV, microFlagCycles& mFC, int JMPcc) {
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u32 badBranchAddr;
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iPC = bPC-2;
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setCode();
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badBranchAddr = branchAddr;
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badBranchAddr = branchAddr(mVU);
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xCMP(ptr16[&mVU.branch], 0);
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@ -314,7 +314,7 @@ void condBranch(mV, microFlagCycles& mFC, int JMPcc) {
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xJMP(mVU.exitFunct);
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tJMP.SetTarget();
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incPC(-4); // Go Back to Branch Opcode to get branchAddr
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iPC = branchAddr/4;
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iPC = branchAddr(mVU)/4;
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xMOV(ptr32[&mVU.regs().VI[REG_TPC].UL], xPC);
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xJMP(mVU.exitFunct);
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eJMP.SetTarget();
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@ -335,7 +335,7 @@ void condBranch(mV, microFlagCycles& mFC, int JMPcc) {
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xJMP(mVU.exitFunct);
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dJMP.SetTarget();
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incPC(-4); // Go Back to Branch Opcode to get branchAddr
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iPC = branchAddr/4;
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iPC = branchAddr(mVU)/4;
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xMOV(ptr32[&mVU.regs().VI[REG_TPC].UL], xPC);
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xJMP(mVU.exitFunct);
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eJMP.SetTarget();
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@ -355,7 +355,7 @@ void condBranch(mV, microFlagCycles& mFC, int JMPcc) {
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xJMP(mVU.exitFunct);
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eJMP.SetTarget();
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incPC(-4); // Go Back to Branch Opcode to get branchAddr
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iPC = branchAddr/4;
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iPC = branchAddr(mVU)/4;
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xMOV(ptr32[&mVU.regs().VI[REG_TPC].UL], xPC);
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xJMP(mVU.exitFunct);
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return;
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@ -380,7 +380,7 @@ void condBranch(mV, microFlagCycles& mFC, int JMPcc) {
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if (bBlock) { // Branch non-taken has already been compiled
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xJcc(xInvertCond((JccComparisonType)JMPcc), bBlock->x86ptrStart);
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incPC(-3); // Go back to branch opcode (to get branch imm addr)
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normBranchCompile(mVU, branchAddr);
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normBranchCompile(mVU, branchAddr(mVU));
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}
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else {
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s32* ajmp = xJcc32((JccComparisonType)JMPcc);
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@ -393,7 +393,7 @@ void condBranch(mV, microFlagCycles& mFC, int JMPcc) {
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iPC = bPC;
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incPC(-3); // Go back to branch opcode (to get branch imm addr)
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uptr jumpAddr = (uptr)mVUblockFetch(mVU, branchAddr, (uptr)&pBlock->pStateEnd);
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uptr jumpAddr = (uptr)mVUblockFetch(mVU, branchAddr(mVU), (uptr)&pBlock->pStateEnd);
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*ajmp = (jumpAddr - ((uptr)ajmp + 4));
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}
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}
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@ -371,7 +371,7 @@ void _mVUflagPass(mV, u32 startPC, u32 sCount, u32 found, std::vector<u32>& v) {
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if (branch >= 2) { shortBranch(); }
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else if (branch == 1) { branch = 2; }
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if (mVUbranch) { branch = ((mVUbranch>8)?(5):((mVUbranch<3)?3:4)); incPC(-1); aBranchAddr = branchAddr; incPC(1); mVUbranch = 0; }
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if (mVUbranch) { branch = ((mVUbranch>8)?(5):((mVUbranch<3)?3:4)); incPC(-1); aBranchAddr = branchAddr(mVU); incPC(1); mVUbranch = 0; }
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incPC(1);
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if ((mVUregs.needExactMatch&7)==7) break;
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}
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@ -405,8 +405,8 @@ void mVUsetFlagInfo(mV) {
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int ffOpt = doFullFlagOpt;
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if (mVUbranch <= 2) { // B/BAL
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incPC(-1);
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mVUflagPass (mVU, branchAddr);
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checkFFblock(mVU, branchAddr, ffOpt);
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mVUflagPass (mVU, branchAddr(mVU));
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checkFFblock(mVU, branchAddr(mVU), ffOpt);
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incPC(1);
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mVUregs.needExactMatch &= 0x7;
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@ -416,8 +416,8 @@ void mVUsetFlagInfo(mV) {
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}
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else if (mVUbranch <= 8) { // Conditional Branch
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incPC(-1); // Branch Taken
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mVUflagPass (mVU, branchAddr);
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checkFFblock(mVU, branchAddr, ffOpt);
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mVUflagPass (mVU, branchAddr(mVU));
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checkFFblock(mVU, branchAddr(mVU), ffOpt);
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int backupFlagInfo = mVUregs.needExactMatch;
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mVUregs.needExactMatch = 0;
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@ -1261,7 +1261,7 @@ void setBranchA(mP, int x, int _x_) {
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void condEvilBranch(mV, int JMPcc) {
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if (mVUlow.badBranch) {
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xMOV(ptr32[&mVU.branch], gprT1);
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xMOV(ptr32[&mVU.badBranch], branchAddrN);
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xMOV(ptr32[&mVU.badBranch], branchAddrN(mVU));
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xCMP(gprT1b, 0);
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xForwardJump8 cJMP((JccComparisonType)JMPcc);
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@ -1271,7 +1271,7 @@ void condEvilBranch(mV, int JMPcc) {
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cJMP.SetTarget();
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return;
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}
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xMOV(ptr32[&mVU.evilBranch], branchAddr);
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xMOV(ptr32[&mVU.evilBranch], branchAddr(mVU));
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xCMP(gprT1b, 0);
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xForwardJump8 cJMP((JccComparisonType)JMPcc);
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xMOV(gprT1, ptr32[&mVU.badBranch]); // Branch Not Taken
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@ -1286,11 +1286,11 @@ mVUop(mVU_B) {
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setBranchA(mX, 1, 0);
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pass1 { mVUanalyzeNormBranch(mVU, 0, false); }
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pass2 {
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if (mVUlow.badBranch) { xMOV(ptr32[&mVU.badBranch], branchAddrN); }
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if (mVUlow.evilBranch) { xMOV(ptr32[&mVU.evilBranch], branchAddr); }
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if (mVUlow.badBranch) { xMOV(ptr32[&mVU.badBranch], branchAddrN(mVU)); }
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if (mVUlow.evilBranch) { xMOV(ptr32[&mVU.evilBranch], branchAddr(mVU)); }
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mVU.profiler.EmitOp(opB);
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}
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pass3 { mVUlog("B [<a href=\"#addr%04x\">%04x</a>]", branchAddr, branchAddr); }
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pass3 { mVUlog("B [<a href=\"#addr%04x\">%04x</a>]", branchAddr(mVU), branchAddr(mVU)); }
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}
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mVUop(mVU_BAL) {
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@ -1303,11 +1303,11 @@ mVUop(mVU_BAL) {
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mVUallocVIb(mVU, gprT1, _It_);
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}
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if (mVUlow.badBranch) { xMOV(ptr32[&mVU.badBranch], branchAddrN); }
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if (mVUlow.evilBranch) { xMOV(ptr32[&mVU.evilBranch], branchAddr);}
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if (mVUlow.badBranch) { xMOV(ptr32[&mVU.badBranch], branchAddrN(mVU)); }
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if (mVUlow.evilBranch) { xMOV(ptr32[&mVU.evilBranch], branchAddr(mVU));}
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mVU.profiler.EmitOp(opBAL);
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}
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pass3 { mVUlog("BAL vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Ft_, branchAddr, branchAddr); }
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pass3 { mVUlog("BAL vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Ft_, branchAddr(mVU), branchAddr(mVU)); }
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}
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mVUop(mVU_IBEQ) {
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@ -1324,7 +1324,7 @@ mVUop(mVU_IBEQ) {
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else condEvilBranch(mVU, Jcc_Equal);
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mVU.profiler.EmitOp(opIBEQ);
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}
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pass3 { mVUlog("IBEQ vi%02d, vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Ft_, _Fs_, branchAddr, branchAddr); }
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pass3 { mVUlog("IBEQ vi%02d, vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Ft_, _Fs_, branchAddr(mVU), branchAddr(mVU)); }
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}
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mVUop(mVU_IBGEZ) {
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@ -1337,7 +1337,7 @@ mVUop(mVU_IBGEZ) {
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else condEvilBranch(mVU, Jcc_GreaterOrEqual);
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mVU.profiler.EmitOp(opIBGEZ);
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}
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pass3 { mVUlog("IBGEZ vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Fs_, branchAddr, branchAddr); }
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pass3 { mVUlog("IBGEZ vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Fs_, branchAddr(mVU), branchAddr(mVU)); }
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}
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mVUop(mVU_IBGTZ) {
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@ -1350,7 +1350,7 @@ mVUop(mVU_IBGTZ) {
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else condEvilBranch(mVU, Jcc_Greater);
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mVU.profiler.EmitOp(opIBGTZ);
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}
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pass3 { mVUlog("IBGTZ vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Fs_, branchAddr, branchAddr); }
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pass3 { mVUlog("IBGTZ vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Fs_, branchAddr(mVU), branchAddr(mVU)); }
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}
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mVUop(mVU_IBLEZ) {
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@ -1363,7 +1363,7 @@ mVUop(mVU_IBLEZ) {
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else condEvilBranch(mVU, Jcc_LessOrEqual);
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mVU.profiler.EmitOp(opIBLEZ);
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}
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pass3 { mVUlog("IBLEZ vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Fs_, branchAddr, branchAddr); }
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pass3 { mVUlog("IBLEZ vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Fs_, branchAddr(mVU), branchAddr(mVU)); }
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}
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mVUop(mVU_IBLTZ) {
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@ -1376,7 +1376,7 @@ mVUop(mVU_IBLTZ) {
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else condEvilBranch(mVU, Jcc_Less);
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mVU.profiler.EmitOp(opIBLTZ);
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}
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pass3 { mVUlog("IBLTZ vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Fs_, branchAddr, branchAddr); }
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pass3 { mVUlog("IBLTZ vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Fs_, branchAddr(mVU), branchAddr(mVU)); }
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}
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mVUop(mVU_IBNE) {
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@ -1393,7 +1393,7 @@ mVUop(mVU_IBNE) {
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else condEvilBranch(mVU, Jcc_NotEqual);
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mVU.profiler.EmitOp(opIBNE);
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}
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pass3 { mVUlog("IBNE vi%02d, vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Ft_, _Fs_, branchAddr, branchAddr); }
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pass3 { mVUlog("IBNE vi%02d, vi%02d [<a href=\"#addr%04x\">%04x</a>]", _Ft_, _Fs_, branchAddr(mVU), branchAddr(mVU)); }
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}
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void normJumpPass2(mV) {
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@ -232,20 +232,12 @@ typedef u32 (__fastcall *mVUCall)(void*, void*);
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#define shuffleSS(x) ((x==1)?(0x27):((x==2)?(0xc6):((x==4)?(0xe1):(0xe4))))
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#define clampE CHECK_VU_EXTRA_OVERFLOW
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#define varPrint(x) DevCon.WriteLn(#x " = %d", (int)x)
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#define islowerOP ((iPC & 1) == 0)
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#define blockCreate(addr) { \
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if (!mVUblocks[addr]) mVUblocks[addr] = new microBlockManager(); \
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}
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#define branchAddr ( \
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pxAssertDev((iPC & 1) == 0, "microVU: Expected Lower Op for valid branch addr."), \
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((((iPC + 2) + (_Imm11_ * 2)) & mVU.progMemMask) * 4) \
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)
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#define branchAddrN ( \
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pxAssertDev((iPC & 1) == 0, "microVU: Expected Lower Op for valid branch addr."), \
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((((iPC + 4) + (_Imm11_ * 2)) & mVU.progMemMask) * 4) \
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)
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// Fetches the PC and instruction opcode relative to the current PC. Used to rewind and
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// fast-forward the IR state while calculating VU pipeline conditions (branches, writebacks, etc)
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#define incPC(x) { iPC = ((iPC + (x)) & mVU.progMemMask); mVU.code = curI; }
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@ -255,6 +255,19 @@ static void __fc mVUwarningRegAccess(u32 prog, u32 pc) {
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Console.Error("microVU0 Warning: Accessing VU1 Regs! [%04x] [%x]", pc, prog);
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}
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static inline u32 branchAddrN(const mV)
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{
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pxAssumeDev(islowerOP, "MicroVU: Expected Lower OP code for valid branch addr.");
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return ((((iPC + 4) + (_Imm11_ * 2)) & mVU.progMemMask) * 4);
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}
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static inline u32 branchAddr(const mV)
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{
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pxAssumeDev(islowerOP, "MicroVU: Expected Lower OP code for valid branch addr.");
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return ((((iPC + 2) + (_Imm11_ * 2)) & mVU.progMemMask) * 4);
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}
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static void __fc mVUwaitMTVU() {
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if (IsDevBuild) DevCon.WriteLn("microVU0: Waiting on VU1 thread to access VU1 regs!");
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if (THREAD_VU1) vu1Thread.WaitVU();
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