mirror of https://github.com/PCSX2/pcsx2.git
microVU: minor changes
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1555 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
parent
0b6ed4bc15
commit
ba0f21463c
30
pcsx2/Hw.h
30
pcsx2/Hw.h
|
@ -85,17 +85,17 @@ enum HWaddress
|
|||
RCNT3_TARGET = 0x10001820,
|
||||
|
||||
IPU_CMD = 0x10002000,
|
||||
IPU_CTRL = 0x10002010,
|
||||
IPU_CTRL = 0x10002010,
|
||||
IPU_BP = 0x10002020,
|
||||
IPU_TOP = 0x10002030,
|
||||
|
||||
GIF_CTRL = 0x10003000,
|
||||
GIF_CTRL = 0x10003000,
|
||||
GIF_MODE = 0x10003010,
|
||||
GIF_STAT = 0x10003020,
|
||||
GIF_TAG0 = 0x10003040,
|
||||
GIF_TAG1 = 0x10003050,
|
||||
GIF_TAG2 = 0x10003060,
|
||||
GIF_TAG3 = 0x10003070,
|
||||
GIF_STAT = 0x10003020,
|
||||
GIF_TAG0 = 0x10003040,
|
||||
GIF_TAG1 = 0x10003050,
|
||||
GIF_TAG2 = 0x10003060,
|
||||
GIF_TAG3 = 0x10003070,
|
||||
GIF_CNT = 0x10003080,
|
||||
GIF_P3CNT = 0x10003090,
|
||||
GIF_P3TAG = 0x100030A0,
|
||||
|
@ -103,16 +103,16 @@ enum HWaddress
|
|||
// Vif Memory Locations
|
||||
VIF0_STAT = 0x10003800,
|
||||
VIF0_FBRST = 0x10003810,
|
||||
VIF0_ERR = 0x10003820,
|
||||
VIF0_ERR = 0x10003820,
|
||||
VIF0_MARK = 0x10003830,
|
||||
VIF0_CYCLE = 0x10003840,
|
||||
VIF0_MODE = 0x10003850,
|
||||
VIF0_NUM = 0x10003860,
|
||||
VIF0_NUM = 0x10003860,
|
||||
VIF0_MASK = 0x10003870,
|
||||
VIF0_CODE = 0x10003880,
|
||||
VIF0_ITOPS = 0x10003890,
|
||||
VIF0_ITOP = 0x100038d0,
|
||||
VIF0_TOP = 0x100038e0,
|
||||
VIF0_TOP = 0x100038e0,
|
||||
VIF0_R0 = 0x10003900,
|
||||
VIF0_R1 = 0x10003910,
|
||||
VIF0_R2 = 0x10003920,
|
||||
|
@ -124,11 +124,11 @@ enum HWaddress
|
|||
|
||||
VIF1_STAT = 0x10003c00,
|
||||
VIF1_FBRST = 0x10003c10,
|
||||
VIF1_ERR = 0x10003c20,
|
||||
VIF1_ERR = 0x10003c20,
|
||||
VIF1_MARK = 0x10003c30,
|
||||
VIF1_CYCLE = 0x10003c40,
|
||||
VIF1_MODE = 0x10003c50,
|
||||
VIF1_NUM = 0x10003c60,
|
||||
VIF1_NUM = 0x10003c60,
|
||||
VIF1_MASK = 0x10003c70,
|
||||
VIF1_CODE = 0x10003c80,
|
||||
VIF1_ITOPS = 0x10003c90,
|
||||
|
@ -136,7 +136,7 @@ enum HWaddress
|
|||
VIF1_OFST = 0x10003cb0,
|
||||
VIF1_TOPS = 0x10003cc0,
|
||||
VIF1_ITOP = 0x10003cd0,
|
||||
VIF1_TOP = 0x10003ce0,
|
||||
VIF1_TOP = 0x10003ce0,
|
||||
VIF1_R0 = 0x10003d00,
|
||||
VIF1_R1 = 0x10003d10,
|
||||
VIF1_R2 = 0x10003d20,
|
||||
|
@ -148,7 +148,7 @@ enum HWaddress
|
|||
|
||||
VIF0_FIFO = 0x10004000,
|
||||
VIF1_FIFO = 0x10005000,
|
||||
GIF_FIFO = 0x10006000,
|
||||
GIF_FIFO = 0x10006000,
|
||||
|
||||
IPUout_FIFO = 0x10007000,
|
||||
IPUin_FIFO = 0x10007010,
|
||||
|
@ -242,7 +242,7 @@ enum HWaddress
|
|||
SBUS_F260 = 0x1000F260,
|
||||
|
||||
MCH_RICM = 0x1000F430,
|
||||
MCH_DRD = 0x1000F440,
|
||||
MCH_DRD = 0x1000F440,
|
||||
|
||||
DMAC_ENABLER = 0x1000F520,
|
||||
DMAC_ENABLEW = 0x1000F590,
|
||||
|
|
|
@ -108,7 +108,7 @@ microVUt(void) mVUclose(mV) {
|
|||
if (mVU->prog.prog) {
|
||||
for (int i = 0; i <= mVU->prog.max; i++) {
|
||||
for (u32 j = 0; j < (mVU->progSize / 2); j++) {
|
||||
microBlockManager::Delete(mVU->prog.prog[i].block[j]);
|
||||
safe_delete(mVU->prog.prog[i].block[j]);
|
||||
}
|
||||
}
|
||||
safe_aligned_free(mVU->prog.prog);
|
||||
|
@ -141,7 +141,7 @@ microVUf(void) mVUclearProg(int progIndex) {
|
|||
mVUprogI.ranges.total = -1;
|
||||
}
|
||||
for (u32 i = 0; i < (mVU->progSize / 2); i++) {
|
||||
microBlockManager::Delete(mVUprogI.block[i]);
|
||||
safe_delete(mVUprogI.block[i]);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -39,12 +39,6 @@ private:
|
|||
int listI;
|
||||
|
||||
public:
|
||||
// Use instead of normal 'delete'
|
||||
static void Delete(microBlockManager* &dead) {
|
||||
if (!dead) return;
|
||||
dead->~microBlockManager();
|
||||
safe_delete(dead);
|
||||
}
|
||||
microBlockManager() {
|
||||
listI = -1;
|
||||
blockList.block = NULL;
|
||||
|
|
|
@ -99,8 +99,8 @@ microVUt(void) mVUallocCFLAGb(mV, int reg, int fInstance) {
|
|||
//------------------------------------------------------------------
|
||||
|
||||
microVUt(void) mVUallocVIa(mV, int GPRreg, int _reg_) {
|
||||
if (!_reg_) { XOR32RtoR(GPRreg, GPRreg); }
|
||||
else { MOVZX32Rm16toR(GPRreg, gprR, (_reg_ - 9) * 16); }
|
||||
if (!_reg_) { XOR32RtoR(GPRreg, GPRreg); }
|
||||
else { MOVZX32Rm16toR(GPRreg, gprR, (_reg_ - 9) * 16); }
|
||||
}
|
||||
|
||||
microVUt(void) mVUallocVIb(mV, int GPRreg, int _reg_) {
|
||||
|
@ -109,8 +109,8 @@ microVUt(void) mVUallocVIb(mV, int GPRreg, int _reg_) {
|
|||
MOV32RtoM((uptr)&mVU->VIbackup, gprR);
|
||||
MOV32ItoR(gprR, Roffset);
|
||||
}
|
||||
if (_reg_ == 0) { return; }
|
||||
else if (_reg_ < 16) { MOV16RtoRm(gprR, GPRreg, (_reg_ - 9) * 16); }
|
||||
if (_reg_ == 0) { return; }
|
||||
else if (_reg_ < 16) { MOV16RtoRm(gprR, GPRreg, (_reg_ - 9) * 16); }
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
|
|
|
@ -299,14 +299,13 @@ microVUt(void) mVUaddrFix(mV, int gprReg) {
|
|||
}
|
||||
|
||||
// Backup Volatile Regs (EAX, ECX, EDX, MM0~7, XMM0~7, are all volatile according to 32bit Win/Linux ABI)
|
||||
microVUt(void) mVUbackupRegs(mV) {
|
||||
//SSE_MOVAPS_XMM_to_M128((uptr)&mVU->regs->ACC.UL[0], xmmACC);
|
||||
microVUt(void) mVUbackupRegs(microVU* mVU) {
|
||||
mVU->regAlloc->flushAll();
|
||||
SSE_MOVAPS_XMM_to_M128((uptr)&mVU->xmmPQb[0], xmmPQ);
|
||||
}
|
||||
|
||||
// Restore Volatile Regs
|
||||
microVUt(void) mVUrestoreRegs(mV) {
|
||||
//SSE_MOVAPS_M128_to_XMM(xmmACC, (uptr)&mVU->regs->ACC.UL[0]);
|
||||
microVUt(void) mVUrestoreRegs(microVU* mVU) {
|
||||
SSE_MOVAPS_M128_to_XMM(xmmPQ, (uptr)&mVU->xmmPQb[0]);
|
||||
MOV32ItoR(gprR, Roffset); // Restore gprR
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue