ShuriZma
/
pcsx2
mirror of https://github.com/PCSX2/pcsx2.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Change the qwc overflow into pad area handling to only include IPU. 

This fixes a few games that had their GS or VIF transfer chopped of otherwise.
(Check games with previously missing graphics, or just plain crashes.)

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2778 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
ramapcsx2 2010-03-26 14:22:04 +00:00
parent 6346c8f061
commit b9afcac346
2 changed files with 19 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
pcsx2/HwWrite.cpp
View File

@ -41,7 +41,7 @@ static __forceinline void DmaExec8( void (*func)(), u32 mem, u8 value )
// Upper 16bits of QWC should not be written since QWC is 16bits in size. // Upper 16bits of QWC should not be written since QWC is 16bits in size.
if ((psHu32(qwcRegister) >> 16) != 0) if ((psHu32(qwcRegister) >> 16) != 0)
{ {
DMA_LOG("DMA QWC (%x) upper 16bits set to %x\n", qwcRegister, psHu32(qwcRegister) >> 16); DevCon.Warning("DmaExec8 DMA QWC (%x) upper 16bits set to %x\n", qwcRegister, psHu32(qwcRegister) >> 16);
psHu32(qwcRegister) = 0; psHu32(qwcRegister) = 0;
} }
@ -71,11 +71,12 @@ static __forceinline void DmaExec16( void (*func)(), u32 mem, u16 value )
// Note: pad is the padding right above qwc, so we're testing whether qwc // Note: pad is the padding right above qwc, so we're testing whether qwc
// has overflowed into pad. // has overflowed into pad.
// Note2: May be only needed for IPU which has this handling in IPU.cpp now. (Fixes GS transfers)
if (reg->pad != 0) if (reg->pad != 0)
{ {
DevCon.Warning(L"DMA QWC (%s) upper 16 bits set to %x\n", DevCon.Warning(L"DmaExec16 DMA QWC (%s) upper 16 bits set to %x\n",
ChcrName(mem), reg->pad); ChcrName(mem), reg->pad);
reg->qwc = reg->pad = 0; //reg->qwc = reg->pad = 0;
} }
psHu16(mem) = chcr.lower(); psHu16(mem) = chcr.lower();
@ -106,11 +107,12 @@ static void DmaExec( void (*func)(), u32 mem, u32 value )
// Note: pad is the padding right above qwc, so we're testing whether qwc // Note: pad is the padding right above qwc, so we're testing whether qwc
// has overflowed into pad. // has overflowed into pad.
// Note2: May be only needed for IPU which has this handling in IPU.cpp now. (Fixes GS transfers)
if (reg->pad != 0) if (reg->pad != 0)
{ {
DevCon.Warning(L"DMA QWC (%s) upper 16 bits set to %x\n", DevCon.Warning(L"DmaExec32 DMA QWC (%s) upper 16 bits set to %x\n",
ChcrName(mem), reg->pad); ChcrName(mem), reg->pad);
reg->qwc = reg->pad = 0; //reg->qwc = reg->pad = 0;
//return; //return;
} }

24
pcsx2/IPU/IPU.cpp
View File

@ -1327,12 +1327,12 @@ int IPU1dma()
// Note: pad is the padding right above qwc, so we're testing whether qwc // Note: pad is the padding right above qwc, so we're testing whether qwc
// has overflowed into pad. // has overflowed into pad.
// if (ipu1dma->pad != 0) if (ipu1dma->pad != 0)
// { {
// DevCon.Warning(L"IPU1dma's upper 16 bits set to %x\n", ipu1dma->pad); DevCon.Warning(L"IPU1dma's upper 16 bits set to %x\n", ipu1dma->pad);
// //ipu1dma->qwc = ipu1dma->pad = 0; ipu1dma->qwc = ipu1dma->pad = 0;
// return 0; //return 0;
// } }
pxAssert(!ipu1dma->chcr.TTE); pxAssert(!ipu1dma->chcr.TTE);
@ -1485,12 +1485,12 @@ int IPU0dma()
// Note: pad is the padding right above qwc, so we're testing whether qwc // Note: pad is the padding right above qwc, so we're testing whether qwc
// has overflowed into pad. // has overflowed into pad.
// if (ipu0dma->pad != 0) if (ipu0dma->pad != 0)
// { {
// DevCon.Warning(L"IPU0dma's upper 16 bits set to %x\n", ipu0dma->pad); DevCon.Warning(L"IPU0dma's upper 16 bits set to %x\n", ipu0dma->pad);
// //ipu0dma->qwc = ipu0dma->pad = 0; ipu0dma->qwc = ipu0dma->pad = 0;
// return 0; //return 0;
// } }
if ((!(ipu0dma->chcr.STR) || (cpuRegs.interrupt & (1 << DMAC_FROM_IPU))) || (ipu0dma->qwc == 0)) if ((!(ipu0dma->chcr.STR) || (cpuRegs.interrupt & (1 << DMAC_FROM_IPU))) || (ipu0dma->qwc == 0))
return 0; return 0;