mirror of https://github.com/PCSX2/pcsx2.git
Major Fix: Found and fixed a big vmhack / COP0 bug. This should fix several games, including those in Issue 49, Issue 58, and possibly Issue 59 as well (testing of those issues and a confirmation is needed).
Code cleanup to iHw.c : Removed some rampant abuse of macros and quite a bit of unnecessary code bloat. git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@393 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
Jake.Stine
Gregory Hainaut
parent
e8366b171a
commit
b8e4a35de6
13
pcsx2/COP0.c
13
pcsx2/COP0.c
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@ -134,8 +134,7 @@ void MTC0() {
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}
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int CPCOND0() {
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if(((psHu16(DMAC_STAT) & psHu16(DMAC_PCR)) & 0x3ff) == (psHu16(DMAC_PCR) & 0x3ff)) return 1;
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else return 0;
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return (((psHu16(DMAC_STAT) & psHu16(DMAC_PCR)) & 0x3ff) == (psHu16(DMAC_PCR) & 0x3ff));
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}
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//#define CPCOND0 1
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@ -147,10 +146,12 @@ int CPCOND0() {
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void BC0F() {
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BC0(== 0);
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COP0_LOG( "COP0 > BC0F\n" );
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}
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void BC0T() {
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BC0(== 1);
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COP0_LOG( "COP0 > BC0T\n" );
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}
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#define BC0L(cond) \
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@ -160,10 +161,12 @@ void BC0T() {
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void BC0FL() {
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BC0L(== 0);
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COP0_LOG( "COP0 > BC0FL\n" );
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}
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void BC0TL() {
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BC0L(== 1);
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COP0_LOG( "COP0 > BCOTL\n" );
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}
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void TLBR() {
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@ -176,7 +179,7 @@ void TLBR() {
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// if( !bExecBIOS )
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// __Log("TLBR %d\n", cpuRegs.CP0.n.Index&0x1f);
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SysPrintf("COP0_TLBR\n");
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COP0_LOG("COP0 > TLBR\n");
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cpuRegs.CP0.n.PageMask = tlb[i].PageMask;
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cpuRegs.CP0.n.EntryHi = tlb[i].EntryHi&~(tlb[i].PageMask|0x1f00);
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cpuRegs.CP0.n.EntryLo0 = (tlb[i].EntryLo0&~1)|((tlb[i].EntryHi>>12)&1);
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@ -219,6 +222,8 @@ void WriteTLB(int i) {
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u32 mask, addr;
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u32 saddr, eaddr;
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COP0_LOG( "COP0 > WriteTLB" );
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tlb[i].PageMask = cpuRegs.CP0.n.PageMask;
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tlb[i].EntryHi = cpuRegs.CP0.n.EntryHi;
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tlb[i].EntryLo0 = cpuRegs.CP0.n.EntryLo0;
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@ -340,7 +345,7 @@ void DI() {
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if (cpuRegs.CP0.n.Status.b._EDI || cpuRegs.CP0.n.Status.b.EXL ||
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cpuRegs.CP0.n.Status.b.ERL || (cpuRegs.CP0.n.Status.b.KSU == 0)) {
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cpuRegs.CP0.n.Status.b.EIE = 0;
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UpdateCP0Status();
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//UpdateCP0Status(); // ints are disabled so checking for them is kinda silly...
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}
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}
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@ -1160,7 +1160,7 @@ __forceinline void intcInterrupt() {
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}
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// fixme: dead/unused code?
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void dmacTestInterrupt() {
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/*void dmacTestInterrupt() {
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cpuRegs.interrupt &= ~(1 << 31);
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if ((cpuRegs.CP0.n.Status.val & 0x800) != 0x800) return;
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@ -1168,7 +1168,7 @@ void dmacTestInterrupt() {
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psHu16(0xe010) & 0x8000) == 0) return;
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if((psHu32(DMAC_CTRL) & 0x1) == 0) return;
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}
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}*/
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__forceinline void dmacInterrupt()
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{
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@ -414,6 +414,11 @@ static __forceinline void _cpuTestTIMR()
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cpuRegs.CP0.n.Count += cpuRegs.cycle-s_iLastCOP0Cycle;
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s_iLastCOP0Cycle = cpuRegs.cycle;
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// fixme: this looks like a hack to make up for the fact that the TIMR
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// doesn't yet have a proper mecahnism for setting itself up on a nextBranchCycle.
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// A proper fix would schedule the TIMR to trigger at a specific cycle anytime
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// the Count or Compare registers are modified.
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if ( (cpuRegs.CP0.n.Status.val & 0x8000) &&
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cpuRegs.CP0.n.Count >= cpuRegs.CP0.n.Compare && cpuRegs.CP0.n.Count < cpuRegs.CP0.n.Compare+1000 ) {
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SysPrintf("timr intr: %x, %x\n", cpuRegs.CP0.n.Count, cpuRegs.CP0.n.Compare);
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@ -440,7 +445,7 @@ static __forceinline void _cpuTestPERF()
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// Maximum wait between branches. Lower values provide a tighter synchronization between
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// the EE and the IOP, but incur more execution overhead.
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#define EE_WAIT_CYCLE 512 // 2048 is still unstable due to COP0
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#define EE_WAIT_CYCLE 1024 // 2048 is probably stable now, but starting low first
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// if cpuRegs.cycle is greater than this cycle, should check cpuBranchTest for updates
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u32 g_nextBranchCycle = 0;
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@ -463,9 +468,9 @@ static __forceinline void _cpuBranchTest_Shared()
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if( cpuTestCycle( nextsCounter, nextCounter ) )
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{
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rcntUpdate();
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_cpuTestPERF();
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}
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_cpuTestPERF();
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_cpuTestTIMR();
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//#ifdef CPU_LOG
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@ -496,7 +501,7 @@ static __forceinline void _cpuBranchTest_Shared()
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if( iopBranchAction )
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{
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//if( EEsCycle < -500 )
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// SysPrintf( " IOP ahead by: %d\n", -EEsCycle );
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// SysPrintf( " IOP ahead by: %d cycles\n", -EEsCycle );
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psxCpu->ExecuteBlock();
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}
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@ -516,13 +516,13 @@ __forceinline void sif1Interrupt() {
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__forceinline void EEsif0Interrupt() {
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sif0dma->chcr &= ~0x100;
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hwDmacIrq(5);
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hwDmacIrq(DMAC_SIF0);
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cpuRegs.interrupt &= ~(1 << 5);
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}
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__forceinline void EEsif1Interrupt() {
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hwDmacIrq(6);
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hwDmacIrq(DMAC_SIF1);
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sif1dma->chcr &= ~0x100;
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cpuRegs.interrupt &= ~(1 << 6);
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@ -578,7 +578,6 @@ _inline void dmaSIF1() {
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}
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// fixme: Unused code
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_inline void dmaSIF2() {
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SIF_LOG("dmaSIF2 chcr = %lx, madr = %lx, qwc = %lx\n",
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sif2dma->chcr, sif2dma->madr, sif2dma->qwc);
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@ -16,6 +16,12 @@
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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// Important Note to Future Developers:
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// None of the COP0 instructions are really critical performance items,
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// so don't waste time converting any more them into recompiled code
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// unless it can make them nicely compact. Calling the C versions will
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// suffice.
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#if !(defined(_MSC_VER) && defined(PCSX2_NORECBUILD))
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#include "Common.h"
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@ -47,8 +53,6 @@ REC_SYS(EI);
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#else
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////////////////////////////////////////////////////
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//REC_SYS(MTC0);
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////////////////////////////////////////////////////
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REC_SYS(BC0F);
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////////////////////////////////////////////////////
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@ -65,12 +69,6 @@ REC_SYS(TLBWI);
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REC_SYS(TLBWR);
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////////////////////////////////////////////////////
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REC_SYS(TLBP);
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////////////////////////////////////////////////////
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REC_SYS(ERET);
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////////////////////////////////////////////////////
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REC_SYS(DI);
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////////////////////////////////////////////////////
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REC_SYS(EI);
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////////////////////////////////////////////////////
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extern u32 s_iLastCOP0Cycle;
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@ -329,6 +327,47 @@ void recMTC0()
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}
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}
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void recERET()
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{
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// Must branch immediately after ERET!
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branch = 2;
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MOV32ItoM( (uptr)&cpuRegs.code, (u32)cpuRegs.code );
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MOV32MtoR( ECX, (uptr)&cpuRegs.cycle );
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MOV32ItoM( (uptr)&cpuRegs.pc, (u32)pc );
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MOV32RtoM( (uptr)&g_nextBranchCycle, ECX );
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iFlushCall(FLUSH_EVERYTHING);
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CALLFunc( (uptr)ERET );
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}
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void recEI()
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{
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// Must branch immediately after enabling ints!
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branch = 2;
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MOV32ItoM( (uptr)&cpuRegs.code, (u32)cpuRegs.code );
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MOV32MtoR( ECX, (uptr)&cpuRegs.cycle );
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MOV32ItoM( (uptr)&cpuRegs.pc, (u32)pc );
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MOV32RtoM( (uptr)&g_nextBranchCycle, ECX );
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iFlushCall(FLUSH_EVERYTHING);
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CALLFunc( (uptr)EI );
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}
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void recDI()
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{
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// No need to branch after disabling interrupts...
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//branch = 2;
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//MOV32ItoM( (uptr)&cpuRegs.code, (u32)cpuRegs.code );
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MOV32MtoR( ECX, (uptr)&cpuRegs.cycle );
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//MOV32ItoM( (uptr)&cpuRegs.pc, (u32)pc );
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MOV32RtoM( (uptr)&g_nextBranchCycle, ECX );
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iFlushCall(FLUSH_EVERYTHING);
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CALLFunc( (uptr)DI );
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}
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/*void rec(COP0) {
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}
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@ -354,11 +393,7 @@ void rec(TLBWR) {
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}
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void rec(TLBP) {
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}
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void rec(ERET) {
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}
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*/
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}*/
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#endif
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306
pcsx2/x86/iHw.c
306
pcsx2/x86/iHw.c
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@ -455,36 +455,38 @@ void hwConstRead128(u32 mem, int xmmreg) {
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}
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// when writing imm
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#define recDmaExecI8(name, num) { \
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MOV8ItoM((uptr)&PS2MEM_HW[(mem) & 0xffff], g_cpuConstRegs[(mmreg>>16)&0x1f].UL[0]); \
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if( g_cpuConstRegs[(mmreg>>16)&0x1f].UL[0] & 1 ) { \
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TEST8ItoM((uptr)&PS2MEM_HW[DMAC_CTRL&0xffff], 1); \
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j8Ptr[6] = JZ8(0); \
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CALLFunc((uptr)dma##name); \
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x86SetJ8( j8Ptr[6] ); \
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} \
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} \
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static void recDmaExecI8(void (*name)(), u32 mem, int mmreg)
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{
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MOV8ItoM((uptr)&PS2MEM_HW[(mem) & 0xffff], g_cpuConstRegs[(mmreg>>16)&0x1f].UL[0]);
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if( g_cpuConstRegs[(mmreg>>16)&0x1f].UL[0] & 1 ) {
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TEST8ItoM((uptr)&PS2MEM_HW[DMAC_CTRL&0xffff], 1);
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j8Ptr[6] = JZ8(0);
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CALLFunc((uptr)name);
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x86SetJ8( j8Ptr[6] );
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}
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}
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#define recDmaExec8(name, num) { \
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iFlushCall(0); \
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if( IS_EECONSTREG(mmreg) ) { \
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recDmaExecI8(name, num); \
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} \
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else { \
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_eeMoveMMREGtoR(EAX, mmreg); \
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_eeWriteConstMem8((uptr)&PS2MEM_HW[(mem) & 0xffff], mmreg); \
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\
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TEST8ItoR(EAX, 1); \
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j8Ptr[5] = JZ8(0); \
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TEST8ItoM((uptr)&PS2MEM_HW[DMAC_CTRL&0xffff], 1); \
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j8Ptr[6] = JZ8(0); \
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\
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CALLFunc((uptr)dma##name); \
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\
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x86SetJ8( j8Ptr[5] ); \
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x86SetJ8( j8Ptr[6] ); \
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} \
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} \
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static void recDmaExec8(void (*name)(), u32 mem, int mmreg)
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{
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iFlushCall(0);
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if( IS_EECONSTREG(mmreg) ) {
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recDmaExecI8(name, mem, mmreg);
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}
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else {
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_eeMoveMMREGtoR(EAX, mmreg);
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_eeWriteConstMem8((uptr)&PS2MEM_HW[(mem) & 0xffff], mmreg);
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TEST8ItoR(EAX, 1);
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j8Ptr[5] = JZ8(0);
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TEST8ItoM((uptr)&PS2MEM_HW[DMAC_CTRL&0xffff], 1);
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j8Ptr[6] = JZ8(0);
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CALLFunc((uptr)name);
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x86SetJ8( j8Ptr[5] );
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x86SetJ8( j8Ptr[6] );
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}
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}
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static void PrintDebug(u8 value)
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{
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@ -536,51 +538,51 @@ void hwConstWrite8(u32 mem, int mmreg)
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CONSTWRITE_TIMERS(8)
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case 0x1000f180:
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_recPushReg(mmreg); \
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_recPushReg(mmreg);
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iFlushCall(0);
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CALLFunc((uptr)PrintDebug);
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ADD32ItoR(ESP, 4);
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break;
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case 0x10008001: // dma0 - vif0
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recDmaExec8(VIF0, 0);
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recDmaExec8(dmaVIF0, mem, mmreg);
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break;
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case 0x10009001: // dma1 - vif1
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recDmaExec8(VIF1, 1);
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recDmaExec8(dmaVIF1, mem, mmreg);
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break;
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case 0x1000a001: // dma2 - gif
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recDmaExec8(GIF, 2);
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recDmaExec8(dmaGIF, mem, mmreg);
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break;
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case 0x1000b001: // dma3 - fromIPU
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recDmaExec8(IPU0, 3);
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recDmaExec8(dmaIPU0, mem, mmreg);
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break;
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case 0x1000b401: // dma4 - toIPU
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recDmaExec8(IPU1, 4);
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recDmaExec8(dmaIPU1, mem, mmreg);
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break;
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case 0x1000c001: // dma5 - sif0
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//if (value == 0) psxSu32(0x30) = 0x40000;
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recDmaExec8(SIF0, 5);
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recDmaExec8(dmaSIF0, mem, mmreg);
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break;
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case 0x1000c401: // dma6 - sif1
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recDmaExec8(SIF1, 6);
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recDmaExec8(dmaSIF1, mem, mmreg);
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break;
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case 0x1000c801: // dma7 - sif2
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recDmaExec8(SIF2, 7);
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recDmaExec8(dmaSIF2, mem, mmreg);
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break;
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case 0x1000d001: // dma8 - fromSPR
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recDmaExec8(SPR0, 8);
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recDmaExec8(dmaSPR0, mem, mmreg);
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break;
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case 0x1000d401: // dma9 - toSPR
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recDmaExec8(SPR1, 9);
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recDmaExec8(dmaSPR1, mem, mmreg);
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break;
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case 0x1000f592: // DMAC_ENABLEW
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@ -636,79 +638,81 @@ void hwConstWrite8(u32 mem, int mmreg)
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}
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}
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#define recDmaExecI16(name, num) { \
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MOV16ItoM((uptr)&PS2MEM_HW[(mem) & 0xffff], g_cpuConstRegs[(mmreg>>16)&0x1f].UL[0]); \
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if( g_cpuConstRegs[(mmreg>>16)&0x1f].UL[0] & 0x100 ) { \
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TEST8ItoM((uptr)&PS2MEM_HW[DMAC_CTRL&0xffff], 1); \
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j8Ptr[6] = JZ8(0); \
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CALLFunc((uptr)dma##name); \
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x86SetJ8( j8Ptr[6] ); \
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} \
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} \
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static void recDmaExecI16( void (*name)(), u32 mem, int mmreg )
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{
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MOV16ItoM((uptr)&PS2MEM_HW[(mem) & 0xffff], g_cpuConstRegs[(mmreg>>16)&0x1f].UL[0]);
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if( g_cpuConstRegs[(mmreg>>16)&0x1f].UL[0] & 0x100 ) {
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TEST8ItoM((uptr)&PS2MEM_HW[DMAC_CTRL&0xffff], 1);
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j8Ptr[6] = JZ8(0);
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CALLFunc((uptr)name);
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x86SetJ8( j8Ptr[6] );
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}
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}
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#define recDmaExec16(name, num) { \
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iFlushCall(0); \
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if( IS_EECONSTREG(mmreg) ) { \
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recDmaExecI16(name, num); \
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} \
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else { \
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_eeMoveMMREGtoR(EAX, mmreg); \
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_eeWriteConstMem16((uptr)&PS2MEM_HW[(mem) & 0xffff], mmreg); \
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\
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TEST16ItoR(EAX, 0x100); \
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j8Ptr[5] = JZ8(0); \
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TEST8ItoM((uptr)&PS2MEM_HW[DMAC_CTRL&0xffff], 1); \
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j8Ptr[6] = JZ8(0); \
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\
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CALLFunc((uptr)dma##name); \
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\
|
||||
x86SetJ8( j8Ptr[5] ); \
|
||||
x86SetJ8( j8Ptr[6] ); \
|
||||
} \
|
||||
} \
|
||||
static void recDmaExec16(void (*name)(), u32 mem, int mmreg)
|
||||
{
|
||||
iFlushCall(0);
|
||||
if( IS_EECONSTREG(mmreg) ) {
|
||||
recDmaExecI16(name, mem, mmreg);
|
||||
}
|
||||
else {
|
||||
_eeMoveMMREGtoR(EAX, mmreg);
|
||||
_eeWriteConstMem16((uptr)&PS2MEM_HW[(mem) & 0xffff], mmreg);
|
||||
|
||||
TEST16ItoR(EAX, 0x100);
|
||||
j8Ptr[5] = JZ8(0);
|
||||
TEST8ItoM((uptr)&PS2MEM_HW[DMAC_CTRL&0xffff], 1);
|
||||
j8Ptr[6] = JZ8(0);
|
||||
|
||||
CALLFunc((uptr)name);
|
||||
|
||||
x86SetJ8( j8Ptr[5] );
|
||||
x86SetJ8( j8Ptr[6] );
|
||||
}
|
||||
}
|
||||
|
||||
void hwConstWrite16(u32 mem, int mmreg)
|
||||
{
|
||||
switch(mem) {
|
||||
CONSTWRITE_TIMERS(16)
|
||||
case 0x10008000: // dma0 - vif0
|
||||
recDmaExec16(VIF0, 0);
|
||||
recDmaExec16(dmaVIF0, mem, mmreg);
|
||||
break;
|
||||
|
||||
case 0x10009000: // dma1 - vif1 - chcr
|
||||
recDmaExec16(VIF1, 1);
|
||||
recDmaExec16(dmaVIF1, mem, mmreg);
|
||||
break;
|
||||
|
||||
case 0x1000a000: // dma2 - gif
|
||||
recDmaExec16(GIF, 2);
|
||||
recDmaExec16(dmaGIF, mem, mmreg);
|
||||
break;
|
||||
case 0x1000b000: // dma3 - fromIPU
|
||||
recDmaExec16(IPU0, 3);
|
||||
recDmaExec16(dmaIPU0, mem, mmreg);
|
||||
break;
|
||||
case 0x1000b400: // dma4 - toIPU
|
||||
recDmaExec16(IPU1, 4);
|
||||
recDmaExec16(dmaIPU1, mem, mmreg);
|
||||
break;
|
||||
case 0x1000c000: // dma5 - sif0
|
||||
//if (value == 0) psxSu32(0x30) = 0x40000;
|
||||
recDmaExec16(SIF0, 5);
|
||||
recDmaExec16(dmaSIF0, mem, mmreg);
|
||||
break;
|
||||
case 0x1000c002:
|
||||
//?
|
||||
break;
|
||||
case 0x1000c400: // dma6 - sif1
|
||||
recDmaExec16(SIF1, 6);
|
||||
recDmaExec16(dmaSIF1, mem, mmreg);
|
||||
break;
|
||||
case 0x1000c800: // dma7 - sif2
|
||||
recDmaExec16(SIF2, 7);
|
||||
recDmaExec16(dmaSIF2, mem, mmreg);
|
||||
break;
|
||||
case 0x1000c802:
|
||||
//?
|
||||
break;
|
||||
case 0x1000d000: // dma8 - fromSPR
|
||||
recDmaExec16(SPR0, 8);
|
||||
recDmaExec16(dmaSPR0, mem, mmreg);
|
||||
break;
|
||||
case 0x1000d400: // dma9 - toSPR
|
||||
recDmaExec16(SPR1, 9);
|
||||
recDmaExec16(dmaSPR1, mem, mmreg);
|
||||
break;
|
||||
case 0x1000f592: // DMAC_ENABLEW
|
||||
_eeWriteConstMem16((uptr)&PS2MEM_HW[0xf522], mmreg);
|
||||
|
|
@ -781,57 +785,59 @@ void hwConstWrite16(u32 mem, int mmreg)
|
|||
}
|
||||
|
||||
// when writing an Imm
|
||||
#define recDmaExecI(name, num) { \
|
||||
u32 c = g_cpuConstRegs[(mmreg>>16)&0x1f].UL[0]; \
|
||||
/* Keep the old tag if in chain mode and hw doesnt set it*/ \
|
||||
if( (c & 0xc) == 0x4 && (c&0xffff0000) == 0 ) { \
|
||||
MOV16ItoM((uptr)&PS2MEM_HW[(mem) & 0xffff], c); \
|
||||
} \
|
||||
else MOV32ItoM((uptr)&PS2MEM_HW[(mem) & 0xffff], c); \
|
||||
if( c & 0x100 ) { \
|
||||
TEST8ItoM((uptr)&PS2MEM_HW[DMAC_CTRL&0xffff], 1); \
|
||||
j8Ptr[6] = JZ8(0); \
|
||||
CALLFunc((uptr)dma##name); \
|
||||
x86SetJ8( j8Ptr[6] ); \
|
||||
} \
|
||||
} \
|
||||
|
||||
#define recDmaExec(name, num) { \
|
||||
iFlushCall(0); \
|
||||
if( IS_EECONSTREG(mmreg) ) { \
|
||||
recDmaExecI(name, num); \
|
||||
} \
|
||||
else { \
|
||||
_eeMoveMMREGtoR(EAX, mmreg); \
|
||||
TEST32ItoR(EAX, 0xffff0000); \
|
||||
j8Ptr[6] = JNZ8(0); \
|
||||
MOV32RtoR(ECX, EAX); \
|
||||
AND32ItoR(ECX, 0xc); \
|
||||
CMP32ItoR(ECX, 4); \
|
||||
j8Ptr[7] = JNE8(0); \
|
||||
if( IS_XMMREG(mmreg) || IS_MMXREG(mmreg) ) { \
|
||||
MOV16RtoM((uptr)&PS2MEM_HW[(mem) & 0xffff], EAX); \
|
||||
} \
|
||||
else { \
|
||||
_eeWriteConstMem16((uptr)&PS2MEM_HW[(mem) & 0xffff], mmreg); \
|
||||
} \
|
||||
j8Ptr[8] = JMP8(0); \
|
||||
x86SetJ8(j8Ptr[6]); \
|
||||
x86SetJ8(j8Ptr[7]); \
|
||||
_eeWriteConstMem32((uptr)&PS2MEM_HW[(mem) & 0xffff], mmreg); \
|
||||
x86SetJ8(j8Ptr[8]); \
|
||||
\
|
||||
TEST16ItoR(EAX, 0x100); \
|
||||
j8Ptr[5] = JZ8(0); \
|
||||
TEST32ItoM((uptr)&PS2MEM_HW[DMAC_CTRL&0xffff], 1); \
|
||||
j8Ptr[6] = JZ8(0); \
|
||||
\
|
||||
CALLFunc((uptr)dma##name); \
|
||||
\
|
||||
x86SetJ8( j8Ptr[5] ); \
|
||||
x86SetJ8( j8Ptr[6] ); \
|
||||
} \
|
||||
} \
|
||||
static void recDmaExecI( void (*name)(), u32 mem, int mmreg )
|
||||
{
|
||||
u32 c = g_cpuConstRegs[(mmreg>>16)&0x1f].UL[0];
|
||||
/* Keep the old tag if in chain mode and hw doesnt set it*/
|
||||
if( (c & 0xc) == 0x4 && (c&0xffff0000) == 0 ) {
|
||||
MOV16ItoM((uptr)&PS2MEM_HW[(mem) & 0xffff], c);
|
||||
}
|
||||
else MOV32ItoM((uptr)&PS2MEM_HW[(mem) & 0xffff], c);
|
||||
if( c & 0x100 ) {
|
||||
TEST8ItoM((uptr)&PS2MEM_HW[DMAC_CTRL&0xffff], 1);
|
||||
j8Ptr[6] = JZ8(0);
|
||||
CALLFunc((uptr)name);
|
||||
x86SetJ8( j8Ptr[6] );
|
||||
}
|
||||
}
|
||||
|
||||
static void recDmaExec( void (*name)(), u32 mem, int mmreg )
|
||||
{
|
||||
iFlushCall(0);
|
||||
if( IS_EECONSTREG(mmreg) ) {
|
||||
recDmaExecI(name, mem, mmreg);
|
||||
}
|
||||
else {
|
||||
_eeMoveMMREGtoR(EAX, mmreg);
|
||||
TEST32ItoR(EAX, 0xffff0000);
|
||||
j8Ptr[6] = JNZ8(0);
|
||||
MOV32RtoR(ECX, EAX);
|
||||
AND32ItoR(ECX, 0xc);
|
||||
CMP32ItoR(ECX, 4);
|
||||
j8Ptr[7] = JNE8(0);
|
||||
if( IS_XMMREG(mmreg) || IS_MMXREG(mmreg) ) {
|
||||
MOV16RtoM((uptr)&PS2MEM_HW[(mem) & 0xffff], EAX);
|
||||
}
|
||||
else {
|
||||
_eeWriteConstMem16((uptr)&PS2MEM_HW[(mem) & 0xffff], mmreg);
|
||||
}
|
||||
j8Ptr[8] = JMP8(0);
|
||||
x86SetJ8(j8Ptr[6]);
|
||||
x86SetJ8(j8Ptr[7]);
|
||||
_eeWriteConstMem32((uptr)&PS2MEM_HW[(mem) & 0xffff], mmreg);
|
||||
x86SetJ8(j8Ptr[8]);
|
||||
|
||||
TEST16ItoR(EAX, 0x100);
|
||||
j8Ptr[5] = JZ8(0);
|
||||
TEST32ItoM((uptr)&PS2MEM_HW[DMAC_CTRL&0xffff], 1);
|
||||
j8Ptr[6] = JZ8(0);
|
||||
|
||||
CALLFunc((uptr)name);
|
||||
x86SetJ8( j8Ptr[5] );
|
||||
x86SetJ8( j8Ptr[6] );
|
||||
}
|
||||
}
|
||||
|
||||
#define CONSTWRITE_CALLTIMER32(name, index, bit) { \
|
||||
_recPushReg(mmreg); \
|
||||
|
|
@ -925,42 +931,42 @@ void hwConstWrite32(u32 mem, int mmreg)
|
|||
return;
|
||||
|
||||
case 0x10008000: // dma0 - vif0
|
||||
recDmaExec(VIF0, 0);
|
||||
recDmaExec(dmaVIF0, mem, mmreg);
|
||||
break;
|
||||
|
||||
case 0x10009000: // dma1 - vif1 - chcr
|
||||
recDmaExec(VIF1, 1);
|
||||
recDmaExec(dmaVIF1, mem, mmreg);
|
||||
break;
|
||||
|
||||
case 0x1000a000: // dma2 - gif
|
||||
recDmaExec(GIF, 2);
|
||||
recDmaExec(dmaGIF, mem, mmreg);
|
||||
break;
|
||||
|
||||
case 0x1000b000: // dma3 - fromIPU
|
||||
recDmaExec(IPU0, 3);
|
||||
recDmaExec(dmaIPU0, mem, mmreg);
|
||||
break;
|
||||
case 0x1000b400: // dma4 - toIPU
|
||||
recDmaExec(IPU1, 4);
|
||||
recDmaExec(dmaIPU1, mem, mmreg);
|
||||
break;
|
||||
case 0x1000c000: // dma5 - sif0
|
||||
//if (value == 0) psxSu32(0x30) = 0x40000;
|
||||
recDmaExec(SIF0, 5);
|
||||
recDmaExec(dmaSIF0, mem, mmreg);
|
||||
break;
|
||||
|
||||
case 0x1000c400: // dma6 - sif1
|
||||
recDmaExec(SIF1, 6);
|
||||
recDmaExec(dmaSIF1, mem, mmreg);
|
||||
break;
|
||||
|
||||
case 0x1000c800: // dma7 - sif2
|
||||
recDmaExec(SIF2, 7);
|
||||
recDmaExec(dmaSIF2, mem, mmreg);
|
||||
break;
|
||||
|
||||
case 0x1000d000: // dma8 - fromSPR
|
||||
recDmaExec(SPR0, 8);
|
||||
recDmaExec(dmaSPR0, mem, mmreg);
|
||||
break;
|
||||
|
||||
case 0x1000d400: // dma9 - toSPR
|
||||
recDmaExec(SPR1, 9);
|
||||
recDmaExec(dmaSPR1, mem, mmreg);
|
||||
break;
|
||||
|
||||
case 0x1000e010: // DMAC_STAT
|
||||
|
|
@ -973,11 +979,6 @@ void hwConstWrite32(u32 mem, int mmreg)
|
|||
SHR32ItoR(EAX, 16);
|
||||
XOR16RtoM((uptr)&PS2MEM_HW[0xe012], EAX);
|
||||
|
||||
// cpuRegs.CP0.n.Status.val is checked by cpuTestDMACInts.
|
||||
//MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.n.Status.val);
|
||||
//AND32ItoR(EAX, 0x10807);
|
||||
//CMP32ItoR(EAX, 0x10801);
|
||||
//j8Ptr[5] = JNE8(0);
|
||||
CALLFunc((uptr)cpuTestDMACInts);
|
||||
|
||||
//x86SetJ8( j8Ptr[5] );
|
||||
|
|
@ -985,29 +986,14 @@ void hwConstWrite32(u32 mem, int mmreg)
|
|||
|
||||
case 0x1000f000: // INTC_STAT
|
||||
_eeWriteConstMem32OP((uptr)&PS2MEM_HW[0xf000], mmreg, 2);
|
||||
// note: cpuRegs.CP0.n.Status.val conditional is done by cpuTestINTCInts.
|
||||
//MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.n.Status.val);
|
||||
//AND32ItoR(EAX, 0x10407);
|
||||
//CMP32ItoR(EAX, 0x10401);
|
||||
//j8Ptr[5] = JNE8(0);
|
||||
CALLFunc((uptr)cpuTestINTCInts);
|
||||
|
||||
//x86SetJ8( j8Ptr[5] );
|
||||
break;
|
||||
|
||||
case 0x1000f010: // INTC_MASK
|
||||
_eeMoveMMREGtoR(EAX, mmreg);
|
||||
iFlushCall(0);
|
||||
XOR16RtoM((uptr)&PS2MEM_HW[0xf010], EAX);
|
||||
|
||||
// note: cpuRegs.CP0.n.Status.val conditional is done by cpuTestINTCInts.
|
||||
//MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.n.Status.val);
|
||||
//AND32ItoR(EAX, 0x10407);
|
||||
//CMP32ItoR(EAX, 0x10401);
|
||||
//j8Ptr[5] = JNE8(0);
|
||||
CALLFunc((uptr)cpuTestINTCInts);
|
||||
|
||||
//x86SetJ8( j8Ptr[5] );
|
||||
break;
|
||||
|
||||
case 0x1000f130:
|
||||
|
|
@ -1174,7 +1160,7 @@ void hwConstWrite64(u32 mem, int mmreg)
|
|||
return;
|
||||
|
||||
case 0x1000a000: // dma2 - gif
|
||||
recDmaExec(GIF, 2);
|
||||
recDmaExec(dmaGIF, mem, mmreg);
|
||||
break;
|
||||
|
||||
case 0x1000e010: // DMAC_STAT
|
||||
|
|
|
|||
Loading…
Reference in New Issue