mirror of https://github.com/PCSX2/pcsx2.git
Clang: Format GS.h
This commit is contained in:
refractionpcsx2
parent
7717450044
commit
b843989719
242
pcsx2/GS.h
242
pcsx2/GS.h
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@ -28,10 +28,10 @@ alignas(16) extern u8 g_RealGSMem[Ps2MemSize::GSregs];
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enum CSR_FifoState
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{
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CSR_FIFO_NORMAL = 0, // Somwhere in between (Neither empty or almost full).
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CSR_FIFO_EMPTY, // Empty
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CSR_FIFO_FULL, // Almost Full
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CSR_FIFO_RESERVED // Reserved / Unused.
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CSR_FIFO_NORMAL = 0, // Somwhere in between (Neither empty or almost full).
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CSR_FIFO_EMPTY, // Empty
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CSR_FIFO_FULL, // Almost Full
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CSR_FIFO_RESERVED // Reserved / Unused.
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};
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// --------------------------------------------------------------------------------------
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@ -51,7 +51,7 @@ union tGS_CSR
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// Read:
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// 0 - No SIGNAL pending.
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// 1 - SIGNAL has been generated.
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u64 SIGNAL :1;
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u64 SIGNAL : 1;
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// Write:
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// 0 - No action;
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@ -59,7 +59,7 @@ union tGS_CSR
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// Read:
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// 0 - No FINISH event pending.
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// 1 - FINISH event has been generated.
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u64 FINISH :1;
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u64 FINISH : 1;
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// Hsync Interrupt Control
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// Write:
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@ -68,7 +68,7 @@ union tGS_CSR
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// Read:
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// 0 - No Hsync interrupt pending.
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// 1 - Hsync interrupt has been generated.
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u64 HSINT :1;
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u64 HSINT : 1;
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// Vsync Interrupt Control
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// Write:
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@ -77,7 +77,7 @@ union tGS_CSR
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// Read:
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// 0 - No Vsync interrupt pending.
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// 1 - Vsync interrupt has been generated.
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u64 VSINT :1;
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u64 VSINT : 1;
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// Rect Area Write Termination Control
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// 0 - No action;
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@ -85,18 +85,18 @@ union tGS_CSR
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// Read:
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// 0 - No RAWrite interrupt pending.
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// 1 - RAWrite interrupt has been generated.
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u64 EDWINT :1;
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u64 EDWINT : 1;
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u64 _zero1 :1;
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u64 _zero2 :1;
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u64 pad1 :1;
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u64 _zero1 : 1;
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u64 _zero2 : 1;
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u64 pad1 : 1;
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// FLUSH (write-only!)
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// Write:
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// 0 - Resume drawing if suspended (?)
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// 1 - Flush the GS FIFO and suspend drawing
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// Read: Always returns 0. (?)
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u64 FLUSH :1;
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u64 FLUSH : 1;
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// RESET (write-only!)
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// Write:
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@ -104,18 +104,18 @@ union tGS_CSR
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// 1 - GS soft system reset. Clears FIFOs and resets IMR to all 1's.
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// (PCSX2 implementation also clears GIFpaths, though that behavior may differ on real HW).
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// Read: Always returns 0. (?)
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u64 RESET :1;
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u64 RESET : 1;
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u64 _pad2 :2;
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u64 _pad2 : 2;
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// (I have no idea what this reg is-- air)
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// Output value is updated by sampling the VSync. (?)
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u64 NFIELD :1;
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u64 NFIELD : 1;
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// Current Field of Display [page flipping] (read-only?)
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// 0 - EVEN
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// 1 - ODD
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u64 FIELD :1;
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u64 FIELD : 1;
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// GS FIFO Status (read-only)
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// 00 - Somewhere in between
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@ -123,22 +123,22 @@ union tGS_CSR
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// 10 - Almost Full
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// 11 - Reserved (unused)
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// Assign values using the CSR_FifoState enum.
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u64 FIFO :2;
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u64 FIFO : 2;
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// Revision number of the GS (fairly arbitrary)
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u64 REV :8;
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u64 REV : 8;
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// ID of the GS (also fairly arbitrary)
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u64 ID :8;
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u64 ID : 8;
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};
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u64 _u64;
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struct
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{
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u32 _u32; // lower 32 bits (all useful content!)
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u32 _unused32; // upper 32 bits (unused -- should probably be 0)
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};
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u64 _u64;
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struct
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{
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u32 _u32; // lower 32 bits (all useful content!)
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u32 _unused32; // upper 32 bits (unused -- should probably be 0)
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};
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void SwapField()
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{
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@ -150,25 +150,25 @@ union tGS_CSR
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_u32 |= 0x2000;
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}
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void Reset()
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{
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_u64 = 0;
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FIFO = CSR_FIFO_EMPTY;
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REV = 0x1B; // GS Revision
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ID = 0x55; // GS ID
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}
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void Reset()
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{
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_u64 = 0;
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FIFO = CSR_FIFO_EMPTY;
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REV = 0x1B; // GS Revision
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ID = 0x55; // GS ID
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}
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bool HasAnyInterrupts() const { return (SIGNAL || FINISH || HSINT || VSINT || EDWINT); }
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bool HasAnyInterrupts() const { return (SIGNAL || FINISH || HSINT || VSINT || EDWINT); }
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u32 GetInterruptMask() const
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{
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return _u32 & 0x1f;
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}
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void SetAllInterrupts(bool value=true)
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{
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SIGNAL = FINISH = HSINT = VSINT = EDWINT = value;
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}
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void SetAllInterrupts(bool value = true)
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{
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SIGNAL = FINISH = HSINT = VSINT = EDWINT = value;
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}
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tGS_CSR(u64 val) { _u64 = val; }
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tGS_CSR(u32 val) { _u32 = val; }
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@ -180,32 +180,32 @@ union tGS_CSR
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// --------------------------------------------------------------------------------------
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union tGS_IMR
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{
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struct
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{
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u32 _reserved1 : 8;
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u32 SIGMSK : 1; // Signal evevnt interrupt mask
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u32 FINISHMSK : 1; // Finish event interrupt mask
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u32 HSMSK : 1; // HSync interrupt mask
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u32 VSMSK : 1; // VSync interrupt mask
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u32 EDWMSK : 1; // Rectangle write termination interrupt mask
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u32 _undefined : 2; // undefined bits should be set to 1.
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u32 _reserved2 : 17;
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};
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u32 _u32;
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struct
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{
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u32 _reserved1 : 8;
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u32 SIGMSK : 1; // Signal evevnt interrupt mask
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u32 FINISHMSK : 1; // Finish event interrupt mask
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u32 HSMSK : 1; // HSync interrupt mask
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u32 VSMSK : 1; // VSync interrupt mask
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u32 EDWMSK : 1; // Rectangle write termination interrupt mask
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u32 _undefined : 2; // undefined bits should be set to 1.
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u32 _reserved2 : 17;
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};
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u32 _u32;
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void reset()
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{
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_u32 = 0;
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SIGMSK = FINISHMSK = HSMSK = VSMSK = EDWMSK = true;
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_undefined = 0x3;
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}
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void set(u32 value)
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{
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_u32 = (value & 0x1f00); // Set only the interrupt mask fields.
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_undefined = 0x3; // These should always be set.
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}
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void reset()
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{
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_u32 = 0;
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SIGMSK = FINISHMSK = HSMSK = VSMSK = EDWMSK = true;
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_undefined = 0x3;
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}
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void set(u32 value)
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{
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_u32 = (value & 0x1f00); // Set only the interrupt mask fields.
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_undefined = 0x3; // These should always be set.
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}
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bool masked() const { return (SIGMSK || FINISHMSK || HSMSK || VSMSK || EDWMSK); }
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bool masked() const { return (SIGMSK || FINISHMSK || HSMSK || VSMSK || EDWMSK); }
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};
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// --------------------------------------------------------------------------------------
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@ -253,14 +253,14 @@ struct GSRegSIGBLID
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u32 LBLID;
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};
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#define PS2MEM_GS g_RealGSMem
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#define PS2GS_BASE(mem) (PS2MEM_GS+(mem&0x13ff))
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#define PS2MEM_GS g_RealGSMem
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#define PS2GS_BASE(mem) (PS2MEM_GS + (mem & 0x13ff))
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#define CSRreg ((tGS_CSR&)*(PS2MEM_GS+0x1000))
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#define CSRreg ((tGS_CSR&)*(PS2MEM_GS + 0x1000))
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#define GSCSRr ((u32&)*(PS2MEM_GS+0x1000))
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#define GSIMR ((tGS_IMR&)*(PS2MEM_GS+0x1010))
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#define GSSIGLBLID ((GSRegSIGBLID&)*(PS2MEM_GS+0x1080))
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#define GSCSRr ((u32&)*(PS2MEM_GS + 0x1000))
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#define GSIMR ((tGS_IMR&)*(PS2MEM_GS + 0x1010))
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#define GSSIGLBLID ((GSRegSIGBLID&)*(PS2MEM_GS + 0x1080))
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enum class GS_VideoMode : int
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{
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@ -296,8 +296,8 @@ enum MTGS_RingCommand
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GS_RINGTYPE_VSYNC,
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GS_RINGTYPE_FRAMESKIP,
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GS_RINGTYPE_FREEZE,
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GS_RINGTYPE_RESET, // issues a GSreset() command.
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GS_RINGTYPE_SOFTRESET, // issues a soft reset for the GIF
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GS_RINGTYPE_RESET, // issues a GSreset() command.
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GS_RINGTYPE_SOFTRESET, // issues a soft reset for the GIF
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GS_RINGTYPE_CRC,
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GS_RINGTYPE_GSPACKET,
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GS_RINGTYPE_MTVU_GSPACKET,
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@ -308,15 +308,15 @@ enum MTGS_RingCommand
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struct MTGS_FreezeData
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{
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freezeData* fdata;
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s32 retval; // value returned from the call, valid only after an mtgsWaitGS()
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freezeData* fdata;
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s32 retval; // value returned from the call, valid only after an mtgsWaitGS()
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};
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struct MTGS_MemoryScreenshotData
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{
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u32 width = 0;
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u32 height = 0;
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std::vector<u32> pixels; // width * height
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std::vector<u32> pixels; // width * height
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bool success = false;
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};
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@ -330,14 +330,14 @@ public:
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// note: when m_ReadPos == m_WritePos, the fifo is empty
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// Threading info: m_ReadPos is updated by the MTGS thread. m_WritePos is updated by the EE thread
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std::atomic<unsigned int> m_ReadPos; // cur pos gs is reading from
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std::atomic<unsigned int> m_ReadPos; // cur pos gs is reading from
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std::atomic<unsigned int> m_WritePos; // cur pos ee thread is writing to
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std::atomic<bool> m_SignalRingEnable;
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std::atomic<int> m_SignalRingPosition;
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std::atomic<bool> m_SignalRingEnable;
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std::atomic<int> m_SignalRingPosition;
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std::atomic<int> m_QueuedFrameCount;
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std::atomic<bool> m_VsyncSignalListener;
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std::atomic<int> m_QueuedFrameCount;
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std::atomic<bool> m_VsyncSignalListener;
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std::mutex m_mtx_RingBufferBusy2; // Gets released on semaXGkick waiting...
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std::mutex m_mtx_WaitGS;
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@ -351,14 +351,14 @@ public:
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// Used to delay the sending of events. Performance is better if the ringbuffer
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// has more than one command in it when the thread is kicked.
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int m_CopyDataTally;
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int m_CopyDataTally;
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// These vars maintain instance data for sending Data Packets.
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// Only one data packet can be constructed and uploaded at a time.
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uint m_packet_startpos; // size of the packet (data only, ie. not including the 16 byte command!)
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uint m_packet_size; // size of the packet (data only, ie. not including the 16 byte command!)
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uint m_packet_writepos; // index of the data location in the ringbuffer.
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uint m_packet_startpos; // size of the packet (data only, ie. not including the 16 byte command!)
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uint m_packet_size; // size of the packet (data only, ie. not including the 16 byte command!)
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uint m_packet_writepos; // index of the data location in the ringbuffer.
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#ifdef RINGBUF_DEBUG_STACK
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std::mutex m_lock_Stack;
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@ -387,17 +387,17 @@ public:
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void WaitGS(bool syncRegs=true, bool weakWait=false, bool isMTVU=false);
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void ResetGS(bool hardware_reset);
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void PrepDataPacket( MTGS_RingCommand cmd, u32 size );
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void PrepDataPacket( GIF_PATH pathidx, u32 size );
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void PrepDataPacket(MTGS_RingCommand cmd, u32 size);
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void PrepDataPacket(GIF_PATH pathidx, u32 size);
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void SendDataPacket();
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void SendGameCRC( u32 crc );
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void SendGameCRC(u32 crc);
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bool WaitForOpen();
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void WaitForClose();
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void Freeze( FreezeAction mode, MTGS_FreezeData& data );
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void Freeze(FreezeAction mode, MTGS_FreezeData& data);
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void SendSimpleGSPacket( MTGS_RingCommand type, u32 offset, u32 size, GIF_PATH path );
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void SendSimplePacket( MTGS_RingCommand type, int data0, int data1, int data2 );
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void SendPointerPacket( MTGS_RingCommand type, u32 data0, void* data1 );
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void SendSimpleGSPacket(MTGS_RingCommand type, u32 offset, u32 size, GIF_PATH path);
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void SendSimplePacket(MTGS_RingCommand type, int data0, int data1, int data2);
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void SendPointerPacket(MTGS_RingCommand type, u32 data0, void* data1);
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u8* GetDataPacketPtr() const;
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void SetEvent();
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@ -421,7 +421,7 @@ protected:
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void ThreadEntryPoint();
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void MainLoop();
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void GenericStall( uint size );
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void GenericStall(uint size);
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// Used internally by SendSimplePacket type functions
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void _FinishSimplePacket();
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@ -454,18 +454,18 @@ extern void gsWrite8(u32 mem, u8 value);
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extern void gsWrite16(u32 mem, u16 value);
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extern void gsWrite32(u32 mem, u32 value);
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extern void gsWrite64_page_00( u32 mem, const mem64_t* value );
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extern void gsWrite64_page_01( u32 mem, const mem64_t* value );
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extern void gsWrite64_generic( u32 mem, const mem64_t* value );
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extern void gsWrite64_page_00(u32 mem, const mem64_t* value);
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extern void gsWrite64_page_01(u32 mem, const mem64_t* value);
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extern void gsWrite64_generic(u32 mem, const mem64_t* value);
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extern void gsWrite128_page_00( u32 mem, const mem128_t* value );
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extern void gsWrite128_page_01( u32 mem, const mem128_t* value );
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extern void gsWrite128_generic( u32 mem, const mem128_t* value );
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extern void gsWrite128_page_00(u32 mem, const mem128_t* value);
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extern void gsWrite128_page_01(u32 mem, const mem128_t* value);
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extern void gsWrite128_generic(u32 mem, const mem128_t* value);
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extern u8 gsRead8(u32 mem);
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extern u16 gsRead16(u32 mem);
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extern u32 gsRead32(u32 mem);
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extern u64 gsRead64(u32 mem);
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extern u8 gsRead8(u32 mem);
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extern u16 gsRead16(u32 mem);
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extern u32 gsRead32(u32 mem);
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extern u64 gsRead64(u32 mem);
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extern u128 gsNonMirroredRead(u32 mem);
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void gsIrq();
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@ -479,7 +479,7 @@ extern tGS_CSR CSRr;
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static const uint RingBufferSizeFactor = 19;
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// size of the ringbuffer in simd128's.
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static const uint RingBufferSize = 1<<RingBufferSizeFactor;
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static const uint RingBufferSize = 1 << RingBufferSizeFactor;
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// Mask to apply to ring buffer indices to wrap the pointer from end to
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// start (the wrapping is what makes it a ringbuffer, yo!)
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@ -487,14 +487,14 @@ static const uint RingBufferMask = RingBufferSize - 1;
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struct MTGS_BufferedData
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{
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u128 m_Ring[RingBufferSize];
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u8 Regs[Ps2MemSize::GSregs];
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u128 m_Ring[RingBufferSize];
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u8 Regs[Ps2MemSize::GSregs];
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MTGS_BufferedData() {}
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u128& operator[]( uint idx )
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u128& operator[](uint idx)
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{
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pxAssert( idx < RingBufferSize );
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pxAssert(idx < RingBufferSize);
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return m_Ring[idx];
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}
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};
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@ -503,30 +503,36 @@ alignas(32) extern MTGS_BufferedData RingBuffer;
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// FIXME: These belong in common with other memcpy tools. Will move them there later if no one
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// else beats me to it. --air
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inline void MemCopy_WrappedDest( const u128* src, u128* destBase, uint& destStart, uint destSize, uint len ) {
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inline void MemCopy_WrappedDest(const u128* src, u128* destBase, uint& destStart, uint destSize, uint len)
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{
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uint endpos = destStart + len;
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if ( endpos < destSize ) {
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memcpy(&destBase[destStart], src, len*16);
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if (endpos < destSize)
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{
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memcpy(&destBase[destStart], src, len * 16);
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destStart += len;
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}
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else {
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else
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{
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uint firstcopylen = destSize - destStart;
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memcpy(&destBase[destStart], src, firstcopylen*16);
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memcpy(&destBase[destStart], src, firstcopylen * 16);
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destStart = endpos % destSize;
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memcpy(destBase, src+firstcopylen, destStart*16);
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memcpy(destBase, src + firstcopylen, destStart * 16);
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}
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}
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inline void MemCopy_WrappedSrc( const u128* srcBase, uint& srcStart, uint srcSize, u128* dest, uint len ) {
|
||||
inline void MemCopy_WrappedSrc(const u128* srcBase, uint& srcStart, uint srcSize, u128* dest, uint len)
|
||||
{
|
||||
uint endpos = srcStart + len;
|
||||
if ( endpos < srcSize ) {
|
||||
memcpy(dest, &srcBase[srcStart], len*16);
|
||||
if (endpos < srcSize)
|
||||
{
|
||||
memcpy(dest, &srcBase[srcStart], len * 16);
|
||||
srcStart += len;
|
||||
}
|
||||
else {
|
||||
else
|
||||
{
|
||||
uint firstcopylen = srcSize - srcStart;
|
||||
memcpy(dest, &srcBase[srcStart], firstcopylen*16);
|
||||
memcpy(dest, &srcBase[srcStart], firstcopylen * 16);
|
||||
srcStart = endpos % srcSize;
|
||||
memcpy(dest+firstcopylen, srcBase, srcStart*16);
|
||||
memcpy(dest + firstcopylen, srcBase, srcStart * 16);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue