mirror of https://github.com/PCSX2/pcsx2.git
Linux: Added more correct __asm__ qualifiers and conditions; including __volatile__ on a lot of asm code (it should really be the default behavior and non-vlatile the specifier, but whatever >_<), and added register clobber specifiers. Might help unbreak some of GCC 4.4's optimization problems, although VIFdma's uber-hack SSE optimization looks like a real problem.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1964 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
Jake.Stine
parent
a8b55baa38
commit
b71b837efa
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@ -102,64 +102,64 @@ static __forceinline void memset_8( void *dest )
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return;
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case 3:
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__asm__
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__asm__ volatile
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(
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".intel_syntax noprefix\n"
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"cld\n"
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// "mov edi, %[dest]\n"
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// "mov eax, %[data32]\n"
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"stosd\n"
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"stosd\n"
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"stosd\n"
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".att_syntax\n"
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:
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// Input specifiers: D - edi, a -- eax, c ecx
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: [dest]"D"(dest), [data32]"a"(data32)
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: "memory"
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);
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return;
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case 4:
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__asm__ volatile
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(
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".intel_syntax noprefix\n"
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"cld\n"
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// "mov edi, %[dest]\n"
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// "mov eax, %[data32]\n"
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"stosd\n"
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"stosd\n"
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"stosd\n"
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"stosd\n"
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".att_syntax\n"
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:
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: [dest]"D"(dest), [data32]"a"(data32)
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: "memory"
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);
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return;
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case 5:
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__asm__ volatile
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(
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".intel_syntax noprefix\n"
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"cld\n"
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// "mov edi, %[dest]\n"
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// "mov eax, %[data32]\n"
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"stosd\n"
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"stosd\n"
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"stosd\n"
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"stosd\n"
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"stosd\n"
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".att_syntax\n"
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:
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: [dest]"D"(dest), [data32]"a"(data32)
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// D - edi, a -- eax, c ecx
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:
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);
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return;
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case 4:
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__asm__
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(
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".intel_syntax noprefix\n"
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"cld\n"
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// "mov edi, %[dest]\n"
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// "mov eax, %[data32]\n"
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"stosd\n"
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"stosd\n"
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"stosd\n"
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"stosd\n"
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".att_syntax\n"
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:
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: [dest]"D"(dest), [data32]"a"(data32)
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:
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);
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return;
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case 5:
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__asm__
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(
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".intel_syntax noprefix\n"
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"cld\n"
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// "mov edi, %[dest]\n"
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// "mov eax, %[data32]\n"
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"stosd\n"
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"stosd\n"
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"stosd\n"
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"stosd\n"
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"stosd\n"
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".att_syntax\n"
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:
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: [dest]"D"(dest), [data32]"a"(data32)
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:
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: "memory"
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);
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return;
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default:
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__asm__
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__asm__ volatile
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(
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".intel_syntax noprefix\n"
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"cld\n"
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@ -170,7 +170,7 @@ static __forceinline void memset_8( void *dest )
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".att_syntax\n"
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:
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: [remdat]"c"(remdat), [dest]"D"(dest), [data32]"a"(data32)
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:
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: "memory"
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);
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return;
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}
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@ -27,12 +27,9 @@ __aligned16 x86CPU_INFO x86caps;
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static s32 iCpuId( u32 cmd, u32 *regs )
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{
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#ifdef _MSC_VER
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__asm
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{
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xor ecx, ecx; // ecx should be zero for CPUID(4)
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}
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__asm xor ecx, ecx; // ecx should be zero for CPUID(4)
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#else
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__asm__ ( "xor %ecx, %ecx" );
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__asm__ __volatile__ ( "xor %ecx, %ecx" );
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#endif
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__cpuid( (int*)regs, cmd );
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@ -65,7 +65,7 @@ __forceinline void FreezeMMXRegs(int save)
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emms
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}
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#else
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__asm__(
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__asm__ volatile(
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".intel_syntax noprefix\n"
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"movq [%[g_globalMMXData]+0x00], mm0\n"
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"movq [%[g_globalMMXData]+0x08], mm1\n"
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@ -76,7 +76,7 @@ __forceinline void FreezeMMXRegs(int save)
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"movq [%[g_globalMMXData]+0x30], mm6\n"
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"movq [%[g_globalMMXData]+0x38], mm7\n"
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"emms\n"
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".att_syntax\n" : : [g_globalMMXData]"r"(g_globalMMXData)
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".att_syntax\n" : : [g_globalMMXData]"r"(g_globalMMXData) : "memory"
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);
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#endif
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@ -105,7 +105,7 @@ __forceinline void FreezeMMXRegs(int save)
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emms
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}
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#else
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__asm__(
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__asm__ volatile(
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".intel_syntax noprefix\n"
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"movq mm0, [%[g_globalMMXData]+0x00]\n"
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"movq mm1, [%[g_globalMMXData]+0x08]\n"
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@ -116,7 +116,7 @@ __forceinline void FreezeMMXRegs(int save)
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"movq mm6, [%[g_globalMMXData]+0x30]\n"
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"movq mm7, [%[g_globalMMXData]+0x38]\n"
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"emms\n"
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".att_syntax\n" : : [g_globalMMXData]"r"(g_globalMMXData)
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".att_syntax\n" : : [g_globalMMXData]"r"(g_globalMMXData) : "memory"
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);
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#endif
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}
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@ -154,7 +154,7 @@ __forceinline void FreezeXMMRegs(int save)
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}
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#else
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__asm__(
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__asm__ volatile(
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".intel_syntax noprefix\n"
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"movaps [%[g_globalXMMData]+0x00], xmm0\n"
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"movaps [%[g_globalXMMData]+0x10], xmm1\n"
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@ -164,7 +164,7 @@ __forceinline void FreezeXMMRegs(int save)
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"movaps [%[g_globalXMMData]+0x50], xmm5\n"
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"movaps [%[g_globalXMMData]+0x60], xmm6\n"
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"movaps [%[g_globalXMMData]+0x70], xmm7\n"
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".att_syntax\n" : : [g_globalXMMData]"r"(g_globalXMMData)
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".att_syntax\n" : : [g_globalXMMData]"r"(g_globalXMMData) : "memory"
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);
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#endif // _MSC_VER
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@ -196,7 +196,7 @@ __forceinline void FreezeXMMRegs(int save)
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}
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#else
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__asm__(
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__asm__ volatile(
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".intel_syntax noprefix\n"
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"movaps xmm0, [%[g_globalXMMData]+0x00]\n"
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"movaps xmm1, [%[g_globalXMMData]+0x10]\n"
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@ -206,7 +206,7 @@ __forceinline void FreezeXMMRegs(int save)
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"movaps xmm5, [%[g_globalXMMData]+0x50]\n"
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"movaps xmm6, [%[g_globalXMMData]+0x60]\n"
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"movaps xmm7, [%[g_globalXMMData]+0x70]\n"
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".att_syntax\n" : : [g_globalXMMData]"r"(g_globalXMMData)
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".att_syntax\n" : : [g_globalXMMData]"r"(g_globalXMMData) : "memory"
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);
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#endif // _MSC_VER
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@ -55,7 +55,7 @@ enum
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BCb_COEFF = 0x40
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};
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static volatile const __aligned16 SSE2_Tables sse2_tables =
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static const __aligned16 SSE2_Tables sse2_tables =
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{
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{0x8000,0x8000,0x8000,0x8000,0x8000,0x8000,0x8000,0x8000}, // c_bias
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{16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16}, // y_bias
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@ -211,8 +211,10 @@ ihatemsvc:
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cmp esi, 64
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jne tworows
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}
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#elif defined(__GNUC__)
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__asm__(
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__asm__ __volatile__ (
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".intel_syntax noprefix\n"
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"mov eax, 1\n"
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"xor esi, esi\n"
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@ -220,8 +222,8 @@ ihatemsvc:
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// Use ecx and edx as base pointers, to allow for Mod/RM form on memOps.
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// This saves 2-3 bytes per instruction where these are used. :)
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"mov ecx, offset %c[yuv2rgb_temp]\n"
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"mov edx, offset %c[sse2_tables]+64\n"
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//"mov ecx, offset %c[yuv2rgb_temp]\n"
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//"mov edx, offset %c[sse2_tables]+64\n"
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".align 16\n"
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"tworows:\n"
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@ -237,29 +239,29 @@ ihatemsvc:
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// unfortunately I don't think this will matter despite being
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// technically potentially a little faster, but this is
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// equivalent to an add or sub
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"pxor xmm2, xmmword ptr [edx+%c[C_BIAS]]\n" // xmm2 <-- 8 x (Cb - 128) << 8
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"pxor xmm0, xmmword ptr [edx+%c[C_BIAS]]\n" // xmm0 <-- 8 x (Cr - 128) << 8
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"pxor xmm2, xmmword ptr [%[sse2_tables]+%c[C_BIAS]]\n" // xmm2 <-- 8 x (Cb - 128) << 8
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"pxor xmm0, xmmword ptr [%[sse2_tables]+%c[C_BIAS]]\n" // xmm0 <-- 8 x (Cr - 128) << 8
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"movaps xmm1, xmm0\n"
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"movaps xmm3, xmm2\n"
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"pmulhw xmm1, xmmword ptr [edx+%c[GCr_COEFF]]\n"
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"pmulhw xmm3, xmmword ptr [edx+%c[GCb_COEFF]]\n"
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"pmulhw xmm0, xmmword ptr [edx+%c[RCr_COEFF]]\n"
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"pmulhw xmm2, xmmword ptr [edx+%c[BCb_COEFF]]\n"
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"pmulhw xmm1, xmmword ptr [%[sse2_tables]+%c[GCr_COEFF]]\n"
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"pmulhw xmm3, xmmword ptr [%[sse2_tables]+%c[GCb_COEFF]]\n"
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"pmulhw xmm0, xmmword ptr [%[sse2_tables]+%c[RCr_COEFF]]\n"
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"pmulhw xmm2, xmmword ptr [%[sse2_tables]+%c[BCb_COEFF]]\n"
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"paddsw xmm1, xmm3\n"
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// store for the next line; looking at the code above
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// compared to the code below, I have to wonder whether
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// this was worth the hassle
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"movaps xmmword ptr [ecx], xmm0\n"
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"movaps xmmword ptr [ecx+16], xmm1\n"
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"movaps xmmword ptr [ecx+32], xmm2\n"
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"movaps xmmword ptr [%[yuv2rgb_temp]], xmm0\n"
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"movaps xmmword ptr [%[yuv2rgb_temp]+16], xmm1\n"
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"movaps xmmword ptr [%[yuv2rgb_temp]+32], xmm2\n"
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"jmp ihategcctoo\n"
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".align 16\n"
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"onerow:\n"
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"movaps xmm0, xmmword ptr [ecx]\n"
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"movaps xmm1, xmmword ptr [ecx+16]\n"
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"movaps xmm2, xmmword ptr [ecx+32]\n"
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"movaps xmm0, xmmword ptr [%[yuv2rgb_temp]]\n"
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"movaps xmm1, xmmword ptr [%[yuv2rgb_temp]+16]\n"
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"movaps xmm2, xmmword ptr [%[yuv2rgb_temp]+32]\n"
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"ihategcctoo:\n"
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"movaps xmm3, xmm0\n"
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@ -267,13 +269,13 @@ ihatemsvc:
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"movaps xmm5, xmm2\n"
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"movaps xmm6, xmmword ptr [mb8+edi]\n"
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"psubusb xmm6, xmmword ptr [edx+%c[Y_BIAS]]\n"
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"psubusb xmm6, xmmword ptr [%[sse2_tables]+%c[Y_BIAS]]\n"
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"movaps xmm7, xmm6\n"
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"psllw xmm6, 8\n" // xmm6 <- Y << 8 for pixels 0,2,4,6,8,10,12,14
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"pand xmm7, xmmword ptr [edx+%c[Y_MASK]]\n" // xmm7 <- Y << 8 for pixels 1,3,5,7,9,11,13,15
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"pand xmm7, xmmword ptr [%[sse2_tables]+%c[Y_MASK]]\n" // xmm7 <- Y << 8 for pixels 1,3,5,7,9,11,13,15
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"pmulhuw xmm6, xmmword ptr [edx+%c[Y_COEFF]]\n"
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"pmulhuw xmm7, xmmword ptr [edx+%c[Y_COEFF]]\n"
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"pmulhuw xmm6, xmmword ptr [%[sse2_tables]+%c[Y_COEFF]]\n"
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"pmulhuw xmm7, xmmword ptr [%[sse2_tables]+%c[Y_COEFF]]\n"
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"paddsw xmm0, xmm6\n"
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"paddsw xmm3, xmm7\n"
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@ -283,7 +285,7 @@ ihatemsvc:
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"paddsw xmm5, xmm7\n"
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// round
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"movaps xmm6, xmmword ptr [edx+%c[ROUND_1BIT]]\n"
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"movaps xmm6, xmmword ptr [%[sse2_tables]+%c[ROUND_1BIT]]\n"
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"paddw xmm0, xmm6\n"
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"paddw xmm1, xmm6\n"
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"paddw xmm2, xmm6\n"
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@ -343,11 +345,11 @@ ihatemsvc:
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:[C_BIAS]"i"(C_BIAS), [Y_BIAS]"i"(Y_BIAS), [Y_MASK]"i"(Y_MASK),
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[ROUND_1BIT]"i"(ROUND_1BIT), [Y_COEFF]"i"(Y_COEFF), [GCr_COEFF]"i"(GCr_COEFF),
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[GCb_COEFF]"i"(GCb_COEFF), [RCr_COEFF]"i"(RCr_COEFF), [BCb_COEFF]"i"(BCb_COEFF),
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[yuv2rgb_temp]"i"(yuv2rgb_temp), [sse2_tables]"i"(&sse2_tables)
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:
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[yuv2rgb_temp]"r"(yuv2rgb_temp), [sse2_tables]"r"(&sse2_tables)
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: "eax", "ebx", "esi", "edi", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "memory"
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);
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#else
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#error Unsupported compiler
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# error Unsupported compiler
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#endif
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FreezeXMMRegs(0);
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@ -646,6 +646,11 @@ static void VIFunpack(u32 *data, vifCode *v, unsigned int size, const unsigned i
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int writemask;
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u32 oldcycle = -1;
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// yay evil .. let's just set some XMM registers in the middle of C code
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// and "hope" they get preserved, in spite of the fact that x86-32 ABI specifies
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// these as "clobberable" registers (so any printf or something could decide to
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// clobber them, and has every right to... >_<) --air
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#ifdef _MSC_VER
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if (VIFdmanum)
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{
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@ -658,6 +663,10 @@ static void VIFunpack(u32 *data, vifCode *v, unsigned int size, const unsigned i
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__asm movaps XMM_COL, xmmword ptr [g_vifmask.Col0]
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}
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#else
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// I'd add volatile to these, but what's the point? This code already breaks
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// like 5000 coveted rules of binary interfacing regardless, and is only working by
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// the miracles and graces of a profound deity (or maybe it doesn't -- linux port
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// *does* have stability issues, especially in GCC 4.4). --air
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if (VIFdmanum)
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{
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__asm__(".intel_syntax noprefix\n"
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|
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@ -46,7 +46,7 @@ void SetCPUState(u32 sseMXCSR, u32 sseVUMXCSR)
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#ifdef _MSC_VER
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__asm ldmxcsr g_sseMXCSR; // set the new sse control
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#else
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__asm__("ldmxcsr %[g_sseMXCSR]" : : [g_sseMXCSR]"m"(g_sseMXCSR) );
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__asm__ __volatile__("ldmxcsr %[g_sseMXCSR]" : : [g_sseMXCSR]"m"(g_sseMXCSR) );
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#endif
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//g_sseVUMXCSR = g_sseMXCSR|0x6000;
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}
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|
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@ -657,22 +657,29 @@ static __forceinline s32 recExecuteBlock( s32 eeCycles )
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pop ebx
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}
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#else
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__asm__
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__asm__ __volatile__
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(
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// We should be able to rely on GAS syntax (the register clobber list) as a
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// replacement for manual push/pop of unpreserved registers.
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//
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// EBP note: As I feared, EBP is "required" for C++ excepion handling in Linux, and trying
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// to issue a clobber specifier for it causes an error. We really need to find a way to
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// disable EBP regalloc in iCore. --air
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".intel_syntax noprefix\n"
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"push ebx\n"
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"push esi\n"
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"push edi\n"
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//"push ebx\n"
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//"push esi\n"
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//"push edi\n"
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"push ebp\n"
|
||||
|
||||
"call iopDispatcherReg\n"
|
||||
|
||||
"pop ebp\n"
|
||||
"pop edi\n"
|
||||
"pop esi\n"
|
||||
"pop ebx\n"
|
||||
//"pop edi\n"
|
||||
//"pop esi\n"
|
||||
//"pop ebx\n"
|
||||
".att_syntax\n"
|
||||
);
|
||||
: : : "eax", "ebx", "ecx", "edx", "esi", "edi", "memory" );
|
||||
#endif
|
||||
|
||||
return psxBreak + psxCycleEE;
|
||||
|
|
@ -836,7 +843,7 @@ static void checkcodefn()
|
|||
#ifdef _MSC_VER
|
||||
__asm mov pctemp, eax;
|
||||
#else
|
||||
__asm__("movl %%eax, %[pctemp]" : : [pctemp]"m"(pctemp) );
|
||||
__asm__ __volatile__("movl %%eax, %[pctemp]" : [pctemp]"m="(pctemp) );
|
||||
#endif
|
||||
Console.WriteLn("iop code changed! %x", pctemp);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -104,7 +104,7 @@ static void __forceinline UseOldMaskCode(u32* &vif1masks, u32 &mask)
|
|||
u8* p0 = (u8*)&s_maskarr[mask&15][0];
|
||||
u8* p1 = (u8*)&s_maskarr[(mask>>4)&15][0];
|
||||
|
||||
__asm__(".intel_syntax noprefix\n"
|
||||
__asm__ __volatile__(".intel_syntax noprefix\n"
|
||||
"movaps xmm0, [%0]\n"
|
||||
"movaps xmm1, [%1]\n"
|
||||
"movaps xmm2, xmm0\n"
|
||||
|
|
@ -121,6 +121,6 @@ static void __forceinline UseOldMaskCode(u32* &vif1masks, u32 &mask)
|
|||
"movq [%2+40], xmm3\n"
|
||||
"movhps [%2+48], xmm2\n"
|
||||
"movhps [%2+56], xmm3\n"
|
||||
".att_syntax\n" : : "r"(p0), "r"(p1), "r"(vif1masks) );
|
||||
".att_syntax\n" : : "r"(p0), "r"(p1), "r"(vif1masks) : "memory" );
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -601,22 +601,29 @@ static void recExecute()
|
|||
|
||||
#else // _MSC_VER
|
||||
|
||||
__asm__
|
||||
__asm__ __volatile__
|
||||
(
|
||||
// We should be able to rely on GAS syntax (the register clobber list) as a
|
||||
// replacement for manual push/pop of unpreserved registers.
|
||||
|
||||
// EBP note: As I feared, EBP is "required" for C++ excepion handling in Linux, and trying
|
||||
// to issue a clobber specifier for it causes an error. We really need to find a way to
|
||||
// disable EBP regalloc in iCore. --air
|
||||
|
||||
".intel_syntax noprefix\n"
|
||||
"push ebx\n"
|
||||
"push esi\n"
|
||||
"push edi\n"
|
||||
"push ebp\n"
|
||||
//"push ebx\n"
|
||||
//"push esi\n"
|
||||
//"push edi\n"
|
||||
//"push ebp\n"
|
||||
|
||||
"call DispatcherReg\n"
|
||||
|
||||
"pop ebp\n"
|
||||
"pop edi\n"
|
||||
"pop esi\n"
|
||||
"pop ebx\n"
|
||||
//"pop ebp\n"
|
||||
//"pop edi\n"
|
||||
//"pop esi\n"
|
||||
//"pop ebx\n"
|
||||
".att_syntax\n"
|
||||
);
|
||||
: : : "eax", "ebx", "ecx", "edx", "esi", "edi", "memory" );
|
||||
#endif
|
||||
}
|
||||
catch( Exception::ForceDispatcherReg& )
|
||||
|
|
@ -679,21 +686,11 @@ void recClear(u32 addr, u32 size)
|
|||
BASEBLOCKEX* pexblock;
|
||||
BASEBLOCK* pblock;
|
||||
|
||||
//why the hell?
|
||||
#if 1
|
||||
// necessary since recompiler doesn't call femms/emms
|
||||
#ifdef __INTEL_COMPILER
|
||||
__asm__("emms");
|
||||
#ifdef _MSC_VER
|
||||
asm emms;
|
||||
#else
|
||||
#ifdef _MSC_VER
|
||||
if (x86caps.has3DNOWInstructionExtensions) __asm femms;
|
||||
else __asm emms;
|
||||
#else
|
||||
if( x86caps.has3DNOWInstructionExtensions )__asm__("femms");
|
||||
else
|
||||
__asm__("emms");
|
||||
#endif
|
||||
#endif
|
||||
__asm__ __volatile__("emms");
|
||||
#endif
|
||||
|
||||
if ((addr) >= maxrecmem || !(recLUT[(addr) >> 16] + (addr & ~0xFFFFUL)))
|
||||
|
|
|
|||
|
|
@ -299,7 +299,7 @@ static s32 __forceinline GetNoiseValues()
|
|||
#else
|
||||
__asm__ (
|
||||
".intel_syntax\n"
|
||||
"MOV %%eax,%0\n"
|
||||
"MOV %%eax,%1\n"
|
||||
"ROR %%eax,5\n"
|
||||
"XOR %%eax,0x9a\n"
|
||||
"MOV %%ebx,%%eax\n"
|
||||
|
|
@ -308,7 +308,7 @@ static s32 __forceinline GetNoiseValues()
|
|||
"XOR %%eax,%%ebx\n"
|
||||
"ROR %%eax,3\n"
|
||||
"MOV %0,%%eax\n"
|
||||
".att_syntax\n" : :"r"(Seed));
|
||||
".att_syntax\n" : "m="(Seed) : "m"(Seed));
|
||||
#endif
|
||||
return retval;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -207,7 +207,7 @@ static void __forceinline GetNoiseValues(s32& VD)
|
|||
#else
|
||||
__asm__ (
|
||||
".intel_syntax\n"
|
||||
"MOV %%eax,%0\n"
|
||||
"MOV %%eax,%1\n"
|
||||
"ROR %%eax,5\n"
|
||||
"XOR %%eax,0x9a\n"
|
||||
"MOV %%ebx,%%eax\n"
|
||||
|
|
@ -216,7 +216,7 @@ static void __forceinline GetNoiseValues(s32& VD)
|
|||
"XOR %%eax,%%ebx\n"
|
||||
"ROR %%eax,3\n"
|
||||
"MOV %0,%%eax\n"
|
||||
".att_syntax\n" : :"r"(Seed));
|
||||
".att_syntax\n" : "r="(Seed) :"r"(Seed));
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue