mirror of https://github.com/PCSX2/pcsx2.git
GregMiscellaneous: zzogl-pg:
* fix shift direction in sse2. * Reduce memory transfter to load pixel. git-svn-id: http://pcsx2.googlecode.com/svn/branches/GregMiscellaneous@3815 96395faa-99c1-11dd-bbfe-3dabce05a288
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gregory.hainaut@gmail.com
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eb10a257cb
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b6a224c4f9
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@ -3017,24 +3017,80 @@ static const __aligned16 u32 pixel_Amask[4] = {0x80000000, 0x80000000, 0x8000000
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static const __aligned16 u32 pixel_Rmask[4] = {0x00F80000, 0x00F80000, 0x00F80000, 0x00F80000};
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static const __aligned16 u32 pixel_Gmask[4] = {0x0000F800, 0x0000F800, 0x0000F800, 0x0000F800};
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static const __aligned16 u32 pixel_Bmask[4] = {0x000000F8, 0x000000F8, 0x000000F8, 0x000000F8};
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template <u32 size, u32 pageTable[size][64], typename Tdst, Tdst (*convfn)(u32), u32 INDEX>
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__forceinline void update_4pixels_sse2(u32* src, Tdst* basepage, u32 i_msk, u32 j, u32 mask[4], u32 imask)
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{
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Tdst* dst_tmp;
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__aligned16 u32 dsrc_tmp[4];
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__aligned16 u32 src_tmp[4];
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u32* base_ptr;
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// load 4 pixel into a 128 array
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dsrc_tmp[0] = src[RW((j<<6)+INDEX)];
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dsrc_tmp[1] = src[RW((j<<6)+INDEX+1)];
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dsrc_tmp[2] = src[RW((j<<6)+INDEX+2)];
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dsrc_tmp[3] = src[RW((j<<6)+INDEX+3)];
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// highly slow. memory -> register -> memory -> xmm ...
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// Intel SSE4.1 support an instruction to load memory to a part of xmm
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#if 0
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src_tmp[0] = src[RW((j<<6)+INDEX)];
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src_tmp[1] = src[RW((j<<6)+INDEX+1)];
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src_tmp[2] = src[RW((j<<6)+INDEX+2)];
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src_tmp[3] = src[RW((j<<6)+INDEX+3)];
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#endif
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// NOTE: maybe look at g++ instrinsic. (maybe it could be compatible with the window compiler)
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if (AA.x == 2) {
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base_ptr = &src[(((j<<6)+INDEX)<<2)];
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__asm__ __volatile
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(
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".intel_syntax noprefix\n"
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"movq xmm0, [%[base_ptr]+3]\n"
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"movq xmm1, [%[base_ptr]+11]\n"
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// fusion the 2 registers into 1
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"pslldq xmm1, 8\n"
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"pand xmm0, xmm1\n"
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".att_syntax\n"
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:
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: [base_ptr]"r"(base_ptr)
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: "xmm0", "xmm1"
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);
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} else if(AA.x ==1) {
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base_ptr = &src[(((j<<6)+INDEX)<<1)];
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__asm__ __volatile
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(
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".intel_syntax noprefix\n"
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"movq xmm0, [%[base_ptr]+1]\n"
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"movq xmm1, [%[base_ptr]+5]\n"
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// fusion the 2 registers into 1
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"pslldq xmm1, 8\n"
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"pand xmm0, xmm1\n"
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".att_syntax\n"
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:
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: [base_ptr]"r"(base_ptr)
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: "xmm0", "xmm1"
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);
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} else {
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base_ptr = &src[((j<<6)+INDEX)];
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__asm__ __volatile
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(
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".intel_syntax noprefix\n"
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"movdqu xmm0, [%[base_ptr]]\n"
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".att_syntax\n"
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:
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: [base_ptr]"r"(base_ptr)
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: "xmm0"
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);
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}
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// transform pixel from ARGB:8888 to ARGB:1555
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// It also does the fbm pixel mask
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__asm__
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(
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".intel_syntax noprefix\n"
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"movdqa xmm0, [%[dsrc_tmp]]\n" // load 4 pixel
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// The loading of the register is done above
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// "movdqa xmm0, [%[dsrc_tmp]]\n" // load 4 pixel
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"movdqa xmm1, xmm0\n"
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"movdqa xmm2, xmm0\n"
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"movdqa xmm3, xmm0\n"
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@ -3044,13 +3100,13 @@ __forceinline void update_4pixels_sse2(u32* src, Tdst* basepage, u32 i_msk, u32
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"psrld xmm0, 15\n"
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"pand xmm1, [%[pixel_Rmask]]\n"
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"pslld xmm1, 9\n"
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"psrld xmm1, 9\n"
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"pand xmm2, [%[pixel_Gmask]]\n"
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"pslld xmm2, 6\n"
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"psrld xmm2, 6\n"
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"pand xmm3, [%[pixel_Bmask]]\n"
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"pslld xmm2, 3\n"
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"psrld xmm3, 3\n"
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// Rebuild a full 16bits pixel
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"por xmm0, xmm1\n"
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@ -3062,11 +3118,11 @@ __forceinline void update_4pixels_sse2(u32* src, Tdst* basepage, u32 i_msk, u32
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"pand xmm0, xmm1\n"
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// save the result
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"movdqa [%[dsrc_tmp]], xmm0\n" // load 4 pixel
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"movdqa [%[src_tmp]], xmm0\n" // load 4 pixel
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".att_syntax\n"
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:
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: [dsrc_tmp]"r"(dsrc_tmp), [mask]"r"(mask), // note: I think 'm' only work for STATIC memory...
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: [src_tmp]"r"(src_tmp), [mask]"r"(mask), // note: I think 'm' only work for STATIC memory...
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[pixel_Amask]"m"(*pixel_Amask), [pixel_Rmask]"m"(*pixel_Rmask),
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[pixel_Bmask]"m"(*pixel_Bmask), [pixel_Gmask]"m"(*pixel_Gmask)
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: "xmm0", "xmm1", "xmm2", "xmm3", "memory"
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@ -3074,16 +3130,16 @@ __forceinline void update_4pixels_sse2(u32* src, Tdst* basepage, u32 i_msk, u32
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// Group 4 pixel to allow futur sse optimization of the convfn function
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dst_tmp = basepage + pageTable[i_msk][(INDEX)];
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*dst_tmp = (u16)dsrc_tmp[0] | (*dst_tmp & imask);
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*dst_tmp = (u16)src_tmp[0] | (*dst_tmp & imask);
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dst_tmp = basepage + pageTable[i_msk][INDEX+1];
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*dst_tmp = (u16)dsrc_tmp[1] | (*dst_tmp & imask);
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*dst_tmp = (u16)src_tmp[1] | (*dst_tmp & imask);
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dst_tmp = basepage + pageTable[i_msk][INDEX+2];
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*dst_tmp = (u16)dsrc_tmp[2] | (*dst_tmp & imask);
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*dst_tmp = (u16)src_tmp[2] | (*dst_tmp & imask);
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dst_tmp = basepage + pageTable[i_msk][INDEX+3];
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*dst_tmp = (u16)dsrc_tmp[3] | (*dst_tmp & imask);
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*dst_tmp = (u16)src_tmp[3] | (*dst_tmp & imask);
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}
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template <u32 size, u32 pageTable[size][64], typename Tdst, Tdst (*convfn)(u32), bool do_conversion>
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