mirror of https://github.com/PCSX2/pcsx2.git
Another MTGS fix. This one was a known bug that I was saving for last, and in fixing it I was able to roll back the hack-fix for in-game stalls from r375.
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@376 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
Jake.Stine
Gregory Hainaut
parent
6043dd643a
commit
b585641029
122
pcsx2/GS.cpp
122
pcsx2/GS.cpp
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@ -65,7 +65,7 @@ static void thread_close( thread_t& thread )
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if( status != STILL_ACTIVE ) break;
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Sleep( 3 );
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}
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CloseHandle( &thread );
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CloseHandle( thread );
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thread = NULL;
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}
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@ -126,7 +126,7 @@ struct wait_event_t
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pthread_cond_t cond;
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pthread_mutex_t mutex;
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wait_event_t() : cond( NULL ), mutex( NULL ) {}
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wait_event_t() : cond( PTHREAD_COND_INITIALIZER ), mutex( PTHREAD_MUTEX_INITIALIZER ) {}
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};
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typedef pthread_mutex_t mutex_t;
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@ -141,9 +141,7 @@ static bool thread_create( thread_t& thread )
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static void thread_close( thread_t& thread )
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{
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if( thread.p == NULL ) return;
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pthread_join( thread, NULL );
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thread.p = NULL;
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}
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static void event_init( wait_event_t& evt )
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@ -360,17 +358,6 @@ s32 gsOpen()
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return 0;
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}
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// Sleep instead of timeslice. This function is for use in cases where longer
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// delays are merited.
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__forceinline void _Sleep( int ms )
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{
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#ifdef _WIN32
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Sleep(ms);
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#else
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usleep(ms * 1000);
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#endif
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}
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void GS_SETEVENT()
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{
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event_set(g_hGsEvent);
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@ -383,7 +370,7 @@ __forceinline void gsWaitGS()
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GS_SETEVENT();
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while( *(volatile PU8*)&g_pGSRingPos != *(volatile PU8*)&g_pGSWritePos )
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_Sleep(2);
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_TIMESLICE();
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}
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// Sets the gsEvent flag and releases a timeslice.
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@ -618,7 +605,7 @@ void GSRingBufSimplePacket(int type, int data0, int data1, int data2)
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assert( future_writepos != *(volatile PU8*)&g_pGSRingPos );
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InterlockedExchangePointer(&g_pGSWritePos, future_writepos);
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GS_SETEVENT();
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//GS_SETEVENT();
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}
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void gsReset()
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@ -636,6 +623,7 @@ void gsReset()
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#endif
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MTGS_LOG( "MTGS > Sending Reset...\n" );
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GSRingBufSimplePacket( GS_RINGTYPE_RESET, 0, 0, 0 );
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//GS_SETEVENT();
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#ifdef _DEBUG
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g_mtgsCopyLock = 0;
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@ -704,18 +692,22 @@ void gsGIFReset()
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void CSRwrite(u32 value)
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{
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// [TODO] Ideally GSwriteCSR should be run through the MTGS ringbuffer also, but it doesn't
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// make much of a difference since the GS plugin only uses it for re-enabling gsInts, which
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// are handled by Pcsx2's GIFtagTransferDummy function instead of the GA in MTGS mode anyway.
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// (in other words the gs copy of CSRw is effectively ignored in MTGS mode)
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CSRw |= value & ~0x60;
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if( CHECK_MULTIGS )
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{
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GSRingBufSimplePacket( GS_RINGTYPE_WRITECSR, CSRw, 0, 0 );
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GS_SETEVENT();
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}
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else
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GSwriteCSR(CSRw);
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GSCSRr = ((GSCSRr&~value)&0x1f)|(GSCSRr&~0x1f);
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if( value & 0x100 ) { // FLUSH
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// Our emulated GS has no FIFO...
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/*if( value & 0x100 ) { // FLUSH
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//SysPrintf("GS_CSR FLUSH GS fifo: %x (CSRr=%x)\n", value, GSCSRr);
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}
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}*/
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if (value & 0x200) { // resetGS
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@ -725,20 +717,13 @@ void CSRwrite(u32 value)
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if( !_gsGIFSoftReset( 7 ) )
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{
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if( CHECK_MULTIGS )
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{
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GSRingBufSimplePacket( GS_RINGTYPE_RESET, 0, 0, 0 );
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}
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else
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GSreset();
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}
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GSCSRr = 0x551B400F; // Set the FINISH bit to 1 - GS is always at a finish state as we don't have a FIFO(saqib)
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GSIMR = 0x7F00; //This is bits 14-8 thats all that should be 1
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// and this too (fixed megaman ac)
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//CSRw = (u32)GSCSRr;
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// Since the line above was commented out, I don't think this was needed anymore (Air)
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//GSwriteCSR(CSRw);
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}
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}
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@ -778,14 +763,12 @@ void gsWrite16(u32 mem, u16 value) {
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case 0x12000010: // GS_SMODE1
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if((value & 0x6000) == 0x6000) Config.PsxType |= 1; // PAL
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else Config.PsxType &= ~1; // NTSC
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UpdateVSyncRate();
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break;
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case 0x12000020: // GS_SMODE2
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if(value & 0x1) Config.PsxType |= 2; // Interlaced
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else Config.PsxType &= ~2; // Non-Interlaced
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break;
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case 0x12001000: // GS_CSR
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@ -816,15 +799,12 @@ void gsWrite32(u32 mem, u32 value)
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case 0x12000010: // GS_SMODE1
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if((value & 0x6000) == 0x6000) Config.PsxType |= 1; // PAL
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else Config.PsxType &= ~1; // NTSC
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*(u32*)PS2GS_BASE(mem) = value;
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UpdateVSyncRate();
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break;
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case 0x12000020: // GS_SMODE2
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if(value & 0x1) Config.PsxType |= 2; // Interlaced
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else Config.PsxType &= ~2; // Non-Interlaced
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break;
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case 0x12001000: // GS_CSR
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@ -852,14 +832,13 @@ void gsWrite64(u32 mem, u64 value) {
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if((value & 0x6000) == 0x6000) Config.PsxType |= 1; // PAL
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else Config.PsxType &= ~1; // NTSC
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UpdateVSyncRate();
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break;
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case 0x12000020: // GS_SMODE2
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if(value & 0x1) Config.PsxType |= 2; // Interlaced
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else Config.PsxType &= ~2; // Non-Interlaced
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break;
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case 0x12001000: // GS_CSR
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CSRwrite((u32)value);
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return;
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@ -878,27 +857,27 @@ void gsWrite64(u32 mem, u64 value) {
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u8 gsRead8(u32 mem)
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{
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GIF_LOG("GS read 8 %8.8lx, at %8.8lx\n", *(u8*)PS2GS_BASE(mem), mem);
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GIF_LOG("GS read 8 from %8.8lx value: %8.8lx\n", mem, *(u8*)PS2GS_BASE(mem));
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return *(u8*)PS2GS_BASE(mem);
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}
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u16 gsRead16(u32 mem)
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{
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GIF_LOG("GS read 16 %8.8lx, at %8.8lx\n", *(u16*)PS2GS_BASE(mem), mem);
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GIF_LOG("GS read 16 from %8.8lx value: %8.8lx\n", mem, *(u16*)PS2GS_BASE(mem));
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return *(u16*)PS2GS_BASE(mem);
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}
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u32 gsRead32(u32 mem)
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{
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GIF_LOG("GS read 32 %8.8lx, at %8.8lx\n", *(u32*)PS2GS_BASE(mem), mem);
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GIF_LOG("GS read 32 from %8.8lx value: %8.8lx\n", mem, *(u32*)PS2GS_BASE(mem));
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return *(u32*)PS2GS_BASE(mem);
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}
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u64 gsRead64(u32 mem)
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{
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GIF_LOG("GS read 64 %8.8lx, at %8.8lx\n", *(u32*)PS2GS_BASE(mem), mem);
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GIF_LOG("GS read 64 from %8.8lx value: %8.8lx_%8.8lx\n", mem, *(u32*)PS2GS_BASE(mem+4), *(u32*)PS2GS_BASE(mem) );
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return *(u64*)PS2GS_BASE(mem);
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}
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@ -908,7 +887,7 @@ void gsIrq() {
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static void GSRegHandlerSIGNAL(u32* data)
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{
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GIF_LOG("GS SIGNAL data %x_%x CSRw %x\n",data[0], data[1], CSRw);
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MTGS_LOG("MTGS SIGNAL data %x_%x CSRw %x\n",data[0], data[1], CSRw);
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GSSIGLBLID->SIGID = (GSSIGLBLID->SIGID&~data[1])|(data[0]&data[1]);
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@ -924,7 +903,7 @@ static void GSRegHandlerSIGNAL(u32* data)
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static void GSRegHandlerFINISH(u32* data)
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{
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GIF_LOG("GS FINISH data %x_%x CSRw %x\n",data[0], data[1], CSRw);
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MTGS_LOG("MTGS FINISH data %x_%x CSRw %x\n",data[0], data[1], CSRw);
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if ((CSRw & 0x2))
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GSCSRr |= 2; // finish
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@ -1626,6 +1605,7 @@ extern "C" void GSPostVsyncEnd()
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//SysPrintf( " Sending VSync : %d \n", g_pGSvSyncCount );
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#endif
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GSRingBufSimplePacket(GS_RINGTYPE_VSYNC, (*(u32*)(PS2MEM_GS+0x1000)&0x2000), 0, 0);
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GS_SETEVENT();
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}
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else {
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GSvsync((*(u32*)(PS2MEM_GS+0x1000)&0x2000));
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@ -1737,53 +1717,6 @@ GS_THREADPROC
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*(u64*)(g_MTGSMem+*(u32*)(g_pGSRingPos+4)) = *(u64*)(g_pGSRingPos+8);
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break;
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case GS_RINGTYPE_VIFFIFO:
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{
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u64* pMem;
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assert( vif1ch->madr == *(u32*)(g_pGSRingPos+4) );
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assert( vif1ch->qwc == (tag>>16) );
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assert( vif1ch->madr == *(u32*)(g_pGSRingPos+4) );
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pMem = (u64*)dmaGetAddr(vif1ch->madr);
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if (pMem == NULL) {
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psHu32(DMAC_STAT)|= 1<<15;
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continue; // don't increment gsRingPos
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}
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if( GSreadFIFO2 == NULL ) {
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int size;
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for (size=(tag>>16); size>0; size--) {
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GSreadFIFO((u64*)&PS2MEM_HW[0x5000]);
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pMem[0] = psHu64(0x5000);
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pMem[1] = psHu64(0x5008); pMem+= 2;
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}
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}
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else {
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GSreadFIFO2(pMem, tag>>16);
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// set incase read
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psHu64(0x5000) = pMem[2*(tag>>16)-2];
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psHu64(0x5008) = pMem[2*(tag>>16)-1];
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}
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assert( vif1ch->madr == *(u32*)(g_pGSRingPos+4) );
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assert( vif1ch->qwc == (tag>>16) );
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// tag = (tag>>16) + (cpuRegs.cycle- *(u32*)(g_pGSRingPos+8));
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// if( tag & 0x80000000 ) tag = 0;
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vif1ch->madr += vif1ch->qwc * 16;
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if(vif1Regs->mskpath3 == 0)vif1Regs->stat&= ~0x1f000000;
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// fixme : calling CPU_INT could create a race condition if it runs parallel
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// with the EE/IOP code also calling CPU_INT.
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CPU_INT(1, 0); // since gs thread always lags real thread
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vif1ch->qwc = 0;
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break;
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}
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case GS_RINGTYPE_SAVE:
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{
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gzFile f = *(gzFile*)(g_pGSRingPos+4);
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@ -1852,6 +1785,11 @@ GS_THREADPROC
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break;
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}
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case GS_RINGTYPE_WRITECSR:
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GSwriteCSR( *(u32*)(g_pGSRingPos+4) );
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break;
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default:
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SysPrintf("GSThreadProc, bad packet (%x) at g_pGSRingPos: %x, g_pGSWritePos: %x\n", tag, g_pGSRingPos, g_pGSWritePos);
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@ -54,7 +54,6 @@ enum GS_RINGTYPE
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, GS_RINGTYPE_P2
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, GS_RINGTYPE_P3
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, GS_RINGTYPE_VSYNC
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, GS_RINGTYPE_VIFFIFO // GSreadFIFO2
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, GS_RINGTYPE_FRAMESKIP
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, GS_RINGTYPE_MEMWRITE8
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, GS_RINGTYPE_MEMWRITE16
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@ -65,6 +64,7 @@ enum GS_RINGTYPE
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, GS_RINGTYPE_RECORD
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, GS_RINGTYPE_RESET // issues a GSreset() command.
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, GS_RINGTYPE_SOFTRESET // issues a soft reset for the GIF
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, GS_RINGTYPE_WRITECSR
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};
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// if returns NULL, don't copy (memory is preserved)
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@ -438,7 +438,7 @@ static __forceinline void _cpuTestPERF()
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// Maximum wait between branches. Lower values provide a tighter synchronization between
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// the EE and the IOP, but incur more execution overhead.
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#define EE_WAIT_CYCLE 512 // 2048 is still unstable due to COP0
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#define EE_WAIT_CYCLE 2048 // 2048 is still unstable due to COP0
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// if cpuRegs.cycle is greater than this cycle, should check cpuBranchTest for updates
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u32 g_nextBranchCycle = 0;
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@ -517,8 +517,6 @@ X86_32CODE(extern u8 g_globalMMXSaved;)
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#endif
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#endif
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u32 g_MTGSVifStart = 0, g_MTGSVifCount=0;
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void cpuBranchTest()
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{
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#ifndef PCSX2_NORECBUILD
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@ -534,16 +532,6 @@ void cpuBranchTest()
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// Perform counters, ints, and IOP updates:
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_cpuBranchTest_Shared();
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// ---- MTGS -------------
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// stall mtgs if it is taking too long
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if( g_MTGSVifCount > 0 ) {
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if( (int)(cpuRegs.cycle-g_MTGSVifStart) > g_MTGSVifCount ) {
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gsWaitGS();
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g_MTGSVifCount = 0;
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}
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}
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// ---- VU0 -------------
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if (VU0.VI[REG_VPU_STAT].UL & 0x1)
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@ -2234,7 +2234,6 @@ __forceinline void vif1Interrupt() {
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cpuRegs.interrupt &= ~(1 << 1);
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}
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extern u32 g_MTGSVifStart, g_MTGSVifCount;
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#define spr0 ((DMACh*)&PS2MEM_HW[0xD000])
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void dmaVIF1()
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{
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@ -2309,41 +2308,13 @@ void dmaVIF1()
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return;
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}
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CPU_INT(1, g_vifCycles);
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} else { // from Memory
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if( CHECK_MULTIGS ) {
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u8* pTempMem, *pEndMem;
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u8* pMem = GSRingBufCopy(0, GS_RINGTYPE_VIFFIFO);
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*(u32*)(pMem-16) = GS_RINGTYPE_VIFFIFO|(vif1ch->qwc<<16); // hack
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*(u32*)(pMem-12) = vif1ch->madr;
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*(u32*)(pMem-8) = cpuRegs.cycle;
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// touch all the pages to make sure they are in memory
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pTempMem = dmaGetAddr(vif1ch->madr);
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pEndMem = (u8*)((uptr)(pTempMem + vif1ch->qwc*16 + 0xfff)&~0xfff);
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pTempMem = (u8*)((uptr)pTempMem&~0xfff);
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while(pTempMem < pEndMem ) {
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pTempMem[0]++;
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pTempMem[0]--;
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pTempMem += 0x1000;
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}
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GSRINGBUF_DONECOPY(pMem, 0);
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g_MTGSVifStart = cpuRegs.cycle;
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g_MTGSVifCount = 4000000; // a little less than 1/60th of a second
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// wait is, the safest option
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//gsWaitGS();
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//SysPrintf("waiting for gs\n");
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}
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else {
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} else {
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int size;
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u64* pMem = (u64*)dmaGetAddr(vif1ch->madr);
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// VIF from gsMemory
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if (pMem == NULL) { //Is ptag empty?
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SysPrintf("Vif1 Tag BUSERR\n");
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psHu32(DMAC_STAT)|= 1<<15; //If yes, set BEIS (BUSERR) in DMAC_STAT register
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@ -2354,15 +2325,24 @@ void dmaVIF1()
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return; //Return -1 as an error has occurred
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}
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// MTGS concerns: The MTGS is inherently disagreeable with the idea of downloading
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// stuff from the GS. The *only* way to handle this case safely is to flush the GS
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// completely and execute the transfer there-after.
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FreezeXMMRegs(1);
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if( GSreadFIFO2 == NULL ) {
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for (size=vif1ch->qwc; size>0; --size) {
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if (size > 1) GSreadFIFO((u64*)&PS2MEM_HW[0x5000]);
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if (size > 1 ) {
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gsWaitGS();
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GSreadFIFO((u64*)&PS2MEM_HW[0x5000]);
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}
|
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pMem[0] = psHu64(0x5000);
|
||||
pMem[1] = psHu64(0x5008); pMem+= 2;
|
||||
}
|
||||
}
|
||||
else {
|
||||
gsWaitGS();
|
||||
GSreadFIFO2(pMem, vif1ch->qwc);
|
||||
|
||||
// set incase read
|
||||
|
|
@ -2371,7 +2351,6 @@ void dmaVIF1()
|
|||
}
|
||||
FreezeXMMRegs(0);
|
||||
|
||||
|
||||
if(vif1Regs->mskpath3 == 0)vif1Regs->stat&= ~0x1f000000;
|
||||
g_vifCycles += vif1ch->qwc * 2;
|
||||
vif1ch->madr += vif1ch->qwc * 16; // mgs3 scene changes
|
||||
|
|
@ -2379,8 +2358,6 @@ void dmaVIF1()
|
|||
CPU_INT(1, g_vifCycles);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
vif1.done = 1;
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue