mirror of https://github.com/PCSX2/pcsx2.git
microVU:
- Implemented Nneeve's logical min/max algorithm. This should fix the problems with DaZ and mVU. - Applied a patch by Gigaherz that more clearly distinguishes Immediate values in microProgram log files. - Added a speedhack to disable the logical min/max code. (see below) Note: From my testing, using DaZ on mVU doesn't do much. However I have an AMD cpu, and they don't benefit as much as Intel C2D's from DaZ. So this could be effecting results. The logical min/max code is SLOW, and the little-benefit I get with DaZ means I get better performance with DaZ off and the min/max speedhack (which disables the extra min/max code). It would be nice is someone with an Intel C2D can compare the speed of: -mVU normal without DaZ -mVU normal with DaZ -mVU min/max speedhack without DaZ -mVU min/max speedhack with DaZ git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1177 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
3c715556e9
commit
b3bdaab4f0
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@ -166,7 +166,7 @@ microVUt(void) mVUallocFMAC4a(int& ACC, int& Fs, int& Ft) {
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microVUt(void) mVUallocFMAC4b(int& ACC, int& Fs) {
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microVU* mVU = mVUx;
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if (CHECK_VU_OVERFLOW) mVUclamp1<vuIndex>(Fs, xmmT1, _xyzw_ACC);
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mVUmergeRegs<vuIndex>(ACC, Fs, _X_Y_Z_W);
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mVUmergeRegs(ACC, Fs, _X_Y_Z_W);
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}
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//------------------------------------------------------------------
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@ -435,7 +435,7 @@ microVUt(void) mVUallocFMAC14a(int& ACCw, int& ACCr, int& Fs, int& Ft) {
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microVUt(void) mVUallocFMAC14b(int& ACCw, int& ACCr) {
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microVU* mVU = mVUx;
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if (CHECK_VU_OVERFLOW) mVUclamp1<vuIndex>(ACCr, xmmFt, _xyzw_ACC);
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mVUmergeRegs<vuIndex>(ACCw, ACCr, _X_Y_Z_W);
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mVUmergeRegs(ACCw, ACCr, _X_Y_Z_W);
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}
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//------------------------------------------------------------------
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@ -128,22 +128,19 @@ microVUt(int) mVUsetFlags(int* xStatus, int* xMac, int* xClip) {
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mVUinfo |= findFlagInst(xMac, cycles) << 16; // _fvmInstance
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mVUinfo |= findFlagInst(xClip, cycles) << 20; // _fvcInstance
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mVUinfo |= (xS & 3) << 12; // _fsInstance
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mVUinfo |= (xM & 3) << 10; // _fmInstance
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mVUinfo |= (xC & 3) << 14; // _fcInstance
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mVUinfo |= xS << 12; // _fsInstance
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mVUinfo |= xM << 10; // _fmInstance
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mVUinfo |= xC << 14; // _fcInstance
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if (doStatus || isFSSET || doDivFlag)
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xStatus[xS++ & 3] = cycles + 4;
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if (doMac)
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xMac[xM++ & 3] = cycles + 4;
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if (doClip)
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xClip[xC++ & 3] = cycles + 4;
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if (doStatus || isFSSET || doDivFlag) { xStatus[xS] = cycles + 4; xS = (xS+1) & 3; }
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if (doMac) { xMac [xM] = cycles + 4; xM = (xM+1) & 3; }
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if (doClip) { xClip [xC] = cycles + 4; xC = (xC+1) & 3; }
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cycles++;
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incPC2(2);
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}
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mVUregs.flags = ((__Clip) ? 0 : ((xC & 3) << 2)) | ((__Status) ? 0 : (xS & 3));
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mVUregs.flags = ((__Clip) ? 0 : (xC << 2)) | ((__Status) ? 0 : xS);
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return cycles;
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}
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@ -180,7 +177,6 @@ microVUt(void) mVUsetupFlags(int* xStatus, int* xMac, int* xClip, int cycles) {
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if (__Clip) {
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int bClip[4];
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sortFlag(xClip, bClip, cycles);
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//SysPrintf("__Clip\n");
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SSE_MOVAPS_M128_to_XMM(xmmT1, (uptr)mVU->clipFlag);
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SSE_SHUFPS_XMM_to_XMM (xmmT1, xmmT1, shuffleClip);
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SSE_MOVAPS_XMM_to_M128((uptr)mVU->clipFlag, xmmT1);
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@ -41,7 +41,7 @@ microVUx(void) __mVULog(const char* fmt, ...) {
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microVUt(void) __mVUdumpProgram(int progIndex) {
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microVU* mVU = mVUx;
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bool bitX[9];
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bool bitX[7];
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char str[30];
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int delay = 0;
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mVUbranch = 0;
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@ -73,10 +73,8 @@ microVUt(void) __mVUdumpProgram(int progIndex) {
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bitX[4] = 0;
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bitX[5] = 0;
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bitX[6] = 0;
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bitX[7] = 0;
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bitX[8] = 0;
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if (mVU->code & _Ibit_) { bitX[0] = 1; bitX[5] = 1; bitX[7] = 1; }
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if (mVU->code & _Ibit_) { bitX[0] = 1; bitX[5] = 1; }
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if (mVU->code & _Ebit_) { bitX[1] = 1; bitX[5] = 1; delay = 2; }
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if (mVU->code & _Mbit_) { bitX[2] = 1; bitX[5] = 1; }
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if (mVU->code & _Dbit_) { bitX[3] = 1; bitX[5] = 1; }
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@ -101,12 +99,18 @@ microVUt(void) __mVUdumpProgram(int progIndex) {
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}
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iPC = i;
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if (bitX[7]) { mVUlog("<font color=\"#0070ff\">"); }
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mVU->code = mVU->prog.prog[progIndex].data[i];
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mVUlog("<br>\n[%04x] (%08x) ", i*4, mVU->code);
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mVUopL<vuIndex, 2>();
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mVUlog("\n\n<br><br>");
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if (bitX[7]) { mVUlog("</font>"); }
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if(bitX[0]) {
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mVUlog("<br>\n<font color=\"#FF7000\">");
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mVUlog("[%04x] (%08x) %f", i*4, mVU->code, *(float*)&mVU->code);
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mVUlog("</font>\n\n<br><br>");
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}
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else {
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mVUlog("<br>\n[%04x] (%08x) ", i*4, mVU->code);
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mVUopL<vuIndex, 2>();
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mVUlog("\n\n<br><br>");
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}
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}
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mVUlog("</font>\n");
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mVUlog("</body>\n");
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@ -74,7 +74,7 @@ microVUf(void) mVU_DIV() {
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x86SetJ8(djmp);
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mVUunpack_xyzw<vuIndex>(xmmFs, xmmFs, 0);
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mVUmergeRegs<vuIndex>(xmmPQ, xmmFs, writeQ ? 4 : 8);
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mVUmergeRegs(xmmPQ, xmmFs, writeQ ? 4 : 8);
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}
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pass3 { mVUlog("DIV Q, vf%02d%s, vf%02d%s", _Fs_, _Fsf_String, _Ft_, _Ftf_String); }
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}
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@ -92,7 +92,7 @@ microVUf(void) mVU_SQRT() {
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if (CHECK_VU_OVERFLOW) SSE_MINSS_XMM_to_XMM(xmmFt, xmmMax); // Clamp infinities (only need to do positive clamp since xmmFt is positive)
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SSE_SQRTSS_XMM_to_XMM(xmmFt, xmmFt);
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mVUunpack_xyzw<vuIndex>(xmmFt, xmmFt, 0);
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mVUmergeRegs<vuIndex>(xmmPQ, xmmFt, writeQ ? 4 : 8);
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mVUmergeRegs(xmmPQ, xmmFt, writeQ ? 4 : 8);
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}
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pass3 { mVUlog("SQRT Q, vf%02d%s", _Ft_, _Ftf_String); }
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}
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@ -130,7 +130,7 @@ microVUf(void) mVU_RSQRT() {
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x86SetJ8(djmp);
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mVUunpack_xyzw<vuIndex>(xmmFs, xmmFs, 0);
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mVUmergeRegs<vuIndex>(xmmPQ, xmmFs, writeQ ? 4 : 8);
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mVUmergeRegs(xmmPQ, xmmFs, writeQ ? 4 : 8);
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}
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pass3 { mVUlog("RSQRT Q, vf%02d%s, vf%02d%s", _Fs_, _Fsf_String, _Ft_, _Ftf_String); }
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}
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@ -107,6 +107,7 @@ declareAllVariables
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#define getVUmem(x) (((vuIndex == 1) ? (x & 0x3ff) : ((x >= 0x400) ? (x & 0x43f) : (x & 0xff))) * 16)
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#define offsetSS ((_X) ? (0) : ((_Y) ? (4) : ((_Z) ? 8: 12)))
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#define offsetReg ((_X) ? (0) : ((_Y) ? (1) : ((_Z) ? 2: 3)))
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#define xmmT1 0 // Temp Reg
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#define xmmFs 1 // Holds the Value of Fs (writes back result Fd)
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@ -174,6 +175,7 @@ declareAllVariables
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#define bSaveAddr (((xPC + (2 * 8)) & ((vuIndex) ? 0x3ff8:0xff8)) / 8)
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#define branchAddr ((xPC + 8 + (_Imm11_ * 8)) & ((vuIndex) ? 0x3ff8:0xff8))
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#define shufflePQ (((mVU->p) ? 0xb0 : 0xe0) | ((mVU->q) ? 0x01 : 0x04))
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#define mVUflagHack (mVUcurProg.sFlagHack)
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// Pass 1 uses these to set mVUinfo
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#define _isNOP (1<<0) // Skip Lower Instruction
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@ -287,9 +289,9 @@ declareAllVariables
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#define mVUdumpProg 0&&
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#endif
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// Status Flag Speed Hack
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#define CHECK_VU_FLAGHACK 0 // Set to 1 to turn hack on
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#define mVUflagHack (mVUcurProg.sFlagHack)
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// Speed Hacks (Set to 1 to turn On)
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#define CHECK_VU_FLAGHACK 0 // Status Flag Speed Hack
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#define CHECK_VU_MINMAXHACK 0 // Min/Max Speed Hack
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// Cache Limit Check
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#define mVUcacheCheck(ptr, start, limit) { \
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@ -205,7 +205,7 @@ microVUx(void) mVUsaveReg2(int reg, int gprReg, u32 offset, int xyzw) {
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}
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// Modifies the Source Reg!
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microVUx(void) mVUmergeRegs(int dest, int src, int xyzw) {
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void mVUmergeRegs(int dest, int src, int xyzw) {
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xyzw &= 0xf;
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if ( (dest != src) && (xyzw != 0) ) {
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if ( cpucaps.hasStreamingSIMD4Extensions && (xyzw != 0x8) && (xyzw != 0xf) ) {
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@ -316,4 +316,65 @@ microVUt(void) mVUcheckSflag(int progIndex) {
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}
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}
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static const u32 PCSX2_ALIGNED16(MIN_MAX_MASK1[4]) = {0xffffffff, 0x80000000, 0xffffffff, 0x80000000};
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static const u32 PCSX2_ALIGNED16(MIN_MAX_MASK2[4]) = {0x00000000, 0x40000000, 0x00000000, 0x40000000};
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// Warning: Modifies xmmT1 and xmmT2
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void MIN_MAX_(x86SSERegType to, x86SSERegType from, bool min) {
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// XY
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SSE2_PSHUFD_XMM_to_XMM(xmmT1, to, 0x50);
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SSE2_PAND_M128_to_XMM (xmmT1, (uptr)MIN_MAX_MASK1);
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SSE2_POR_M128_to_XMM (xmmT1, (uptr)MIN_MAX_MASK2);
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SSE2_PSHUFD_XMM_to_XMM(xmmT2, from, 0x50);
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SSE2_PAND_M128_to_XMM (xmmT2, (uptr)MIN_MAX_MASK1);
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SSE2_POR_M128_to_XMM (xmmT2, (uptr)MIN_MAX_MASK2);
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if (min) SSE2_MINPD_XMM_to_XMM(xmmT1, xmmT2);
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else SSE2_MAXPD_XMM_to_XMM(xmmT1, xmmT2);
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SSE2_PSHUFD_XMM_to_XMM(xmmT1, xmmT1, 0x88);
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mVUmergeRegs(to, xmmT1, 0xc);
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// ZW
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SSE2_PSHUFD_XMM_to_XMM(xmmT1, to, 0xfa);
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SSE2_PAND_M128_to_XMM (xmmT1, (uptr)MIN_MAX_MASK1);
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SSE2_POR_M128_to_XMM (xmmT1, (uptr)MIN_MAX_MASK2);
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SSE2_PSHUFD_XMM_to_XMM(xmmT2, from, 0xfa);
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SSE2_PAND_M128_to_XMM (xmmT2, (uptr)MIN_MAX_MASK1);
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SSE2_POR_M128_to_XMM (xmmT2, (uptr)MIN_MAX_MASK2);
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if (min) SSE2_MINPD_XMM_to_XMM(xmmT1, xmmT2);
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else SSE2_MAXPD_XMM_to_XMM(xmmT1, xmmT2);
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SSE2_PSHUFD_XMM_to_XMM(xmmT1, xmmT1, 0x88);
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mVUmergeRegs(to, xmmT1, 0x3);
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}
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// Warning: Modifies from and to's upper 3 vectors
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void MIN_MAX_SS(x86SSERegType to, x86SSERegType from, bool min) {
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SSE2_PSHUFD_XMM_to_XMM(to, to, 0x50);
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SSE2_PAND_M128_to_XMM (to, (uptr)MIN_MAX_MASK1);
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SSE2_POR_M128_to_XMM (to, (uptr)MIN_MAX_MASK2);
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SSE2_PSHUFD_XMM_to_XMM(from, from, 0x50);
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SSE2_PAND_M128_to_XMM (from, (uptr)MIN_MAX_MASK1);
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SSE2_POR_M128_to_XMM (from, (uptr)MIN_MAX_MASK2);
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if (min) SSE2_MINPD_XMM_to_XMM(to, from);
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else SSE2_MAXPD_XMM_to_XMM(to, from);
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}
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void SSE_MAX2PS_XMM_to_XMM(x86SSERegType to, x86SSERegType from) {
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if (CHECK_VU_MINMAXHACK) { SSE_MAXPS_XMM_to_XMM(to, from); }
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else { MIN_MAX_(to, from, 0); }
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}
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void SSE_MIN2PS_XMM_to_XMM(x86SSERegType to, x86SSERegType from) {
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if (CHECK_VU_MINMAXHACK) { SSE_MINPS_XMM_to_XMM(to, from); }
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else { MIN_MAX_(to, from, 1); }
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}
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void SSE_MAX2SS_XMM_to_XMM(x86SSERegType to, x86SSERegType from) {
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if (CHECK_VU_MINMAXHACK) { SSE_MAXSS_XMM_to_XMM(to, from); }
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else { MIN_MAX_SS(to, from, 0); }
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}
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void SSE_MIN2SS_XMM_to_XMM(x86SSERegType to, x86SSERegType from) {
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if (CHECK_VU_MINMAXHACK) { SSE_MINSS_XMM_to_XMM(to, from); }
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else { MIN_MAX_SS(to, from, 1); }
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}
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#endif //PCSX2_MICROVU
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@ -25,7 +25,7 @@
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#define AND_XYZW ((_XYZW_SS && modXYZW) ? (1) : (doMac ? (_X_Y_Z_W) : (flipMask[_X_Y_Z_W])))
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#define ADD_XYZW ((_XYZW_SS && modXYZW) ? (_X ? 3 : (_Y ? 2 : (_Z ? 1 : 0))) : 0)
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#define SHIFT_XYZW(gprReg) { if (_XYZW_SS && modXYZW && !_W) { SHL16ItoR(gprReg, ADD_XYZW); } }
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#define SHIFT_XYZW(gprReg) { if (_XYZW_SS && modXYZW && !_W) { SHL32ItoR(gprReg, ADD_XYZW); } }
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// Note: If modXYZW is true, then it adjusts XYZW for Single Scalar operations
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microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modXYZW) {
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@ -57,8 +57,8 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
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AND32ItoR(mReg, AND_XYZW); // Grab "Is Signed" bits from the previous calculation
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pjmp = JZ8(0); // Skip if none are
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if (doMac) SHL16ItoR(mReg, 4 + ADD_XYZW);
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if (doStatus) OR16ItoR(sReg, 0x82); // SS, S flags
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if (doMac) SHL32ItoR(mReg, 4 + ADD_XYZW);
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if (doStatus) OR32ItoR(sReg, 0x82); // SS, S flags
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if (_XYZW_SS) pjmp2 = JMP8(0); // If negative and not Zero, we can skip the Zero Flag checking
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x86SetJ8(pjmp);
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@ -67,7 +67,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
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AND32ItoR(gprT2, AND_XYZW); // Grab "Is Zero" bits from the previous calculation
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pjmp = JZ8(0); // Skip if none are
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if (doMac) { SHIFT_XYZW(gprT2); OR32RtoR(mReg, gprT2); }
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if (doStatus) { OR16ItoR(sReg, 0x41); } // ZS, Z flags
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if (doStatus) { OR32ItoR(sReg, 0x41); } // ZS, Z flags
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x86SetJ8(pjmp);
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//-------------------------Write back flags------------------------------
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@ -476,90 +476,90 @@ microVUf(void) mVU_ABS() {
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}
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pass3 { mVUlog("ABS"); mVUlogFtFs(); }
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}
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microVUf(void) mVU_ADD() { mVU_FMAC1 (ADD, "ADD"); }
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microVUf(void) mVU_ADDi() { mVU_FMAC6 (ADD, "ADDi"); }
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microVUf(void) mVU_ADDq() { mVU_FMAC22(ADD, "ADDq"); }
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microVUf(void) mVU_ADDx() { mVU_FMAC3 (ADD, "ADDx"); }
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microVUf(void) mVU_ADDy() { mVU_FMAC3 (ADD, "ADDy"); }
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microVUf(void) mVU_ADDz() { mVU_FMAC3 (ADD, "ADDz"); }
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microVUf(void) mVU_ADDw() { mVU_FMAC3 (ADD, "ADDw"); }
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microVUf(void) mVU_ADDA() { mVU_FMAC4 (ADD, "ADDA"); }
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microVUf(void) mVU_ADDAi() { mVU_FMAC7 (ADD, "ADDAi"); }
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microVUf(void) mVU_ADDAq() { mVU_FMAC23(ADD, "ADDAq"); }
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microVUf(void) mVU_ADDAx() { mVU_FMAC5 (ADD, "ADDAx"); }
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microVUf(void) mVU_ADDAy() { mVU_FMAC5 (ADD, "ADDAy"); }
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microVUf(void) mVU_ADDAz() { mVU_FMAC5 (ADD, "ADDAz"); }
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microVUf(void) mVU_ADDAw() { mVU_FMAC5 (ADD, "ADDAw"); }
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microVUf(void) mVU_SUB() { mVU_FMAC1 (SUB, "SUB"); }
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microVUf(void) mVU_SUBi() { mVU_FMAC6 (SUB, "SUBi"); }
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microVUf(void) mVU_SUBq() { mVU_FMAC22(SUB, "SUBq"); }
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microVUf(void) mVU_SUBx() { mVU_FMAC3 (SUB, "SUBx"); }
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microVUf(void) mVU_SUBy() { mVU_FMAC3 (SUB, "SUBy"); }
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microVUf(void) mVU_SUBz() { mVU_FMAC3 (SUB, "SUBz"); }
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microVUf(void) mVU_SUBw() { mVU_FMAC3 (SUB, "SUBw"); }
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microVUf(void) mVU_SUBA() { mVU_FMAC4 (SUB, "SUBA"); }
|
||||
microVUf(void) mVU_SUBAi() { mVU_FMAC7 (SUB, "SUBAi"); }
|
||||
microVUf(void) mVU_SUBAq() { mVU_FMAC23(SUB, "SUBAq"); }
|
||||
microVUf(void) mVU_SUBAx() { mVU_FMAC5 (SUB, "SUBAx"); }
|
||||
microVUf(void) mVU_SUBAy() { mVU_FMAC5 (SUB, "SUBAy"); }
|
||||
microVUf(void) mVU_SUBAz() { mVU_FMAC5 (SUB, "SUBAz"); }
|
||||
microVUf(void) mVU_SUBAw() { mVU_FMAC5 (SUB, "SUBAw"); }
|
||||
microVUf(void) mVU_MUL() { mVU_FMAC1 (MUL, "MUL"); }
|
||||
microVUf(void) mVU_MULi() { mVU_FMAC6 (MUL, "MULi"); }
|
||||
microVUf(void) mVU_MULq() { mVU_FMAC22(MUL, "MULq"); }
|
||||
microVUf(void) mVU_MULx() { mVU_FMAC3 (MUL, "MULx"); }
|
||||
microVUf(void) mVU_MULy() { mVU_FMAC3 (MUL, "MULy"); }
|
||||
microVUf(void) mVU_MULz() { mVU_FMAC3 (MUL, "MULz"); }
|
||||
microVUf(void) mVU_MULw() { mVU_FMAC3 (MUL, "MULw"); }
|
||||
microVUf(void) mVU_MULA() { mVU_FMAC4 (MUL, "MULA"); }
|
||||
microVUf(void) mVU_MULAi() { mVU_FMAC7 (MUL, "MULAi"); }
|
||||
microVUf(void) mVU_MULAq() { mVU_FMAC23(MUL, "MULAq"); }
|
||||
microVUf(void) mVU_MULAx() { mVU_FMAC5 (MUL, "MULAx"); }
|
||||
microVUf(void) mVU_MULAy() { mVU_FMAC5 (MUL, "MULAy"); }
|
||||
microVUf(void) mVU_MULAz() { mVU_FMAC5 (MUL, "MULAz"); }
|
||||
microVUf(void) mVU_MULAw() { mVU_FMAC5 (MUL, "MULAw"); }
|
||||
microVUf(void) mVU_MADD() { mVU_FMAC8 (ADD, "MADD"); }
|
||||
microVUf(void) mVU_MADDi() { mVU_FMAC12(ADD, "MADDi"); }
|
||||
microVUf(void) mVU_MADDq() { mVU_FMAC24(ADD, "MADDq"); }
|
||||
microVUf(void) mVU_MADDx() { mVU_FMAC10(ADD, "MADDx"); }
|
||||
microVUf(void) mVU_MADDy() { mVU_FMAC10(ADD, "MADDy"); }
|
||||
microVUf(void) mVU_MADDz() { mVU_FMAC10(ADD, "MADDz"); }
|
||||
microVUf(void) mVU_MADDw() { mVU_FMAC10(ADD, "MADDw"); }
|
||||
microVUf(void) mVU_MADDA() { mVU_FMAC14(ADD, "MADDA"); }
|
||||
microVUf(void) mVU_MADDAi() { mVU_FMAC16(ADD, "MADDAi"); }
|
||||
microVUf(void) mVU_MADDAq() { mVU_FMAC26(ADD, "MADDAq"); }
|
||||
microVUf(void) mVU_MADDAx() { mVU_FMAC15(ADD, "MADDAx"); }
|
||||
microVUf(void) mVU_MADDAy() { mVU_FMAC15(ADD, "MADDAy"); }
|
||||
microVUf(void) mVU_MADDAz() { mVU_FMAC15(ADD, "MADDAz"); }
|
||||
microVUf(void) mVU_MADDAw() { mVU_FMAC15(ADD, "MADDAw"); }
|
||||
microVUf(void) mVU_MSUB() { mVU_FMAC9 (SUB, "MSUB"); }
|
||||
microVUf(void) mVU_MSUBi() { mVU_FMAC13(SUB, "MSUBi"); }
|
||||
microVUf(void) mVU_MSUBq() { mVU_FMAC25(SUB, "MSUBq"); }
|
||||
microVUf(void) mVU_MSUBx() { mVU_FMAC11(SUB, "MSUBx"); }
|
||||
microVUf(void) mVU_MSUBy() { mVU_FMAC11(SUB, "MSUBy"); }
|
||||
microVUf(void) mVU_MSUBz() { mVU_FMAC11(SUB, "MSUBz"); }
|
||||
microVUf(void) mVU_MSUBw() { mVU_FMAC11(SUB, "MSUBw"); }
|
||||
microVUf(void) mVU_MSUBA() { mVU_FMAC14(SUB, "MSUBA"); }
|
||||
microVUf(void) mVU_MSUBAi() { mVU_FMAC16(SUB, "MSUBAi"); }
|
||||
microVUf(void) mVU_MSUBAq() { mVU_FMAC26(SUB, "MSUBAq"); }
|
||||
microVUf(void) mVU_MSUBAx() { mVU_FMAC15(SUB, "MSUBAx"); }
|
||||
microVUf(void) mVU_MSUBAy() { mVU_FMAC15(SUB, "MSUBAy"); }
|
||||
microVUf(void) mVU_MSUBAz() { mVU_FMAC15(SUB, "MSUBAz"); }
|
||||
microVUf(void) mVU_MSUBAw() { mVU_FMAC15(SUB, "MSUBAw"); }
|
||||
microVUf(void) mVU_MAX() { mVU_FMAC1 (MAX, "MAX"); }
|
||||
microVUf(void) mVU_MAXi() { mVU_FMAC6 (MAX, "MAXi"); }
|
||||
microVUf(void) mVU_MAXx() { mVU_FMAC3 (MAX, "MAXx"); }
|
||||
microVUf(void) mVU_MAXy() { mVU_FMAC3 (MAX, "MAXy"); }
|
||||
microVUf(void) mVU_MAXz() { mVU_FMAC3 (MAX, "MAXz"); }
|
||||
microVUf(void) mVU_MAXw() { mVU_FMAC3 (MAX, "MAXw"); }
|
||||
microVUf(void) mVU_MINI() { mVU_FMAC1 (MIN, "MINI"); }
|
||||
microVUf(void) mVU_MINIi() { mVU_FMAC6 (MIN, "MINIi"); }
|
||||
microVUf(void) mVU_MINIx() { mVU_FMAC3 (MIN, "MINIx"); }
|
||||
microVUf(void) mVU_MINIy() { mVU_FMAC3 (MIN, "MINIy"); }
|
||||
microVUf(void) mVU_MINIz() { mVU_FMAC3 (MIN, "MINIz"); }
|
||||
microVUf(void) mVU_MINIw() { mVU_FMAC3 (MIN, "MINIw"); }
|
||||
microVUf(void) mVU_OPMULA() { mVU_FMAC18(MUL, "OPMULA"); }
|
||||
microVUf(void) mVU_OPMSUB() { mVU_FMAC19(SUB, "OPMSUB"); }
|
||||
microVUf(void) mVU_ADD() { mVU_FMAC1 (ADD, "ADD"); }
|
||||
microVUf(void) mVU_ADDi() { mVU_FMAC6 (ADD, "ADDi"); }
|
||||
microVUf(void) mVU_ADDq() { mVU_FMAC22(ADD, "ADDq"); }
|
||||
microVUf(void) mVU_ADDx() { mVU_FMAC3 (ADD, "ADDx"); }
|
||||
microVUf(void) mVU_ADDy() { mVU_FMAC3 (ADD, "ADDy"); }
|
||||
microVUf(void) mVU_ADDz() { mVU_FMAC3 (ADD, "ADDz"); }
|
||||
microVUf(void) mVU_ADDw() { mVU_FMAC3 (ADD, "ADDw"); }
|
||||
microVUf(void) mVU_ADDA() { mVU_FMAC4 (ADD, "ADDA"); }
|
||||
microVUf(void) mVU_ADDAi() { mVU_FMAC7 (ADD, "ADDAi"); }
|
||||
microVUf(void) mVU_ADDAq() { mVU_FMAC23(ADD, "ADDAq"); }
|
||||
microVUf(void) mVU_ADDAx() { mVU_FMAC5 (ADD, "ADDAx"); }
|
||||
microVUf(void) mVU_ADDAy() { mVU_FMAC5 (ADD, "ADDAy"); }
|
||||
microVUf(void) mVU_ADDAz() { mVU_FMAC5 (ADD, "ADDAz"); }
|
||||
microVUf(void) mVU_ADDAw() { mVU_FMAC5 (ADD, "ADDAw"); }
|
||||
microVUf(void) mVU_SUB() { mVU_FMAC1 (SUB, "SUB"); }
|
||||
microVUf(void) mVU_SUBi() { mVU_FMAC6 (SUB, "SUBi"); }
|
||||
microVUf(void) mVU_SUBq() { mVU_FMAC22(SUB, "SUBq"); }
|
||||
microVUf(void) mVU_SUBx() { mVU_FMAC3 (SUB, "SUBx"); }
|
||||
microVUf(void) mVU_SUBy() { mVU_FMAC3 (SUB, "SUBy"); }
|
||||
microVUf(void) mVU_SUBz() { mVU_FMAC3 (SUB, "SUBz"); }
|
||||
microVUf(void) mVU_SUBw() { mVU_FMAC3 (SUB, "SUBw"); }
|
||||
microVUf(void) mVU_SUBA() { mVU_FMAC4 (SUB, "SUBA"); }
|
||||
microVUf(void) mVU_SUBAi() { mVU_FMAC7 (SUB, "SUBAi"); }
|
||||
microVUf(void) mVU_SUBAq() { mVU_FMAC23(SUB, "SUBAq"); }
|
||||
microVUf(void) mVU_SUBAx() { mVU_FMAC5 (SUB, "SUBAx"); }
|
||||
microVUf(void) mVU_SUBAy() { mVU_FMAC5 (SUB, "SUBAy"); }
|
||||
microVUf(void) mVU_SUBAz() { mVU_FMAC5 (SUB, "SUBAz"); }
|
||||
microVUf(void) mVU_SUBAw() { mVU_FMAC5 (SUB, "SUBAw"); }
|
||||
microVUf(void) mVU_MUL() { mVU_FMAC1 (MUL, "MUL"); }
|
||||
microVUf(void) mVU_MULi() { mVU_FMAC6 (MUL, "MULi"); }
|
||||
microVUf(void) mVU_MULq() { mVU_FMAC22(MUL, "MULq"); }
|
||||
microVUf(void) mVU_MULx() { mVU_FMAC3 (MUL, "MULx"); }
|
||||
microVUf(void) mVU_MULy() { mVU_FMAC3 (MUL, "MULy"); }
|
||||
microVUf(void) mVU_MULz() { mVU_FMAC3 (MUL, "MULz"); }
|
||||
microVUf(void) mVU_MULw() { mVU_FMAC3 (MUL, "MULw"); }
|
||||
microVUf(void) mVU_MULA() { mVU_FMAC4 (MUL, "MULA"); }
|
||||
microVUf(void) mVU_MULAi() { mVU_FMAC7 (MUL, "MULAi"); }
|
||||
microVUf(void) mVU_MULAq() { mVU_FMAC23(MUL, "MULAq"); }
|
||||
microVUf(void) mVU_MULAx() { mVU_FMAC5 (MUL, "MULAx"); }
|
||||
microVUf(void) mVU_MULAy() { mVU_FMAC5 (MUL, "MULAy"); }
|
||||
microVUf(void) mVU_MULAz() { mVU_FMAC5 (MUL, "MULAz"); }
|
||||
microVUf(void) mVU_MULAw() { mVU_FMAC5 (MUL, "MULAw"); }
|
||||
microVUf(void) mVU_MADD() { mVU_FMAC8 (ADD, "MADD"); }
|
||||
microVUf(void) mVU_MADDi() { mVU_FMAC12(ADD, "MADDi"); }
|
||||
microVUf(void) mVU_MADDq() { mVU_FMAC24(ADD, "MADDq"); }
|
||||
microVUf(void) mVU_MADDx() { mVU_FMAC10(ADD, "MADDx"); }
|
||||
microVUf(void) mVU_MADDy() { mVU_FMAC10(ADD, "MADDy"); }
|
||||
microVUf(void) mVU_MADDz() { mVU_FMAC10(ADD, "MADDz"); }
|
||||
microVUf(void) mVU_MADDw() { mVU_FMAC10(ADD, "MADDw"); }
|
||||
microVUf(void) mVU_MADDA() { mVU_FMAC14(ADD, "MADDA"); }
|
||||
microVUf(void) mVU_MADDAi() { mVU_FMAC16(ADD, "MADDAi"); }
|
||||
microVUf(void) mVU_MADDAq() { mVU_FMAC26(ADD, "MADDAq"); }
|
||||
microVUf(void) mVU_MADDAx() { mVU_FMAC15(ADD, "MADDAx"); }
|
||||
microVUf(void) mVU_MADDAy() { mVU_FMAC15(ADD, "MADDAy"); }
|
||||
microVUf(void) mVU_MADDAz() { mVU_FMAC15(ADD, "MADDAz"); }
|
||||
microVUf(void) mVU_MADDAw() { mVU_FMAC15(ADD, "MADDAw"); }
|
||||
microVUf(void) mVU_MSUB() { mVU_FMAC9 (SUB, "MSUB"); }
|
||||
microVUf(void) mVU_MSUBi() { mVU_FMAC13(SUB, "MSUBi"); }
|
||||
microVUf(void) mVU_MSUBq() { mVU_FMAC25(SUB, "MSUBq"); }
|
||||
microVUf(void) mVU_MSUBx() { mVU_FMAC11(SUB, "MSUBx"); }
|
||||
microVUf(void) mVU_MSUBy() { mVU_FMAC11(SUB, "MSUBy"); }
|
||||
microVUf(void) mVU_MSUBz() { mVU_FMAC11(SUB, "MSUBz"); }
|
||||
microVUf(void) mVU_MSUBw() { mVU_FMAC11(SUB, "MSUBw"); }
|
||||
microVUf(void) mVU_MSUBA() { mVU_FMAC14(SUB, "MSUBA"); }
|
||||
microVUf(void) mVU_MSUBAi() { mVU_FMAC16(SUB, "MSUBAi"); }
|
||||
microVUf(void) mVU_MSUBAq() { mVU_FMAC26(SUB, "MSUBAq"); }
|
||||
microVUf(void) mVU_MSUBAx() { mVU_FMAC15(SUB, "MSUBAx"); }
|
||||
microVUf(void) mVU_MSUBAy() { mVU_FMAC15(SUB, "MSUBAy"); }
|
||||
microVUf(void) mVU_MSUBAz() { mVU_FMAC15(SUB, "MSUBAz"); }
|
||||
microVUf(void) mVU_MSUBAw() { mVU_FMAC15(SUB, "MSUBAw"); }
|
||||
microVUf(void) mVU_MAX() { mVU_FMAC1 (MAX2, "MAX"); }
|
||||
microVUf(void) mVU_MAXi() { mVU_FMAC6 (MAX2, "MAXi"); }
|
||||
microVUf(void) mVU_MAXx() { mVU_FMAC3 (MAX2, "MAXx"); }
|
||||
microVUf(void) mVU_MAXy() { mVU_FMAC3 (MAX2, "MAXy"); }
|
||||
microVUf(void) mVU_MAXz() { mVU_FMAC3 (MAX2, "MAXz"); }
|
||||
microVUf(void) mVU_MAXw() { mVU_FMAC3 (MAX2, "MAXw"); }
|
||||
microVUf(void) mVU_MINI() { mVU_FMAC1 (MIN2, "MINI"); }
|
||||
microVUf(void) mVU_MINIi() { mVU_FMAC6 (MIN2, "MINIi"); }
|
||||
microVUf(void) mVU_MINIx() { mVU_FMAC3 (MIN2, "MINIx"); }
|
||||
microVUf(void) mVU_MINIy() { mVU_FMAC3 (MIN2, "MINIy"); }
|
||||
microVUf(void) mVU_MINIz() { mVU_FMAC3 (MIN2, "MINIz"); }
|
||||
microVUf(void) mVU_MINIw() { mVU_FMAC3 (MIN2, "MINIw"); }
|
||||
microVUf(void) mVU_OPMULA() { mVU_FMAC18(MUL, "OPMULA"); }
|
||||
microVUf(void) mVU_OPMSUB() { mVU_FMAC19(SUB, "OPMSUB"); }
|
||||
microVUf(void) mVU_NOP() { pass3 { mVUlog("NOP"); } }
|
||||
microVUq(void) mVU_FTOIx(uptr addr) {
|
||||
microVU* mVU = mVUx;
|
||||
|
|
|
|||
Loading…
Reference in New Issue