x86emitter: Purge MXCSR mask

We require SSE4, no need to mask away things that are unsupported by
SSE1.

common/emitter/cpudetect.cpp

@@ -59,38 +59,6 @@ x86capabilities::x86capabilities()
 #pragma optimize("", on)
 #endif
 
-// Warning!  We've had problems with the MXCSR detection code causing stack corruption in
-// MSVC PGO builds.  The problem was fixed when I moved the MXCSR code to this function, and
-// moved the recSSE[] array to a global static (it was local to cpudetectInit).  Commented
-// here in case the nutty crash ever re-surfaces. >_<
-// Note: recSSE was deleted
-void x86capabilities::SIMD_EstablishMXCSRmask()
-{
-	if (!hasStreamingSIMDExtensions)
-		return;
-
-	MXCSR_Mask.bitmask = 0xFFBF; // MMX/SSE default
-
-	if (hasStreamingSIMD2Extensions)
-	{
-		// This is generally safe assumption, but FXSAVE is the "correct" way to
-		// detect MXCSR masking features of the cpu, so we use it's result below
-		// and override this.
-
-		MXCSR_Mask.bitmask = 0xFFFF; // SSE2 features added
-	}
-
-	alignas(16) u8 targetFXSAVE[512];
-
-	// Work for recent enough GCC/CLANG/MSVC 2012
-	_fxsave(&targetFXSAVE);
-
-	u32 result;
-	memcpy(&result, &targetFXSAVE[28], 4); // bytes 28->32 are the MXCSR_Mask.
-	if (result != 0)
-		MXCSR_Mask.bitmask = result;
-}
-
 const char* x86capabilities::GetTypeName() const
 {
 	switch (TypeID)

common/emitter/simd.cpp

@@ -5,11 +5,6 @@
 #include "common/emitter/tools.h"
 #include "common/VectorIntrin.h"
 
-// Mask of valid bit fields for the target CPU.  Typically this is either 0xFFFF (SSE2
-// or better) or 0xFFBF (SSE1 and earlier).  Code can ensure a safe/valid MXCSR by
-// AND'ing this mask against an MXCSR prior to LDMXCSR.
-SSE_MXCSR MXCSR_Mask;
-
 const char* EnumToString(SSE_RoundMode sse)
 {
 	switch (sse)
@@ -69,14 +64,6 @@ SSE_MXCSR& SSE_MXCSR::DisableExceptions()
 	return *this;
 }
 
-// Applies the reserve bits mask for the current running cpu, as fetched from the CPU
-// during CPU init/detection.
-SSE_MXCSR& SSE_MXCSR::ApplyReserveMask()
-{
-	bitmask &= MXCSR_Mask.bitmask;
-	return *this;
-}
-
 SSE_MXCSR::operator x86Emitter::xIndirect32() const
 {
 	return x86Emitter::ptr32[&bitmask];

common/emitter/tools.h

@@ -104,8 +104,6 @@ public:
 	void CountCores();
 	const char* GetTypeName() const;
 
-	void SIMD_EstablishMXCSRmask();
-
 protected:
 	void CountLogicalCores();
 };
@@ -153,9 +151,6 @@ union SSE_MXCSR
 			UnderflowFlag : 1,
 			PrecisionFlag : 1,
 
-			// This bit is supported only on SSE2 or better CPUs.  Setting it to 1 on
-			// SSE1 cpus will result in an invalid instruction exception when executing
-			// LDMXSCR.
 			DenormalsAreZero : 1,
 
 			InvalidOpMask : 1,
@@ -178,8 +173,6 @@ union SSE_MXCSR
 	SSE_MXCSR& EnableExceptions();
 	SSE_MXCSR& DisableExceptions();
 
-	SSE_MXCSR& ApplyReserveMask();
-
 	bool operator==(const SSE_MXCSR& right) const
 	{
 		return bitmask == right.bitmask;
@@ -193,7 +186,4 @@ union SSE_MXCSR
 	operator x86Emitter::xIndirect32() const;
 };
 
-extern SSE_MXCSR MXCSR_Mask;
-
-
 alignas(16) extern x86capabilities x86caps;

pcsx2/System.cpp

@@ -53,9 +53,9 @@ void SetCPUState(SSE_MXCSR sseMXCSR, SSE_MXCSR sseVU0MXCSR, SSE_MXCSR sseVU1MXCS
 {
 	//Msgbox::Alert("SetCPUState: Config.sseMXCSR = %x; Config.sseVUMXCSR = %x \n", Config.sseMXCSR, Config.sseVUMXCSR);
 
-	g_sseMXCSR = sseMXCSR.ApplyReserveMask();
+	g_sseMXCSR = sseMXCSR;
-	g_sseVU0MXCSR = sseVU0MXCSR.ApplyReserveMask();
+	g_sseVU0MXCSR = sseVU0MXCSR;
-	g_sseVU1MXCSR = sseVU1MXCSR.ApplyReserveMask();
+	g_sseVU1MXCSR = sseVU1MXCSR;
 
 	_mm_setcsr(g_sseMXCSR.bitmask);
 }

pcsx2/VMManager.cpp

@@ -344,7 +344,6 @@ bool VMManager::Internal::CPUThreadInitialize()
 
 	x86caps.Identify();
 	x86caps.CountCores();
-	x86caps.SIMD_EstablishMXCSRmask();
 	SysLogMachineCaps();
 
 	if (!SysMemory::Allocate())