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VU Int: Clang formatting

This commit is contained in:
refractionpcsx2 2021-09-12 15:57:43 +01:00
parent 52943d8399
commit b0d1d4ff44
2 changed files with 1253 additions and 886 deletions
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72
pcsx2/VU0microInterp.cpp
View File

@ -23,13 +23,15 @@
extern void _vuFlushAll(VURegs* VU);
static void _vu0ExecUpper(VURegs* VU, u32 *ptr) {
static void _vu0ExecUpper(VURegs* VU, u32* ptr)
{
VU->code = ptr[1];
IdebugUPPER(VU0);
VU0_UPPER_OPCODE[VU->code & 0x3f]();
}
static void _vu0ExecLower(VURegs* VU, u32 *ptr) {
static void _vu0ExecLower(VURegs* VU, u32* ptr)
{
VU->code = ptr[0];
IdebugLOWER(VU0);
VU0_LOWER_OPCODE[VU->code >> 25]();
@ -40,10 +42,10 @@ static void _vu0Exec(VURegs* VU)
{
_VURegsNum lregs;
_VURegsNum uregs;
u32 *ptr;
u32* ptr;
ptr = (u32*)&VU->Micro[VU->VI[REG_TPC].UL];
VU->VI[REG_TPC].UL+=8;
VU->VI[REG_TPC].UL += 8;
if (ptr[1] & 0x40000000) // E flag
{
@ -51,33 +53,33 @@ static void _vu0Exec(VURegs* VU)
}
if (ptr[1] & 0x20000000 && VU == &VU0) // M flag
{
VU->flags|= VUFLAG_MFLAGSET;
VU->flags |= VUFLAG_MFLAGSET;
VU0.blockhasmbit = true;
// Console.WriteLn("fixme: M flag set");
// Console.WriteLn("fixme: M flag set");
}
if (ptr[1] & 0x10000000) // D flag
{
if (VU0.VI[REG_FBRST].UL & 0x4) {
VU0.VI[REG_VPU_STAT].UL|= 0x2;
if (VU0.VI[REG_FBRST].UL & 0x4)
{
VU0.VI[REG_VPU_STAT].UL |= 0x2;
hwIntcIrq(INTC_VU0);
VU->ebit = 1;
}
}
if (ptr[1] & 0x08000000) // T flag
{
if (VU0.VI[REG_FBRST].UL & 0x8) {
VU0.VI[REG_VPU_STAT].UL|= 0x4;
if (VU0.VI[REG_FBRST].UL & 0x8)
{
VU0.VI[REG_VPU_STAT].UL |= 0x4;
hwIntcIrq(INTC_VU0);
VU->ebit = 1;
}
}
VU->code = ptr[1];
VU0regs_UPPER_OPCODE[VU->code & 0x3f](&uregs);
u32 cyclesBeforeOp = VU0.cycle-1;
u32 cyclesBeforeOp = VU0.cycle - 1;
_vuTestUpperStalls(VU, &uregs);
@ -93,7 +95,7 @@ static void _vu0Exec(VURegs* VU)
VU->VI[REG_I].UL = ptr[0];
memset(&lregs, 0, sizeof(lregs));
}
}
else
{
VECTOR _VF;
@ -118,13 +120,13 @@ static void _vu0Exec(VURegs* VU)
{
if (lregs.VFwrite == uregs.VFwrite)
{
// Console.Warning("*PCSX2*: Warning, VF write to the same reg in both lower/upper cycle");
// Console.Warning("*PCSX2*: Warning, VF write to the same reg in both lower/upper cycle");
discard = 1;
}
if (lregs.VFread0 == uregs.VFwrite ||
lregs.VFread1 == uregs.VFwrite)
{
// Console.WriteLn("saving reg %d at pc=%x", i, VU->VI[REG_TPC].UL);
// Console.WriteLn("saving reg %d at pc=%x", i, VU->VI[REG_TPC].UL);
_VF = VU->VF[uregs.VFwrite];
vfreg = uregs.VFwrite;
}
@ -185,7 +187,7 @@ static void _vu0Exec(VURegs* VU)
VU->blockhasmbit = false;
if(VU->takedelaybranch)
if (VU->takedelaybranch)
{
DevCon.Warning("VU0 - Branch/Jump in Delay Slot");
VU->branch = 1;
@ -195,13 +197,13 @@ static void _vu0Exec(VURegs* VU)
}
}
if(VU->ebit > 0)
if (VU->ebit > 0)
{
if(VU->ebit-- == 1)
if (VU->ebit-- == 1)
{
VU->VIBackupCycles = 0;
_vuFlushAll(VU);
VU0.VI[REG_VPU_STAT].UL&= ~0x1; /* E flag */
VU0.VI[REG_VPU_STAT].UL &= ~0x1; /* E flag */
vif0Regs.stat.VEW = false;
VU->blockhasmbit = false;
@ -219,11 +221,16 @@ void vu0Exec(VURegs* VU)
VU->cycle++;
_vu0Exec(VU);
if (VU->VI[0].UL != 0) DbgCon.Error("VI[0] != 0!!!!\n");
if (VU->VF[0].f.x != 0.0f) DbgCon.Error("VF[0].x != 0.0!!!!\n");
if (VU->VF[0].f.y != 0.0f) DbgCon.Error("VF[0].y != 0.0!!!!\n");
if (VU->VF[0].f.z != 0.0f) DbgCon.Error("VF[0].z != 0.0!!!!\n");
if (VU->VF[0].f.w != 1.0f) DbgCon.Error("VF[0].w != 1.0!!!!\n");
if (VU->VI[0].UL != 0)
DbgCon.Error("VI[0] != 0!!!!\n");
if (VU->VF[0].f.x != 0.0f)
DbgCon.Error("VF[0].x != 0.0!!!!\n");
if (VU->VF[0].f.y != 0.0f)
DbgCon.Error("VF[0].y != 0.0!!!!\n");
if (VU->VF[0].f.z != 0.0f)
DbgCon.Error("VF[0].z != 0.0!!!!\n");
if (VU->VF[0].f.w != 1.0f)
DbgCon.Error("VF[0].w != 1.0!!!!\n");
}
// --------------------------------------------------------------------------------------
@ -244,7 +251,6 @@ void InterpVU0::Reset()
VU0.ialuwritepos = 0;
VU0.ialureadpos = 0;
VU0.ialucount = 0;
}
void InterpVU0::SetStartPC(u32 startPC)
{
@ -253,7 +259,7 @@ void InterpVU0::SetStartPC(u32 startPC)
void InterpVU0::Step()
{
vu0Exec( &VU0 );
vu0Exec(&VU0);
}
void InterpVU0::Execute(u32 cycles)
@ -264,10 +270,13 @@ void InterpVU0::Execute(u32 cycles)
VU0.VI[REG_TPC].UL <<= 3;
VU0.flags &= ~VUFLAG_MFLAGSET;
u32 startcycles = VU0.cycle;
while((VU0.cycle - startcycles) < cycles) {
if (!(VU0.VI[REG_VPU_STAT].UL & 0x1)) {
while ((VU0.cycle - startcycles) < cycles)
{
if (!(VU0.VI[REG_VPU_STAT].UL & 0x1))
{
// Branches advance the PC to the new location if there was a branch in the E-Bit delay slot
if (VU0.branch) {
if (VU0.branch)
{
VU0.VI[REG_TPC].UL = VU0.branchpc;
VU0.branch = 0;
}
@ -275,6 +284,7 @@ void InterpVU0::Execute(u32 cycles)
}
if (VU0.flags & VUFLAG_MFLAGSET)
break;
vu0Exec(&VU0);
}
VU0.VI[REG_TPC].UL >>= 3;

2067
pcsx2/VUops.cpp
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