diff --git a/3rdparty/cpuinfo/CMakeLists.txt b/3rdparty/cpuinfo/CMakeLists.txt index 914273bc56..d8d514ad03 100644 --- a/3rdparty/cpuinfo/CMakeLists.txt +++ b/3rdparty/cpuinfo/CMakeLists.txt @@ -67,6 +67,9 @@ ENDIF() # -- [ Determine target processor SET(CPUINFO_TARGET_PROCESSOR "${CMAKE_SYSTEM_PROCESSOR}") +IF(CMAKE_SYSTEM_NAME MATCHES "FreeBSD" AND CPUINFO_TARGET_PROCESSOR STREQUAL "amd64") + SET(CPUINFO_TARGET_PROCESSOR "AMD64") +ENDIF() IF(IS_APPLE_OS AND CMAKE_OSX_ARCHITECTURES MATCHES "^(x86_64|arm64.*)$") SET(CPUINFO_TARGET_PROCESSOR "${CMAKE_OSX_ARCHITECTURES}") ELSEIF(CMAKE_GENERATOR MATCHES "^Visual Studio " AND CMAKE_VS_PLATFORM_NAME) @@ -105,7 +108,7 @@ IF(NOT CMAKE_SYSTEM_NAME) "Target operating system is not specified. " "cpuinfo will compile, but cpuinfo_initialize() will always fail.") SET(CPUINFO_SUPPORTED_PLATFORM FALSE) -ELSEIF(NOT CMAKE_SYSTEM_NAME MATCHES "^(Windows|WindowsStore|CYGWIN|MSYS|Darwin|Linux|Android)$") +ELSEIF(NOT CMAKE_SYSTEM_NAME MATCHES "^(Windows|WindowsStore|CYGWIN|MSYS|Darwin|Linux|Android|FreeBSD)$") IF(${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.14" AND NOT IS_APPLE_OS) MESSAGE(WARNING "Target operating system \"${CMAKE_SYSTEM_NAME}\" is not supported in cpuinfo. " @@ -178,6 +181,8 @@ IF(CPUINFO_SUPPORTED_PLATFORM) LIST(APPEND CPUINFO_SRCS src/x86/mach/init.c) ELSEIF(CMAKE_SYSTEM_NAME MATCHES "^(Windows|WindowsStore|CYGWIN|MSYS)$") LIST(APPEND CPUINFO_SRCS src/x86/windows/init.c) + ELSEIF(CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") + LIST(APPEND CPUINFO_SRCS src/x86/freebsd/init.c) ENDIF() ELSEIF(CMAKE_SYSTEM_NAME MATCHES "^Windows" AND CPUINFO_TARGET_PROCESSOR MATCHES "^(ARM64|arm64)$") LIST(APPEND CPUINFO_SRCS @@ -234,9 +239,11 @@ IF(CPUINFO_SUPPORTED_PLATFORM) src/linux/processors.c) ELSEIF(IS_APPLE_OS) LIST(APPEND CPUINFO_SRCS src/mach/topology.c) + ELSEIF(CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") + LIST(APPEND CPUINFO_SRCS src/freebsd/topology.c) ENDIF() - IF(CMAKE_SYSTEM_NAME STREQUAL "Linux" OR CMAKE_SYSTEM_NAME STREQUAL "Android") + IF(CMAKE_SYSTEM_NAME STREQUAL "Linux" OR CMAKE_SYSTEM_NAME STREQUAL "Android" OR CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") SET(CMAKE_THREAD_PREFER_PTHREAD TRUE) SET(THREADS_PREFER_PTHREAD_FLAG TRUE) FIND_PACKAGE(Threads REQUIRED) @@ -301,6 +308,9 @@ IF(CPUINFO_SUPPORTED_PLATFORM) TARGET_LINK_LIBRARIES(cpuinfo_internals PUBLIC ${CMAKE_THREAD_LIBS_INIT}) TARGET_COMPILE_DEFINITIONS(cpuinfo PRIVATE _GNU_SOURCE=1) TARGET_COMPILE_DEFINITIONS(cpuinfo_internals PRIVATE _GNU_SOURCE=1) + ELSEIF(CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") + TARGET_LINK_LIBRARIES(cpuinfo PUBLIC ${CMAKE_THREAD_LIBS_INIT}) + TARGET_LINK_LIBRARIES(cpuinfo_internals PUBLIC ${CMAKE_THREAD_LIBS_INIT}) ENDIF() ELSE() TARGET_COMPILE_DEFINITIONS(cpuinfo INTERFACE CPUINFO_SUPPORTED_PLATFORM=0) diff --git a/3rdparty/cpuinfo/include/cpuinfo-mock.h b/3rdparty/cpuinfo/include/cpuinfo-mock.h index 3c1f637d9e..5e129aa659 100644 --- a/3rdparty/cpuinfo/include/cpuinfo-mock.h +++ b/3rdparty/cpuinfo/include/cpuinfo-mock.h @@ -7,37 +7,35 @@ #include #if defined(__linux__) - #include +#include #endif #if !defined(CPUINFO_MOCK) || !(CPUINFO_MOCK) - #error This header is intended only for test use +#error This header is intended only for test use #endif - #ifdef __cplusplus extern "C" { #endif - #if CPUINFO_ARCH_ARM - void CPUINFO_ABI cpuinfo_set_fpsid(uint32_t fpsid); - void CPUINFO_ABI cpuinfo_set_wcid(uint32_t wcid); +void CPUINFO_ABI cpuinfo_set_fpsid(uint32_t fpsid); +void CPUINFO_ABI cpuinfo_set_wcid(uint32_t wcid); #endif /* CPUINFO_ARCH_ARM */ #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - struct cpuinfo_mock_cpuid { - uint32_t input_eax; - uint32_t input_ecx; - uint32_t eax; - uint32_t ebx; - uint32_t ecx; - uint32_t edx; - }; +struct cpuinfo_mock_cpuid { + uint32_t input_eax; + uint32_t input_ecx; + uint32_t eax; + uint32_t ebx; + uint32_t ecx; + uint32_t edx; +}; - void CPUINFO_ABI cpuinfo_mock_set_cpuid(struct cpuinfo_mock_cpuid* dump, size_t entries); - void CPUINFO_ABI cpuinfo_mock_get_cpuid(uint32_t eax, uint32_t regs[4]); - void CPUINFO_ABI cpuinfo_mock_get_cpuidex(uint32_t eax, uint32_t ecx, uint32_t regs[4]); +void CPUINFO_ABI cpuinfo_mock_set_cpuid(struct cpuinfo_mock_cpuid* dump, size_t entries); +void CPUINFO_ABI cpuinfo_mock_get_cpuid(uint32_t eax, uint32_t regs[4]); +void CPUINFO_ABI cpuinfo_mock_get_cpuidex(uint32_t eax, uint32_t ecx, uint32_t regs[4]); #endif /* CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 */ struct cpuinfo_mock_file { @@ -53,22 +51,22 @@ struct cpuinfo_mock_property { }; #if defined(__linux__) - void CPUINFO_ABI cpuinfo_mock_filesystem(struct cpuinfo_mock_file* files); - int CPUINFO_ABI cpuinfo_mock_open(const char* path, int oflag); - int CPUINFO_ABI cpuinfo_mock_close(int fd); - ssize_t CPUINFO_ABI cpuinfo_mock_read(int fd, void* buffer, size_t capacity); +void CPUINFO_ABI cpuinfo_mock_filesystem(struct cpuinfo_mock_file* files); +int CPUINFO_ABI cpuinfo_mock_open(const char* path, int oflag); +int CPUINFO_ABI cpuinfo_mock_close(int fd); +ssize_t CPUINFO_ABI cpuinfo_mock_read(int fd, void* buffer, size_t capacity); - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - void CPUINFO_ABI cpuinfo_set_hwcap(uint32_t hwcap); - #endif - #if CPUINFO_ARCH_ARM - void CPUINFO_ABI cpuinfo_set_hwcap2(uint32_t hwcap2); - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 +void CPUINFO_ABI cpuinfo_set_hwcap(uint32_t hwcap); +#endif +#if CPUINFO_ARCH_ARM +void CPUINFO_ABI cpuinfo_set_hwcap2(uint32_t hwcap2); +#endif #endif #if defined(__ANDROID__) - void CPUINFO_ABI cpuinfo_mock_android_properties(struct cpuinfo_mock_property* properties); - void CPUINFO_ABI cpuinfo_mock_gl_renderer(const char* renderer); +void CPUINFO_ABI cpuinfo_mock_android_properties(struct cpuinfo_mock_property* properties); +void CPUINFO_ABI cpuinfo_mock_gl_renderer(const char* renderer); #endif #ifdef __cplusplus diff --git a/3rdparty/cpuinfo/include/cpuinfo.h b/3rdparty/cpuinfo/include/cpuinfo.h index 3fbcad2a08..2d74b62fd6 100644 --- a/3rdparty/cpuinfo/include/cpuinfo.h +++ b/3rdparty/cpuinfo/include/cpuinfo.h @@ -3,11 +3,11 @@ #define CPUINFO_H #ifndef __cplusplus - #include +#include #endif #ifdef __APPLE__ - #include +#include #endif #include @@ -15,97 +15,97 @@ /* Identify architecture and define corresponding macro */ #if defined(__i386__) || defined(__i486__) || defined(__i586__) || defined(__i686__) || defined(_M_IX86) - #define CPUINFO_ARCH_X86 1 +#define CPUINFO_ARCH_X86 1 #endif #if defined(__x86_64__) || defined(__x86_64) || defined(_M_X64) || defined(_M_AMD64) - #define CPUINFO_ARCH_X86_64 1 +#define CPUINFO_ARCH_X86_64 1 #endif #if defined(__arm__) || defined(_M_ARM) - #define CPUINFO_ARCH_ARM 1 +#define CPUINFO_ARCH_ARM 1 #endif #if defined(__aarch64__) || defined(_M_ARM64) - #define CPUINFO_ARCH_ARM64 1 +#define CPUINFO_ARCH_ARM64 1 #endif #if defined(__PPC64__) || defined(__powerpc64__) || defined(_ARCH_PPC64) - #define CPUINFO_ARCH_PPC64 1 +#define CPUINFO_ARCH_PPC64 1 #endif #if defined(__asmjs__) - #define CPUINFO_ARCH_ASMJS 1 +#define CPUINFO_ARCH_ASMJS 1 #endif #if defined(__wasm__) - #if defined(__wasm_simd128__) - #define CPUINFO_ARCH_WASMSIMD 1 - #else - #define CPUINFO_ARCH_WASM 1 - #endif +#if defined(__wasm_simd128__) +#define CPUINFO_ARCH_WASMSIMD 1 +#else +#define CPUINFO_ARCH_WASM 1 +#endif #endif #if defined(__riscv) - #if (__riscv_xlen == 32) - #define CPUINFO_ARCH_RISCV32 1 - #elif (__riscv_xlen == 64) - #define CPUINFO_ARCH_RISCV64 1 - #endif +#if (__riscv_xlen == 32) +#define CPUINFO_ARCH_RISCV32 1 +#elif (__riscv_xlen == 64) +#define CPUINFO_ARCH_RISCV64 1 +#endif #endif /* Define other architecture-specific macros as 0 */ #ifndef CPUINFO_ARCH_X86 - #define CPUINFO_ARCH_X86 0 +#define CPUINFO_ARCH_X86 0 #endif #ifndef CPUINFO_ARCH_X86_64 - #define CPUINFO_ARCH_X86_64 0 +#define CPUINFO_ARCH_X86_64 0 #endif #ifndef CPUINFO_ARCH_ARM - #define CPUINFO_ARCH_ARM 0 +#define CPUINFO_ARCH_ARM 0 #endif #ifndef CPUINFO_ARCH_ARM64 - #define CPUINFO_ARCH_ARM64 0 +#define CPUINFO_ARCH_ARM64 0 #endif #ifndef CPUINFO_ARCH_PPC64 - #define CPUINFO_ARCH_PPC64 0 +#define CPUINFO_ARCH_PPC64 0 #endif #ifndef CPUINFO_ARCH_ASMJS - #define CPUINFO_ARCH_ASMJS 0 +#define CPUINFO_ARCH_ASMJS 0 #endif #ifndef CPUINFO_ARCH_WASM - #define CPUINFO_ARCH_WASM 0 +#define CPUINFO_ARCH_WASM 0 #endif #ifndef CPUINFO_ARCH_WASMSIMD - #define CPUINFO_ARCH_WASMSIMD 0 +#define CPUINFO_ARCH_WASMSIMD 0 #endif #ifndef CPUINFO_ARCH_RISCV32 - #define CPUINFO_ARCH_RISCV32 0 +#define CPUINFO_ARCH_RISCV32 0 #endif #ifndef CPUINFO_ARCH_RISCV64 - #define CPUINFO_ARCH_RISCV64 0 +#define CPUINFO_ARCH_RISCV64 0 #endif #if CPUINFO_ARCH_X86 && defined(_MSC_VER) - #define CPUINFO_ABI __cdecl +#define CPUINFO_ABI __cdecl #elif CPUINFO_ARCH_X86 && defined(__GNUC__) - #define CPUINFO_ABI __attribute__((__cdecl__)) +#define CPUINFO_ABI __attribute__((__cdecl__)) #else - #define CPUINFO_ABI +#define CPUINFO_ABI #endif -#define CPUINFO_CACHE_UNIFIED 0x00000001 -#define CPUINFO_CACHE_INCLUSIVE 0x00000002 +#define CPUINFO_CACHE_UNIFIED 0x00000001 +#define CPUINFO_CACHE_INCLUSIVE 0x00000002 #define CPUINFO_CACHE_COMPLEX_INDEXING 0x00000004 struct cpuinfo_cache { @@ -120,9 +120,11 @@ struct cpuinfo_cache { /** Line size in bytes */ uint32_t line_size; /** - * Binary characteristics of the cache (unified cache, inclusive cache, cache with complex indexing). + * Binary characteristics of the cache (unified cache, inclusive cache, + * cache with complex indexing). * - * @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE, CPUINFO_CACHE_COMPLEX_INDEXING + * @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE, + * CPUINFO_CACHE_COMPLEX_INDEXING */ uint32_t flags; /** Index of the first logical processor that shares this cache */ @@ -136,12 +138,12 @@ struct cpuinfo_trace_cache { uint32_t associativity; }; -#define CPUINFO_PAGE_SIZE_4KB 0x1000 -#define CPUINFO_PAGE_SIZE_1MB 0x100000 -#define CPUINFO_PAGE_SIZE_2MB 0x200000 -#define CPUINFO_PAGE_SIZE_4MB 0x400000 +#define CPUINFO_PAGE_SIZE_4KB 0x1000 +#define CPUINFO_PAGE_SIZE_1MB 0x100000 +#define CPUINFO_PAGE_SIZE_2MB 0x200000 +#define CPUINFO_PAGE_SIZE_4MB 0x400000 #define CPUINFO_PAGE_SIZE_16MB 0x1000000 -#define CPUINFO_PAGE_SIZE_1GB 0x40000000 +#define CPUINFO_PAGE_SIZE_1GB 0x40000000 struct cpuinfo_tlb { uint32_t entries; @@ -151,74 +153,95 @@ struct cpuinfo_tlb { /** Vendor of processor core design */ enum cpuinfo_vendor { - /** Processor vendor is not known to the library, or the library failed to get vendor information from the OS. */ + /** Processor vendor is not known to the library, or the library failed + to get vendor information from the OS. */ cpuinfo_vendor_unknown = 0, /* Active vendors of modern CPUs */ /** - * Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor microarchitectures. + * Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor + * microarchitectures. * - * Sold its ARM design subsidiary in 2006. The last ARM processor design was released in 2004. + * Sold its ARM design subsidiary in 2006. The last ARM processor design + * was released in 2004. */ - cpuinfo_vendor_intel = 1, - /** Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor microarchitectures. */ - cpuinfo_vendor_amd = 2, - /** ARM Holdings plc. Vendor of ARM and ARM64 processor microarchitectures. */ - cpuinfo_vendor_arm = 3, - /** Qualcomm Incorporated. Vendor of ARM and ARM64 processor microarchitectures. */ + cpuinfo_vendor_intel = 1, + /** Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor + microarchitectures. */ + cpuinfo_vendor_amd = 2, + /** ARM Holdings plc. Vendor of ARM and ARM64 processor + microarchitectures. */ + cpuinfo_vendor_arm = 3, + /** Qualcomm Incorporated. Vendor of ARM and ARM64 processor + microarchitectures. */ cpuinfo_vendor_qualcomm = 4, /** Apple Inc. Vendor of ARM and ARM64 processor microarchitectures. */ - cpuinfo_vendor_apple = 5, - /** Samsung Electronics Co., Ltd. Vendir if ARM64 processor microarchitectures. */ - cpuinfo_vendor_samsung = 6, - /** Nvidia Corporation. Vendor of ARM64-compatible processor microarchitectures. */ - cpuinfo_vendor_nvidia = 7, - /** MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures. */ - cpuinfo_vendor_mips = 8, - /** International Business Machines Corporation. Vendor of PowerPC processor microarchitectures. */ - cpuinfo_vendor_ibm = 9, - /** Ingenic Semiconductor. Vendor of MIPS processor microarchitectures. */ - cpuinfo_vendor_ingenic = 10, - /** - * VIA Technologies, Inc. Vendor of x86 and x86-64 processor microarchitectures. - * - * Processors are designed by Centaur Technology, a subsidiary of VIA Technologies. + cpuinfo_vendor_apple = 5, + /** Samsung Electronics Co., Ltd. Vendir if ARM64 processor + microarchitectures. */ + cpuinfo_vendor_samsung = 6, + /** Nvidia Corporation. Vendor of ARM64-compatible processor + microarchitectures. */ + cpuinfo_vendor_nvidia = 7, + /** MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures. */ - cpuinfo_vendor_via = 11, + cpuinfo_vendor_mips = 8, + /** International Business Machines Corporation. Vendor of PowerPC + processor microarchitectures. */ + cpuinfo_vendor_ibm = 9, + /** Ingenic Semiconductor. Vendor of MIPS processor microarchitectures. + */ + cpuinfo_vendor_ingenic = 10, + /** + * VIA Technologies, Inc. Vendor of x86 and x86-64 processor + * microarchitectures. + * + * Processors are designed by Centaur Technology, a subsidiary of VIA + * Technologies. + */ + cpuinfo_vendor_via = 11, /** Cavium, Inc. Vendor of ARM64 processor microarchitectures. */ - cpuinfo_vendor_cavium = 12, + cpuinfo_vendor_cavium = 12, /** Broadcom, Inc. Vendor of ARM processor microarchitectures. */ cpuinfo_vendor_broadcom = 13, - /** Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor microarchitectures. */ - cpuinfo_vendor_apm = 14, + /** Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor + microarchitectures. */ + cpuinfo_vendor_apm = 14, /** - * Huawei Technologies Co., Ltd. Vendor of ARM64 processor microarchitectures. + * Huawei Technologies Co., Ltd. Vendor of ARM64 processor + * microarchitectures. * * Processors are designed by HiSilicon, a subsidiary of Huawei. */ - cpuinfo_vendor_huawei = 15, + cpuinfo_vendor_huawei = 15, /** - * Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor of x86-64 processor microarchitectures. + * Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor + * of x86-64 processor microarchitectures. * * Processors are variants of AMD cores. */ - cpuinfo_vendor_hygon = 16, + cpuinfo_vendor_hygon = 16, /** SiFive, Inc. Vendor of RISC-V processor microarchitectures. */ - cpuinfo_vendor_sifive = 17, + cpuinfo_vendor_sifive = 17, /* Active vendors of embedded CPUs */ - /** Texas Instruments Inc. Vendor of ARM processor microarchitectures. */ + /** Texas Instruments Inc. Vendor of ARM processor microarchitectures. + */ cpuinfo_vendor_texas_instruments = 30, - /** Marvell Technology Group Ltd. Vendor of ARM processor microarchitectures. */ - cpuinfo_vendor_marvell = 31, - /** RDC Semiconductor Co., Ltd. Vendor of x86 processor microarchitectures. */ - cpuinfo_vendor_rdc = 32, + /** Marvell Technology Group Ltd. Vendor of ARM processor + * microarchitectures. + */ + cpuinfo_vendor_marvell = 31, + /** RDC Semiconductor Co., Ltd. Vendor of x86 processor + microarchitectures. */ + cpuinfo_vendor_rdc = 32, /** DM&P Electronics Inc. Vendor of x86 processor microarchitectures. */ - cpuinfo_vendor_dmp = 33, - /** Motorola, Inc. Vendor of PowerPC and ARM processor microarchitectures. */ - cpuinfo_vendor_motorola = 34, + cpuinfo_vendor_dmp = 33, + /** Motorola, Inc. Vendor of PowerPC and ARM processor + microarchitectures. */ + cpuinfo_vendor_motorola = 34, /* Defunct CPU vendors */ @@ -226,7 +249,8 @@ enum cpuinfo_vendor { * Transmeta Corporation. Vendor of x86 processor microarchitectures. * * Now defunct. The last processor design was released in 2004. - * Transmeta processors implemented VLIW ISA and used binary translation to execute x86 code. + * Transmeta processors implemented VLIW ISA and used binary translation + * to execute x86 code. */ cpuinfo_vendor_transmeta = 50, /** @@ -234,133 +258,144 @@ enum cpuinfo_vendor { * * Now defunct. The last processor design was released in 1996. */ - cpuinfo_vendor_cyrix = 51, + cpuinfo_vendor_cyrix = 51, /** * Rise Technology. Vendor of x86 processor microarchitectures. * * Now defunct. The last processor design was released in 1999. */ - cpuinfo_vendor_rise = 52, + cpuinfo_vendor_rise = 52, /** * National Semiconductor. Vendor of x86 processor microarchitectures. * - * Sold its x86 design subsidiary in 1999. The last processor design was released in 1998. + * Sold its x86 design subsidiary in 1999. The last processor design was + * released in 1998. */ - cpuinfo_vendor_nsc = 53, + cpuinfo_vendor_nsc = 53, /** - * Silicon Integrated Systems. Vendor of x86 processor microarchitectures. + * Silicon Integrated Systems. Vendor of x86 processor + * microarchitectures. * - * Sold its x86 design subsidiary in 2001. The last processor design was released in 2001. + * Sold its x86 design subsidiary in 2001. The last processor design was + * released in 2001. */ - cpuinfo_vendor_sis = 54, + cpuinfo_vendor_sis = 54, /** * NexGen. Vendor of x86 processor microarchitectures. * * Now defunct. The last processor design was released in 1994. - * NexGen designed the first x86 microarchitecture which decomposed x86 instructions into simple microoperations. + * NexGen designed the first x86 microarchitecture which decomposed x86 + * instructions into simple microoperations. */ - cpuinfo_vendor_nexgen = 55, + cpuinfo_vendor_nexgen = 55, /** - * United Microelectronics Corporation. Vendor of x86 processor microarchitectures. + * United Microelectronics Corporation. Vendor of x86 processor + * microarchitectures. * - * Ceased x86 in the early 1990s. The last processor design was released in 1991. - * Designed U5C and U5D processors. Both are 486 level. + * Ceased x86 in the early 1990s. The last processor design was released + * in 1991. Designed U5C and U5D processors. Both are 486 level. */ - cpuinfo_vendor_umc = 56, + cpuinfo_vendor_umc = 56, /** - * Digital Equipment Corporation. Vendor of ARM processor microarchitecture. + * Digital Equipment Corporation. Vendor of ARM processor + * microarchitecture. * - * Sold its ARM designs in 1997. The last processor design was released in 1997. + * Sold its ARM designs in 1997. The last processor design was released + * in 1997. */ - cpuinfo_vendor_dec = 57, + cpuinfo_vendor_dec = 57, }; /** * Processor microarchitecture * - * Processors with different microarchitectures often have different instruction performance characteristics, - * and may have dramatically different pipeline organization. + * Processors with different microarchitectures often have different instruction + * performance characteristics, and may have dramatically different pipeline + * organization. */ enum cpuinfo_uarch { - /** Microarchitecture is unknown, or the library failed to get information about the microarchitecture from OS */ + /** Microarchitecture is unknown, or the library failed to get + information about the microarchitecture from OS */ cpuinfo_uarch_unknown = 0, /** Pentium and Pentium MMX microarchitecture. */ - cpuinfo_uarch_p5 = 0x00100100, + cpuinfo_uarch_p5 = 0x00100100, /** Intel Quark microarchitecture. */ cpuinfo_uarch_quark = 0x00100101, /** Pentium Pro, Pentium II, and Pentium III. */ - cpuinfo_uarch_p6 = 0x00100200, + cpuinfo_uarch_p6 = 0x00100200, /** Pentium M. */ - cpuinfo_uarch_dothan = 0x00100201, + cpuinfo_uarch_dothan = 0x00100201, /** Intel Core microarchitecture. */ - cpuinfo_uarch_yonah = 0x00100202, + cpuinfo_uarch_yonah = 0x00100202, /** Intel Core 2 microarchitecture on 65 nm process. */ - cpuinfo_uarch_conroe = 0x00100203, + cpuinfo_uarch_conroe = 0x00100203, /** Intel Core 2 microarchitecture on 45 nm process. */ - cpuinfo_uarch_penryn = 0x00100204, - /** Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st gen). */ - cpuinfo_uarch_nehalem = 0x00100205, + cpuinfo_uarch_penryn = 0x00100204, + /** Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st + gen). */ + cpuinfo_uarch_nehalem = 0x00100205, /** Intel Sandy Bridge microarchitecture (Core i3/i5/i7 2nd gen). */ cpuinfo_uarch_sandy_bridge = 0x00100206, /** Intel Ivy Bridge microarchitecture (Core i3/i5/i7 3rd gen). */ - cpuinfo_uarch_ivy_bridge = 0x00100207, + cpuinfo_uarch_ivy_bridge = 0x00100207, /** Intel Haswell microarchitecture (Core i3/i5/i7 4th gen). */ - cpuinfo_uarch_haswell = 0x00100208, + cpuinfo_uarch_haswell = 0x00100208, /** Intel Broadwell microarchitecture. */ - cpuinfo_uarch_broadwell = 0x00100209, - /** Intel Sky Lake microarchitecture (14 nm, including Kaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake). */ - cpuinfo_uarch_sky_lake = 0x0010020A, + cpuinfo_uarch_broadwell = 0x00100209, + /** Intel Sky Lake microarchitecture (14 nm, including + Kaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake). */ + cpuinfo_uarch_sky_lake = 0x0010020A, /** DEPRECATED (Intel Kaby Lake microarchitecture). */ - cpuinfo_uarch_kaby_lake = 0x0010020A, + cpuinfo_uarch_kaby_lake = 0x0010020A, /** Intel Palm Cove microarchitecture (10 nm, Cannon Lake). */ - cpuinfo_uarch_palm_cove = 0x0010020B, + cpuinfo_uarch_palm_cove = 0x0010020B, /** Intel Sunny Cove microarchitecture (10 nm, Ice Lake). */ - cpuinfo_uarch_sunny_cove = 0x0010020C, + cpuinfo_uarch_sunny_cove = 0x0010020C, /** Pentium 4 with Willamette, Northwood, or Foster cores. */ cpuinfo_uarch_willamette = 0x00100300, /** Pentium 4 with Prescott and later cores. */ - cpuinfo_uarch_prescott = 0x00100301, + cpuinfo_uarch_prescott = 0x00100301, /** Intel Atom on 45 nm process. */ - cpuinfo_uarch_bonnell = 0x00100400, + cpuinfo_uarch_bonnell = 0x00100400, /** Intel Atom on 32 nm process. */ - cpuinfo_uarch_saltwell = 0x00100401, + cpuinfo_uarch_saltwell = 0x00100401, /** Intel Silvermont microarchitecture (22 nm out-of-order Atom). */ - cpuinfo_uarch_silvermont = 0x00100402, + cpuinfo_uarch_silvermont = 0x00100402, /** Intel Airmont microarchitecture (14 nm out-of-order Atom). */ - cpuinfo_uarch_airmont = 0x00100403, + cpuinfo_uarch_airmont = 0x00100403, /** Intel Goldmont microarchitecture (Denverton, Apollo Lake). */ - cpuinfo_uarch_goldmont = 0x00100404, + cpuinfo_uarch_goldmont = 0x00100404, /** Intel Goldmont Plus microarchitecture (Gemini Lake). */ cpuinfo_uarch_goldmont_plus = 0x00100405, /** Intel Knights Ferry HPC boards. */ - cpuinfo_uarch_knights_ferry = 0x00100500, + cpuinfo_uarch_knights_ferry = 0x00100500, /** Intel Knights Corner HPC boards (aka Xeon Phi). */ - cpuinfo_uarch_knights_corner = 0x00100501, + cpuinfo_uarch_knights_corner = 0x00100501, /** Intel Knights Landing microarchitecture (second-gen MIC). */ cpuinfo_uarch_knights_landing = 0x00100502, /** Intel Knights Hill microarchitecture (third-gen MIC). */ - cpuinfo_uarch_knights_hill = 0x00100503, + cpuinfo_uarch_knights_hill = 0x00100503, /** Intel Knights Mill Xeon Phi. */ - cpuinfo_uarch_knights_mill = 0x00100504, + cpuinfo_uarch_knights_mill = 0x00100504, /** Intel/Marvell XScale series. */ cpuinfo_uarch_xscale = 0x00100600, /** AMD K5. */ - cpuinfo_uarch_k5 = 0x00200100, + cpuinfo_uarch_k5 = 0x00200100, /** AMD K6 and alike. */ - cpuinfo_uarch_k6 = 0x00200101, + cpuinfo_uarch_k6 = 0x00200101, /** AMD Athlon and Duron. */ - cpuinfo_uarch_k7 = 0x00200102, + cpuinfo_uarch_k7 = 0x00200102, /** AMD Athlon 64, Opteron 64. */ - cpuinfo_uarch_k8 = 0x00200103, + cpuinfo_uarch_k8 = 0x00200103, /** AMD Family 10h (Barcelona, Istambul, Magny-Cours). */ - cpuinfo_uarch_k10 = 0x00200104, + cpuinfo_uarch_k10 = 0x00200104, /** * AMD Bulldozer microarchitecture * Zambezi FX-series CPUs, Zurich, Valencia and Interlagos Opteron CPUs. @@ -368,46 +403,47 @@ enum cpuinfo_uarch { cpuinfo_uarch_bulldozer = 0x00200105, /** * AMD Piledriver microarchitecture - * Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu Dhabi Opteron CPUs. + * Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu + * Dhabi Opteron CPUs. */ - cpuinfo_uarch_piledriver = 0x00200106, + cpuinfo_uarch_piledriver = 0x00200106, /** AMD Steamroller microarchitecture (Kaveri APUs). */ cpuinfo_uarch_steamroller = 0x00200107, /** AMD Excavator microarchitecture (Carizzo APUs). */ - cpuinfo_uarch_excavator = 0x00200108, + cpuinfo_uarch_excavator = 0x00200108, /** AMD Zen microarchitecture (12/14 nm Ryzen and EPYC CPUs). */ - cpuinfo_uarch_zen = 0x00200109, + cpuinfo_uarch_zen = 0x00200109, /** AMD Zen 2 microarchitecture (7 nm Ryzen and EPYC CPUs). */ - cpuinfo_uarch_zen2 = 0x0020010A, + cpuinfo_uarch_zen2 = 0x0020010A, /** AMD Zen 3 microarchitecture. */ - cpuinfo_uarch_zen3 = 0x0020010B, + cpuinfo_uarch_zen3 = 0x0020010B, /** AMD Zen 4 microarchitecture. */ - cpuinfo_uarch_zen4 = 0x0020010C, + cpuinfo_uarch_zen4 = 0x0020010C, /** NSC Geode and AMD Geode GX and LX. */ - cpuinfo_uarch_geode = 0x00200200, + cpuinfo_uarch_geode = 0x00200200, /** AMD Bobcat mobile microarchitecture. */ cpuinfo_uarch_bobcat = 0x00200201, /** AMD Jaguar mobile microarchitecture. */ cpuinfo_uarch_jaguar = 0x00200202, /** AMD Puma mobile microarchitecture. */ - cpuinfo_uarch_puma = 0x00200203, + cpuinfo_uarch_puma = 0x00200203, /** ARM7 series. */ - cpuinfo_uarch_arm7 = 0x00300100, + cpuinfo_uarch_arm7 = 0x00300100, /** ARM9 series. */ - cpuinfo_uarch_arm9 = 0x00300101, + cpuinfo_uarch_arm9 = 0x00300101, /** ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore. */ cpuinfo_uarch_arm11 = 0x00300102, /** ARM Cortex-A5. */ - cpuinfo_uarch_cortex_a5 = 0x00300205, + cpuinfo_uarch_cortex_a5 = 0x00300205, /** ARM Cortex-A7. */ - cpuinfo_uarch_cortex_a7 = 0x00300207, + cpuinfo_uarch_cortex_a7 = 0x00300207, /** ARM Cortex-A8. */ - cpuinfo_uarch_cortex_a8 = 0x00300208, + cpuinfo_uarch_cortex_a8 = 0x00300208, /** ARM Cortex-A9. */ - cpuinfo_uarch_cortex_a9 = 0x00300209, + cpuinfo_uarch_cortex_a9 = 0x00300209, /** ARM Cortex-A12. */ cpuinfo_uarch_cortex_a12 = 0x00300212, /** ARM Cortex-A15. */ @@ -416,124 +452,125 @@ enum cpuinfo_uarch { cpuinfo_uarch_cortex_a17 = 0x00300217, /** ARM Cortex-A32. */ - cpuinfo_uarch_cortex_a32 = 0x00300332, + cpuinfo_uarch_cortex_a32 = 0x00300332, /** ARM Cortex-A35. */ - cpuinfo_uarch_cortex_a35 = 0x00300335, + cpuinfo_uarch_cortex_a35 = 0x00300335, /** ARM Cortex-A53. */ - cpuinfo_uarch_cortex_a53 = 0x00300353, - /** ARM Cortex-A55 revision 0 (restricted dual-issue capabilities compared to revision 1+). */ + cpuinfo_uarch_cortex_a53 = 0x00300353, + /** ARM Cortex-A55 revision 0 (restricted dual-issue capabilities + compared to revision 1+). */ cpuinfo_uarch_cortex_a55r0 = 0x00300354, /** ARM Cortex-A55. */ - cpuinfo_uarch_cortex_a55 = 0x00300355, + cpuinfo_uarch_cortex_a55 = 0x00300355, /** ARM Cortex-A57. */ - cpuinfo_uarch_cortex_a57 = 0x00300357, + cpuinfo_uarch_cortex_a57 = 0x00300357, /** ARM Cortex-A65. */ - cpuinfo_uarch_cortex_a65 = 0x00300365, + cpuinfo_uarch_cortex_a65 = 0x00300365, /** ARM Cortex-A72. */ - cpuinfo_uarch_cortex_a72 = 0x00300372, + cpuinfo_uarch_cortex_a72 = 0x00300372, /** ARM Cortex-A73. */ - cpuinfo_uarch_cortex_a73 = 0x00300373, + cpuinfo_uarch_cortex_a73 = 0x00300373, /** ARM Cortex-A75. */ - cpuinfo_uarch_cortex_a75 = 0x00300375, + cpuinfo_uarch_cortex_a75 = 0x00300375, /** ARM Cortex-A76. */ - cpuinfo_uarch_cortex_a76 = 0x00300376, + cpuinfo_uarch_cortex_a76 = 0x00300376, /** ARM Cortex-A77. */ - cpuinfo_uarch_cortex_a77 = 0x00300377, + cpuinfo_uarch_cortex_a77 = 0x00300377, /** ARM Cortex-A78. */ - cpuinfo_uarch_cortex_a78 = 0x00300378, + cpuinfo_uarch_cortex_a78 = 0x00300378, /** ARM Neoverse N1. */ - cpuinfo_uarch_neoverse_n1 = 0x00300400, + cpuinfo_uarch_neoverse_n1 = 0x00300400, /** ARM Neoverse E1. */ - cpuinfo_uarch_neoverse_e1 = 0x00300401, + cpuinfo_uarch_neoverse_e1 = 0x00300401, /** ARM Neoverse V1. */ - cpuinfo_uarch_neoverse_v1 = 0x00300402, + cpuinfo_uarch_neoverse_v1 = 0x00300402, /** ARM Neoverse N2. */ - cpuinfo_uarch_neoverse_n2 = 0x00300403, + cpuinfo_uarch_neoverse_n2 = 0x00300403, /** ARM Neoverse V2. */ - cpuinfo_uarch_neoverse_v2 = 0x00300404, + cpuinfo_uarch_neoverse_v2 = 0x00300404, /** ARM Cortex-X1. */ - cpuinfo_uarch_cortex_x1 = 0x00300501, + cpuinfo_uarch_cortex_x1 = 0x00300501, /** ARM Cortex-X2. */ - cpuinfo_uarch_cortex_x2 = 0x00300502, + cpuinfo_uarch_cortex_x2 = 0x00300502, /** ARM Cortex-X3. */ - cpuinfo_uarch_cortex_x3 = 0x00300503, + cpuinfo_uarch_cortex_x3 = 0x00300503, /** ARM Cortex-A510. */ - cpuinfo_uarch_cortex_a510 = 0x00300551, + cpuinfo_uarch_cortex_a510 = 0x00300551, /** ARM Cortex-A710. */ - cpuinfo_uarch_cortex_a710 = 0x00300571, + cpuinfo_uarch_cortex_a710 = 0x00300571, /** ARM Cortex-A715. */ - cpuinfo_uarch_cortex_a715 = 0x00300572, + cpuinfo_uarch_cortex_a715 = 0x00300572, /** Qualcomm Scorpion. */ cpuinfo_uarch_scorpion = 0x00400100, /** Qualcomm Krait. */ - cpuinfo_uarch_krait = 0x00400101, + cpuinfo_uarch_krait = 0x00400101, /** Qualcomm Kryo. */ - cpuinfo_uarch_kryo = 0x00400102, + cpuinfo_uarch_kryo = 0x00400102, /** Qualcomm Falkor. */ - cpuinfo_uarch_falkor = 0x00400103, + cpuinfo_uarch_falkor = 0x00400103, /** Qualcomm Saphira. */ - cpuinfo_uarch_saphira = 0x00400104, + cpuinfo_uarch_saphira = 0x00400104, /** Nvidia Denver. */ - cpuinfo_uarch_denver = 0x00500100, + cpuinfo_uarch_denver = 0x00500100, /** Nvidia Denver 2. */ - cpuinfo_uarch_denver2 = 0x00500101, + cpuinfo_uarch_denver2 = 0x00500101, /** Nvidia Carmel. */ - cpuinfo_uarch_carmel = 0x00500102, + cpuinfo_uarch_carmel = 0x00500102, /** Samsung Exynos M1 (Exynos 8890 big cores). */ cpuinfo_uarch_exynos_m1 = 0x00600100, /** Samsung Exynos M2 (Exynos 8895 big cores). */ cpuinfo_uarch_exynos_m2 = 0x00600101, /** Samsung Exynos M3 (Exynos 9810 big cores). */ - cpuinfo_uarch_exynos_m3 = 0x00600102, + cpuinfo_uarch_exynos_m3 = 0x00600102, /** Samsung Exynos M4 (Exynos 9820 big cores). */ - cpuinfo_uarch_exynos_m4 = 0x00600103, + cpuinfo_uarch_exynos_m4 = 0x00600103, /** Samsung Exynos M5 (Exynos 9830 big cores). */ - cpuinfo_uarch_exynos_m5 = 0x00600104, + cpuinfo_uarch_exynos_m5 = 0x00600104, /* Deprecated synonym for Cortex-A76 */ cpuinfo_uarch_cortex_a76ae = 0x00300376, /* Deprecated names for Exynos. */ cpuinfo_uarch_mongoose_m1 = 0x00600100, cpuinfo_uarch_mongoose_m2 = 0x00600101, - cpuinfo_uarch_meerkat_m3 = 0x00600102, - cpuinfo_uarch_meerkat_m4 = 0x00600103, + cpuinfo_uarch_meerkat_m3 = 0x00600102, + cpuinfo_uarch_meerkat_m4 = 0x00600103, /** Apple A6 and A6X processors. */ - cpuinfo_uarch_swift = 0x00700100, + cpuinfo_uarch_swift = 0x00700100, /** Apple A7 processor. */ - cpuinfo_uarch_cyclone = 0x00700101, + cpuinfo_uarch_cyclone = 0x00700101, /** Apple A8 and A8X processor. */ - cpuinfo_uarch_typhoon = 0x00700102, + cpuinfo_uarch_typhoon = 0x00700102, /** Apple A9 and A9X processor. */ - cpuinfo_uarch_twister = 0x00700103, + cpuinfo_uarch_twister = 0x00700103, /** Apple A10 and A10X processor. */ cpuinfo_uarch_hurricane = 0x00700104, /** Apple A11 processor (big cores). */ - cpuinfo_uarch_monsoon = 0x00700105, + cpuinfo_uarch_monsoon = 0x00700105, /** Apple A11 processor (little cores). */ - cpuinfo_uarch_mistral = 0x00700106, + cpuinfo_uarch_mistral = 0x00700106, /** Apple A12 processor (big cores). */ - cpuinfo_uarch_vortex = 0x00700107, + cpuinfo_uarch_vortex = 0x00700107, /** Apple A12 processor (little cores). */ - cpuinfo_uarch_tempest = 0x00700108, + cpuinfo_uarch_tempest = 0x00700108, /** Apple A13 processor (big cores). */ cpuinfo_uarch_lightning = 0x00700109, /** Apple A13 processor (little cores). */ - cpuinfo_uarch_thunder = 0x0070010A, + cpuinfo_uarch_thunder = 0x0070010A, /** Apple A14 / M1 processor (big cores). */ cpuinfo_uarch_firestorm = 0x0070010B, /** Apple A14 / M1 processor (little cores). */ - cpuinfo_uarch_icestorm = 0x0070010C, + cpuinfo_uarch_icestorm = 0x0070010C, /** Apple A15 / M2 processor (big cores). */ cpuinfo_uarch_avalanche = 0x0070010D, /** Apple A15 / M2 processor (little cores). */ - cpuinfo_uarch_blizzard = 0x0070010E, + cpuinfo_uarch_blizzard = 0x0070010E, /** Cavium ThunderX. */ cpuinfo_uarch_thunderx = 0x00800100, @@ -570,17 +607,20 @@ struct cpuinfo_processor { #if defined(__linux__) /** * Linux-specific ID for the logical processor: - * - Linux kernel exposes information about this logical processor in /sys/devices/system/cpu/cpu/ + * - Linux kernel exposes information about this logical processor in + * /sys/devices/system/cpu/cpu/ * - Bit in the cpu_set_t identifies this logical processor */ int linux_id; #endif #if defined(_WIN32) || defined(__CYGWIN__) - /** Windows-specific ID for the group containing the logical processor. */ + /** Windows-specific ID for the group containing the logical processor. + */ uint16_t windows_group_id; /** * Windows-specific ID of the logical processor within its group: - * - Bit in the KAFFINITY mask identifies this logical processor within its group. + * - Bit in the KAFFINITY mask identifies this + * logical processor within its group. */ uint16_t windows_processor_id; #endif @@ -700,1302 +740,1401 @@ bool CPUINFO_ABI cpuinfo_initialize(void); void CPUINFO_ABI cpuinfo_deinitialize(void); #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - /* This structure is not a part of stable API. Use cpuinfo_has_x86_* functions instead. */ - struct cpuinfo_x86_isa { - #if CPUINFO_ARCH_X86 - bool rdtsc; - #endif - bool rdtscp; - bool rdpid; - bool sysenter; - #if CPUINFO_ARCH_X86 - bool syscall; - #endif - bool msr; - bool clzero; - bool clflush; - bool clflushopt; - bool mwait; - bool mwaitx; - #if CPUINFO_ARCH_X86 - bool emmx; - #endif - bool fxsave; - bool xsave; - #if CPUINFO_ARCH_X86 - bool fpu; - bool mmx; - bool mmx_plus; - #endif - bool three_d_now; - bool three_d_now_plus; - #if CPUINFO_ARCH_X86 - bool three_d_now_geode; - #endif - bool prefetch; - bool prefetchw; - bool prefetchwt1; - #if CPUINFO_ARCH_X86 - bool daz; - bool sse; - bool sse2; - #endif - bool sse3; - bool ssse3; - bool sse4_1; - bool sse4_2; - bool sse4a; - bool misaligned_sse; - bool avx; - bool avxvnni; - bool fma3; - bool fma4; - bool xop; - bool f16c; - bool avx2; - bool avx512f; - bool avx512pf; - bool avx512er; - bool avx512cd; - bool avx512dq; - bool avx512bw; - bool avx512vl; - bool avx512ifma; - bool avx512vbmi; - bool avx512vbmi2; - bool avx512bitalg; - bool avx512vpopcntdq; - bool avx512vnni; - bool avx512bf16; - bool avx512fp16; - bool avx512vp2intersect; - bool avx512_4vnniw; - bool avx512_4fmaps; - bool hle; - bool rtm; - bool xtest; - bool mpx; - #if CPUINFO_ARCH_X86 - bool cmov; - bool cmpxchg8b; - #endif - bool cmpxchg16b; - bool clwb; - bool movbe; - #if CPUINFO_ARCH_X86_64 - bool lahf_sahf; - #endif - bool fs_gs_base; - bool lzcnt; - bool popcnt; - bool tbm; - bool bmi; - bool bmi2; - bool adx; - bool aes; - bool vaes; - bool pclmulqdq; - bool vpclmulqdq; - bool gfni; - bool rdrand; - bool rdseed; - bool sha; - bool rng; - bool ace; - bool ace2; - bool phe; - bool pmm; - bool lwp; - }; +/* This structure is not a part of stable API. Use cpuinfo_has_x86_* functions + * instead. */ +struct cpuinfo_x86_isa { +#if CPUINFO_ARCH_X86 + bool rdtsc; +#endif + bool rdtscp; + bool rdpid; + bool sysenter; +#if CPUINFO_ARCH_X86 + bool syscall; +#endif + bool msr; + bool clzero; + bool clflush; + bool clflushopt; + bool mwait; + bool mwaitx; +#if CPUINFO_ARCH_X86 + bool emmx; +#endif + bool fxsave; + bool xsave; +#if CPUINFO_ARCH_X86 + bool fpu; + bool mmx; + bool mmx_plus; +#endif + bool three_d_now; + bool three_d_now_plus; +#if CPUINFO_ARCH_X86 + bool three_d_now_geode; +#endif + bool prefetch; + bool prefetchw; + bool prefetchwt1; +#if CPUINFO_ARCH_X86 + bool daz; + bool sse; + bool sse2; +#endif + bool sse3; + bool ssse3; + bool sse4_1; + bool sse4_2; + bool sse4a; + bool misaligned_sse; + bool avx; + bool avxvnni; + bool fma3; + bool fma4; + bool xop; + bool f16c; + bool avx2; + bool avx512f; + bool avx512pf; + bool avx512er; + bool avx512cd; + bool avx512dq; + bool avx512bw; + bool avx512vl; + bool avx512ifma; + bool avx512vbmi; + bool avx512vbmi2; + bool avx512bitalg; + bool avx512vpopcntdq; + bool avx512vnni; + bool avx512bf16; + bool avx512fp16; + bool avx512vp2intersect; + bool avx512_4vnniw; + bool avx512_4fmaps; + bool amx_bf16; + bool amx_tile; + bool amx_int8; + bool amx_fp16; + bool avx_vnni_int8; + bool avx_vnni_int16; + bool avx_ne_convert; + bool hle; + bool rtm; + bool xtest; + bool mpx; +#if CPUINFO_ARCH_X86 + bool cmov; + bool cmpxchg8b; +#endif + bool cmpxchg16b; + bool clwb; + bool movbe; +#if CPUINFO_ARCH_X86_64 + bool lahf_sahf; +#endif + bool fs_gs_base; + bool lzcnt; + bool popcnt; + bool tbm; + bool bmi; + bool bmi2; + bool adx; + bool aes; + bool vaes; + bool pclmulqdq; + bool vpclmulqdq; + bool gfni; + bool rdrand; + bool rdseed; + bool sha; + bool rng; + bool ace; + bool ace2; + bool phe; + bool pmm; + bool lwp; +}; - extern struct cpuinfo_x86_isa cpuinfo_isa; +extern struct cpuinfo_x86_isa cpuinfo_isa; #endif static inline bool cpuinfo_has_x86_rdtsc(void) { - #if CPUINFO_ARCH_X86_64 - return true; - #elif CPUINFO_ARCH_X86 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.rdtsc; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return true; +#elif CPUINFO_ARCH_X86 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.rdtsc; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_rdtscp(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.rdtscp; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.rdtscp; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_rdpid(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.rdpid; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.rdpid; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_clzero(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.clzero; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.clzero; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_mwait(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.mwait; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.mwait; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_mwaitx(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.mwaitx; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.mwaitx; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_fxsave(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.fxsave; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.fxsave; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_xsave(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.xsave; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.xsave; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_fpu(void) { - #if CPUINFO_ARCH_X86_64 - return true; - #elif CPUINFO_ARCH_X86 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.fpu; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return true; +#elif CPUINFO_ARCH_X86 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.fpu; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_mmx(void) { - #if CPUINFO_ARCH_X86_64 - return true; - #elif CPUINFO_ARCH_X86 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.mmx; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return true; +#elif CPUINFO_ARCH_X86 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.mmx; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_mmx_plus(void) { - #if CPUINFO_ARCH_X86_64 - return true; - #elif CPUINFO_ARCH_X86 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.mmx_plus; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return true; +#elif CPUINFO_ARCH_X86 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.mmx_plus; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_3dnow(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.three_d_now; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.three_d_now; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_3dnow_plus(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.three_d_now_plus; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.three_d_now_plus; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_3dnow_geode(void) { - #if CPUINFO_ARCH_X86_64 - return false; - #elif CPUINFO_ARCH_X86 - #if defined(__ANDROID__) - return false; - #else - return cpuinfo_isa.three_d_now_geode; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return false; +#elif CPUINFO_ARCH_X86 +#if defined(__ANDROID__) + return false; +#else + return cpuinfo_isa.three_d_now_geode; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_prefetch(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.prefetch; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.prefetch; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_prefetchw(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.prefetchw; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.prefetchw; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_prefetchwt1(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.prefetchwt1; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.prefetchwt1; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_daz(void) { - #if CPUINFO_ARCH_X86_64 - return true; - #elif CPUINFO_ARCH_X86 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.daz; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return true; +#elif CPUINFO_ARCH_X86 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.daz; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_sse(void) { - #if CPUINFO_ARCH_X86_64 - return true; - #elif CPUINFO_ARCH_X86 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.sse; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return true; +#elif CPUINFO_ARCH_X86 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.sse; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_sse2(void) { - #if CPUINFO_ARCH_X86_64 - return true; - #elif CPUINFO_ARCH_X86 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.sse2; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return true; +#elif CPUINFO_ARCH_X86 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.sse2; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_sse3(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.sse3; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.sse3; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_ssse3(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.ssse3; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.ssse3; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_sse4_1(void) { - #if CPUINFO_ARCH_X86_64 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.sse4_1; - #endif - #elif CPUINFO_ARCH_X86 - return cpuinfo_isa.sse4_1; - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.sse4_1; +#endif +#elif CPUINFO_ARCH_X86 + return cpuinfo_isa.sse4_1; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_sse4_2(void) { - #if CPUINFO_ARCH_X86_64 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.sse4_2; - #endif - #elif CPUINFO_ARCH_X86 - return cpuinfo_isa.sse4_2; - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.sse4_2; +#endif +#elif CPUINFO_ARCH_X86 + return cpuinfo_isa.sse4_2; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_sse4a(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.sse4a; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.sse4a; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_misaligned_sse(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.misaligned_sse; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.misaligned_sse; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avxvnni(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avxvnni; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avxvnni; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_fma3(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.fma3; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.fma3; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_fma4(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.fma4; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.fma4; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_xop(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.xop; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.xop; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_f16c(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.f16c; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.f16c; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx2(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx2; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx2; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512f(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512f; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512f; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512pf(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512pf; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512pf; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512er(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512er; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512er; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512cd(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512cd; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512cd; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512dq(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512dq; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512dq; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512bw(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512bw; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512bw; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512vl(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512vl; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512vl; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512ifma(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512ifma; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512ifma; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512vbmi(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512vbmi; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512vbmi; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512vbmi2(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512vbmi2; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512vbmi2; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512bitalg(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512bitalg; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512bitalg; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512vpopcntdq(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512vpopcntdq; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512vpopcntdq; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512vnni(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512vnni; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512vnni; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512bf16(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512bf16; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512bf16; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512fp16(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512fp16; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512fp16; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512vp2intersect(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512vp2intersect; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512vp2intersect; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512_4vnniw(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512_4vnniw; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512_4vnniw; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512_4fmaps(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512_4fmaps; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512_4fmaps; +#else + return false; +#endif +} + +/* [NOTE] Intel Advanced Matrix Extensions (AMX) detection + * + * I. AMX is a new extensions to the x86 ISA to work on matrices, consists of + * 1) 2-dimentional registers (tiles), hold sub-matrices from larger matrices in memory + * 2) Accelerator called Tile Matrix Multiply (TMUL), contains instructions operating on tiles + * + * II. Platforms that supports AMX: + * +-----------------+-----+----------+----------+----------+----------+ + * | Platforms | Gen | amx-bf16 | amx-tile | amx-int8 | amx-fp16 | + * +-----------------+-----+----------+----------+----------+----------+ + * | Sapphire Rapids | 4th | YES | YES | YES | NO | + * +-----------------+-----+----------+----------+----------+----------+ + * | Emerald Rapids | 5th | YES | YES | YES | NO | + * +-----------------+-----+----------+----------+----------+----------+ + * | Granite Rapids | 6th | YES | YES | YES | YES | + * +-----------------+-----+----------+----------+----------+----------+ + * + * Reference: https://www.intel.com/content/www/us/en/products/docs + * /accelerator-engines/advanced-matrix-extensions/overview.html + */ +static inline bool cpuinfo_has_x86_amx_bf16(void) { +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.amx_bf16; +#else + return false; +#endif +} + +static inline bool cpuinfo_has_x86_amx_tile(void) { +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.amx_tile; +#else + return false; +#endif +} + +static inline bool cpuinfo_has_x86_amx_int8(void) { +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.amx_int8; +#else + return false; +#endif +} + +static inline bool cpuinfo_has_x86_amx_fp16(void) { +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.amx_fp16; +#else + return false; +#endif +} + +/* + * Intel AVX Vector Neural Network Instructions (VNNI) INT8 + * Supported Platfroms: Sierra Forest, Arrow Lake, Lunar Lake + */ +static inline bool cpuinfo_has_x86_avx_vnni_int8(void) { +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx_vnni_int8; +#else + return false; +#endif +} + +/* + * Intel AVX Vector Neural Network Instructions (VNNI) INT16 + * Supported Platfroms: Arrow Lake, Lunar Lake + */ +static inline bool cpuinfo_has_x86_avx_vnni_int16(void) { +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx_vnni_int16; +#else + return false; +#endif +} + +/* + * A new set of instructions, which can convert low precision floating point + * like BF16/FP16 to high precision floating point FP32, as well as convert FP32 + * elements to BF16. This instruction allows the platform to have improved AI + * capabilities and better compatibility. + * + * Supported Platforms: Sierra Forest, Arrow Lake, Lunar Lake + */ +static inline bool cpuinfo_has_x86_avx_ne_convert(void) { +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx_ne_convert; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_hle(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.hle; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.hle; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_rtm(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.rtm; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.rtm; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_xtest(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.xtest; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.xtest; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_mpx(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.mpx; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.mpx; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_cmov(void) { - #if CPUINFO_ARCH_X86_64 - return true; - #elif CPUINFO_ARCH_X86 - return cpuinfo_isa.cmov; - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return true; +#elif CPUINFO_ARCH_X86 + return cpuinfo_isa.cmov; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_cmpxchg8b(void) { - #if CPUINFO_ARCH_X86_64 - return true; - #elif CPUINFO_ARCH_X86 - return cpuinfo_isa.cmpxchg8b; - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return true; +#elif CPUINFO_ARCH_X86 + return cpuinfo_isa.cmpxchg8b; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_cmpxchg16b(void) { - #if CPUINFO_ARCH_X86_64 - return cpuinfo_isa.cmpxchg16b; - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return cpuinfo_isa.cmpxchg16b; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_clwb(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.clwb; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.clwb; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_movbe(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.movbe; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.movbe; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_lahf_sahf(void) { - #if CPUINFO_ARCH_X86 - return true; - #elif CPUINFO_ARCH_X86_64 - return cpuinfo_isa.lahf_sahf; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 + return true; +#elif CPUINFO_ARCH_X86_64 + return cpuinfo_isa.lahf_sahf; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_lzcnt(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.lzcnt; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.lzcnt; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_popcnt(void) { - #if CPUINFO_ARCH_X86_64 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.popcnt; - #endif - #elif CPUINFO_ARCH_X86 - return cpuinfo_isa.popcnt; - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.popcnt; +#endif +#elif CPUINFO_ARCH_X86 + return cpuinfo_isa.popcnt; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_tbm(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.tbm; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.tbm; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_bmi(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.bmi; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.bmi; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_bmi2(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.bmi2; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.bmi2; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_adx(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.adx; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.adx; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_aes(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.aes; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.aes; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_vaes(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.vaes; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.vaes; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_pclmulqdq(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.pclmulqdq; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.pclmulqdq; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_vpclmulqdq(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.vpclmulqdq; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.vpclmulqdq; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_gfni(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.gfni; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.gfni; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_rdrand(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.rdrand; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.rdrand; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_rdseed(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.rdseed; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.rdseed; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_sha(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.sha; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.sha; +#else + return false; +#endif } #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - /* This structure is not a part of stable API. Use cpuinfo_has_arm_* functions instead. */ - struct cpuinfo_arm_isa { - #if CPUINFO_ARCH_ARM - bool thumb; - bool thumb2; - bool thumbee; - bool jazelle; - bool armv5e; - bool armv6; - bool armv6k; - bool armv7; - bool armv7mp; - bool armv8; - bool idiv; +/* This structure is not a part of stable API. Use cpuinfo_has_arm_* functions + * instead. */ +struct cpuinfo_arm_isa { +#if CPUINFO_ARCH_ARM + bool thumb; + bool thumb2; + bool thumbee; + bool jazelle; + bool armv5e; + bool armv6; + bool armv6k; + bool armv7; + bool armv7mp; + bool armv8; + bool idiv; - bool vfpv2; - bool vfpv3; - bool d32; - bool fp16; - bool fma; + bool vfpv2; + bool vfpv3; + bool d32; + bool fp16; + bool fma; - bool wmmx; - bool wmmx2; - bool neon; - #endif - #if CPUINFO_ARCH_ARM64 - bool atomics; - bool bf16; - bool sve; - bool sve2; - bool i8mm; - #endif - bool rdm; - bool fp16arith; - bool dot; - bool jscvt; - bool fcma; - bool fhm; + bool wmmx; + bool wmmx2; + bool neon; +#endif +#if CPUINFO_ARCH_ARM64 + bool atomics; + bool bf16; + bool sve; + bool sve2; + bool i8mm; +#endif + bool rdm; + bool fp16arith; + bool dot; + bool jscvt; + bool fcma; + bool fhm; - bool aes; - bool sha1; - bool sha2; - bool pmull; - bool crc32; - }; + bool aes; + bool sha1; + bool sha2; + bool pmull; + bool crc32; +}; - extern struct cpuinfo_arm_isa cpuinfo_isa; +extern struct cpuinfo_arm_isa cpuinfo_isa; #endif static inline bool cpuinfo_has_arm_thumb(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.thumb; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.thumb; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_thumb2(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.thumb2; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.thumb2; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_v5e(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.armv5e; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.armv5e; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_v6(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.armv6; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.armv6; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_v6k(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.armv6k; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.armv6k; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_v7(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.armv7; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.armv7; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_v7mp(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.armv7mp; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.armv7mp; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_v8(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.armv8; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.armv8; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_idiv(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.idiv; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.idiv; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_vfpv2(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.vfpv2; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.vfpv2; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_vfpv3(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.vfpv3; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.vfpv3; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_vfpv3_d32(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.vfpv3 && cpuinfo_isa.d32; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.vfpv3 && cpuinfo_isa.d32; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_vfpv3_fp16(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.vfpv3 && cpuinfo_isa.fp16; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.vfpv3 && cpuinfo_isa.fp16; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_vfpv3_fp16_d32(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.vfpv3 && cpuinfo_isa.fp16 && cpuinfo_isa.d32; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.vfpv3 && cpuinfo_isa.fp16 && cpuinfo_isa.d32; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_vfpv4(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.vfpv3 && cpuinfo_isa.fma; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.vfpv3 && cpuinfo_isa.fma; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_vfpv4_d32(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.vfpv3 && cpuinfo_isa.fma && cpuinfo_isa.d32; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.vfpv3 && cpuinfo_isa.fma && cpuinfo_isa.d32; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_fp16_arith(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.fp16arith; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.fp16arith; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_bf16(void) { - #if CPUINFO_ARCH_ARM64 - return cpuinfo_isa.bf16; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return cpuinfo_isa.bf16; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_wmmx(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.wmmx; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.wmmx; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_wmmx2(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.wmmx2; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.wmmx2; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_neon(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.neon; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.neon; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_neon_fp16(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.neon && cpuinfo_isa.fp16; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.neon && cpuinfo_isa.fp16; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_neon_fma(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.neon && cpuinfo_isa.fma; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.neon && cpuinfo_isa.fma; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_neon_v8(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.neon && cpuinfo_isa.armv8; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.neon && cpuinfo_isa.armv8; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_atomics(void) { - #if CPUINFO_ARCH_ARM64 - return cpuinfo_isa.atomics; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return cpuinfo_isa.atomics; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_neon_rdm(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.rdm; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.rdm; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_neon_fp16_arith(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.neon && cpuinfo_isa.fp16arith; - #elif CPUINFO_ARCH_ARM64 - return cpuinfo_isa.fp16arith; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.neon && cpuinfo_isa.fp16arith; +#elif CPUINFO_ARCH_ARM64 + return cpuinfo_isa.fp16arith; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_fhm(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.fhm; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.fhm; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_neon_dot(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.dot; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.dot; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_neon_bf16(void) { - #if CPUINFO_ARCH_ARM64 - return cpuinfo_isa.bf16; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return cpuinfo_isa.bf16; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_jscvt(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.jscvt; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.jscvt; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_fcma(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.fcma; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.fcma; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_i8mm(void) { - #if CPUINFO_ARCH_ARM64 - return cpuinfo_isa.i8mm; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return cpuinfo_isa.i8mm; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_aes(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.aes; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.aes; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_sha1(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.sha1; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.sha1; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_sha2(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.sha2; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.sha2; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_pmull(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.pmull; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.pmull; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_crc32(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.crc32; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.crc32; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_sve(void) { - #if CPUINFO_ARCH_ARM64 - return cpuinfo_isa.sve; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return cpuinfo_isa.sve; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_sve_bf16(void) { - #if CPUINFO_ARCH_ARM64 - return cpuinfo_isa.sve && cpuinfo_isa.bf16; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return cpuinfo_isa.sve && cpuinfo_isa.bf16; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_sve2(void) { - #if CPUINFO_ARCH_ARM64 - return cpuinfo_isa.sve2; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return cpuinfo_isa.sve2; +#else + return false; +#endif } #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - /* This structure is not a part of stable API. Use cpuinfo_has_riscv_* functions instead. */ - struct cpuinfo_riscv_isa { - /** - * Keep fields in line with the canonical order as defined by - * Section 27.11 Subset Naming Convention. - */ - /* RV32I/64I/128I Base ISA. */ - bool i; - #if CPUINFO_ARCH_RISCV32 - /* RV32E Base ISA. */ - bool e; - #endif - /* Integer Multiply/Divide Extension. */ - bool m; - /* Atomic Extension. */ - bool a; - /* Single-Precision Floating-Point Extension. */ - bool f; - /* Double-Precision Floating-Point Extension. */ - bool d; - /* Compressed Extension. */ - bool c; - /* Vector Extension. */ - bool v; - }; +/* This structure is not a part of stable API. Use cpuinfo_has_riscv_* functions + * instead. */ +struct cpuinfo_riscv_isa { + /** + * Keep fields in line with the canonical order as defined by + * Section 27.11 Subset Naming Convention. + */ + /* RV32I/64I/128I Base ISA. */ + bool i; +#if CPUINFO_ARCH_RISCV32 + /* RV32E Base ISA. */ + bool e; +#endif + /* Integer Multiply/Divide Extension. */ + bool m; + /* Atomic Extension. */ + bool a; + /* Single-Precision Floating-Point Extension. */ + bool f; + /* Double-Precision Floating-Point Extension. */ + bool d; + /* Compressed Extension. */ + bool c; + /* Vector Extension. */ + bool v; +}; - extern struct cpuinfo_riscv_isa cpuinfo_isa; +extern struct cpuinfo_riscv_isa cpuinfo_isa; #endif static inline bool cpuinfo_has_riscv_i(void) { - #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - return cpuinfo_isa.i; - #else - return false; - #endif +#if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.i; +#else + return false; +#endif } static inline bool cpuinfo_has_riscv_e(void) { - #if CPUINFO_ARCH_RISCV32 - return cpuinfo_isa.e; - #else - return false; - #endif +#if CPUINFO_ARCH_RISCV32 + return cpuinfo_isa.e; +#else + return false; +#endif } static inline bool cpuinfo_has_riscv_m(void) { - #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - return cpuinfo_isa.m; - #else - return false; - #endif +#if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.m; +#else + return false; +#endif } static inline bool cpuinfo_has_riscv_a(void) { - #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - return cpuinfo_isa.a; - #else - return false; - #endif +#if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.a; +#else + return false; +#endif } static inline bool cpuinfo_has_riscv_f(void) { - #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - return cpuinfo_isa.f; - #else - return false; - #endif +#if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.f; +#else + return false; +#endif } static inline bool cpuinfo_has_riscv_d(void) { - #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - return cpuinfo_isa.d; - #else - return false; - #endif +#if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.d; +#else + return false; +#endif } static inline bool cpuinfo_has_riscv_g(void) { // The 'G' extension is simply shorthand for 'IMAFD'. - return cpuinfo_has_riscv_i() - && cpuinfo_has_riscv_m() - && cpuinfo_has_riscv_a() - && cpuinfo_has_riscv_f() - && cpuinfo_has_riscv_d(); + return cpuinfo_has_riscv_i() && cpuinfo_has_riscv_m() && cpuinfo_has_riscv_a() && cpuinfo_has_riscv_f() && + cpuinfo_has_riscv_d(); } static inline bool cpuinfo_has_riscv_c(void) { - #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - return cpuinfo_isa.c; - #else - return false; - #endif +#if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.c; +#else + return false; +#endif } static inline bool cpuinfo_has_riscv_v(void) { - #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - return cpuinfo_isa.v; - #else - return false; - #endif +#if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.v; +#else + return false; +#endif } const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_processors(void); @@ -2039,34 +2178,38 @@ uint32_t CPUINFO_ABI cpuinfo_get_max_cache_size(void); /** * Identify the logical processor that executes the current thread. * - * There is no guarantee that the thread will stay on the same logical processor for any time. - * Callers should treat the result as only a hint, and be prepared to handle NULL return value. + * There is no guarantee that the thread will stay on the same logical processor + * for any time. Callers should treat the result as only a hint, and be prepared + * to handle NULL return value. */ const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_current_processor(void); /** * Identify the core that executes the current thread. * - * There is no guarantee that the thread will stay on the same core for any time. - * Callers should treat the result as only a hint, and be prepared to handle NULL return value. + * There is no guarantee that the thread will stay on the same core for any + * time. Callers should treat the result as only a hint, and be prepared to + * handle NULL return value. */ const struct cpuinfo_core* CPUINFO_ABI cpuinfo_get_current_core(void); /** - * Identify the microarchitecture index of the core that executes the current thread. - * If the system does not support such identification, the function returns 0. + * Identify the microarchitecture index of the core that executes the current + * thread. If the system does not support such identification, the function + * returns 0. * - * There is no guarantee that the thread will stay on the same type of core for any time. - * Callers should treat the result as only a hint. + * There is no guarantee that the thread will stay on the same type of core for + * any time. Callers should treat the result as only a hint. */ uint32_t CPUINFO_ABI cpuinfo_get_current_uarch_index(void); /** - * Identify the microarchitecture index of the core that executes the current thread. - * If the system does not support such identification, the function returns the user-specified default value. + * Identify the microarchitecture index of the core that executes the current + * thread. If the system does not support such identification, the function + * returns the user-specified default value. * - * There is no guarantee that the thread will stay on the same type of core for any time. - * Callers should treat the result as only a hint. + * There is no guarantee that the thread will stay on the same type of core for + * any time. Callers should treat the result as only a hint. */ uint32_t CPUINFO_ABI cpuinfo_get_current_uarch_index_with_default(uint32_t default_uarch_index); diff --git a/3rdparty/cpuinfo/src/api.c b/3rdparty/cpuinfo/src/api.c index 2f70aeffbb..b8c999f32c 100644 --- a/3rdparty/cpuinfo/src/api.c +++ b/3rdparty/cpuinfo/src/api.c @@ -6,13 +6,13 @@ #include #ifdef __linux__ - #include +#include - #include - #include - #if !defined(__NR_getcpu) - #include - #endif +#include +#include +#if !defined(__NR_getcpu) +#include +#endif #endif bool cpuinfo_is_initialized = false; @@ -21,57 +21,54 @@ struct cpuinfo_processor* cpuinfo_processors = NULL; struct cpuinfo_core* cpuinfo_cores = NULL; struct cpuinfo_cluster* cpuinfo_clusters = NULL; struct cpuinfo_package* cpuinfo_packages = NULL; -struct cpuinfo_cache* cpuinfo_cache[cpuinfo_cache_level_max] = { NULL }; +struct cpuinfo_cache* cpuinfo_cache[cpuinfo_cache_level_max] = {NULL}; uint32_t cpuinfo_processors_count = 0; uint32_t cpuinfo_cores_count = 0; uint32_t cpuinfo_clusters_count = 0; uint32_t cpuinfo_packages_count = 0; -uint32_t cpuinfo_cache_count[cpuinfo_cache_level_max] = { 0 }; +uint32_t cpuinfo_cache_count[cpuinfo_cache_level_max] = {0}; uint32_t cpuinfo_max_cache_size = 0; -#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ - || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - struct cpuinfo_uarch_info* cpuinfo_uarchs = NULL; - uint32_t cpuinfo_uarchs_count = 0; +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 +struct cpuinfo_uarch_info* cpuinfo_uarchs = NULL; +uint32_t cpuinfo_uarchs_count = 0; #else - struct cpuinfo_uarch_info cpuinfo_global_uarch = { cpuinfo_uarch_unknown }; +struct cpuinfo_uarch_info cpuinfo_global_uarch = {cpuinfo_uarch_unknown}; #endif #ifdef __linux__ - uint32_t cpuinfo_linux_cpu_max = 0; - const struct cpuinfo_processor** cpuinfo_linux_cpu_to_processor_map = NULL; - const struct cpuinfo_core** cpuinfo_linux_cpu_to_core_map = NULL; - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ - || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - const uint32_t* cpuinfo_linux_cpu_to_uarch_index_map = NULL; - #endif +uint32_t cpuinfo_linux_cpu_max = 0; +const struct cpuinfo_processor** cpuinfo_linux_cpu_to_processor_map = NULL; +const struct cpuinfo_core** cpuinfo_linux_cpu_to_core_map = NULL; +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 +const uint32_t* cpuinfo_linux_cpu_to_uarch_index_map = NULL; +#endif #endif - const struct cpuinfo_processor* cpuinfo_get_processors(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "processors"); } return cpuinfo_processors; } const struct cpuinfo_core* cpuinfo_get_cores(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "core"); } return cpuinfo_cores; } const struct cpuinfo_cluster* cpuinfo_get_clusters(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "clusters"); } return cpuinfo_clusters; } const struct cpuinfo_package* cpuinfo_get_packages(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "packages"); } return cpuinfo_packages; @@ -81,49 +78,48 @@ const struct cpuinfo_uarch_info* cpuinfo_get_uarchs() { if (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "uarchs"); } - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ - || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - return cpuinfo_uarchs; - #else - return &cpuinfo_global_uarch; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_uarchs; +#else + return &cpuinfo_global_uarch; +#endif } const struct cpuinfo_processor* cpuinfo_get_processor(uint32_t index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "processor"); } - if CPUINFO_UNLIKELY(index >= cpuinfo_processors_count) { + if CPUINFO_UNLIKELY (index >= cpuinfo_processors_count) { return NULL; } return &cpuinfo_processors[index]; } const struct cpuinfo_core* cpuinfo_get_core(uint32_t index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "core"); } - if CPUINFO_UNLIKELY(index >= cpuinfo_cores_count) { + if CPUINFO_UNLIKELY (index >= cpuinfo_cores_count) { return NULL; } return &cpuinfo_cores[index]; } const struct cpuinfo_cluster* cpuinfo_get_cluster(uint32_t index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "cluster"); } - if CPUINFO_UNLIKELY(index >= cpuinfo_clusters_count) { + if CPUINFO_UNLIKELY (index >= cpuinfo_clusters_count) { return NULL; } return &cpuinfo_clusters[index]; } const struct cpuinfo_package* cpuinfo_get_package(uint32_t index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "package"); } - if CPUINFO_UNLIKELY(index >= cpuinfo_packages_count) { + if CPUINFO_UNLIKELY (index >= cpuinfo_packages_count) { return NULL; } return &cpuinfo_packages[index]; @@ -133,43 +129,42 @@ const struct cpuinfo_uarch_info* cpuinfo_get_uarch(uint32_t index) { if (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "uarch"); } - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ - || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - if CPUINFO_UNLIKELY(index >= cpuinfo_uarchs_count) { - return NULL; - } - return &cpuinfo_uarchs[index]; - #else - if CPUINFO_UNLIKELY(index != 0) { - return NULL; - } - return &cpuinfo_global_uarch; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + if CPUINFO_UNLIKELY (index >= cpuinfo_uarchs_count) { + return NULL; + } + return &cpuinfo_uarchs[index]; +#else + if CPUINFO_UNLIKELY (index != 0) { + return NULL; + } + return &cpuinfo_global_uarch; +#endif } uint32_t cpuinfo_get_processors_count(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "processors_count"); } return cpuinfo_processors_count; } uint32_t cpuinfo_get_cores_count(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "cores_count"); } return cpuinfo_cores_count; } uint32_t cpuinfo_get_clusters_count(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "clusters_count"); } return cpuinfo_clusters_count; } uint32_t cpuinfo_get_packages_count(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "packages_count"); } return cpuinfo_packages_count; @@ -179,239 +174,243 @@ uint32_t cpuinfo_get_uarchs_count(void) { if (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "uarchs_count"); } - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ - || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - return cpuinfo_uarchs_count; - #else - return 1; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_uarchs_count; +#else + return 1; +#endif } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1i_caches(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l1i_caches"); } return cpuinfo_cache[cpuinfo_cache_level_1i]; } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1d_caches(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l1d_caches"); } return cpuinfo_cache[cpuinfo_cache_level_1d]; } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l2_caches(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l2_caches"); } return cpuinfo_cache[cpuinfo_cache_level_2]; } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l3_caches(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l3_caches"); } return cpuinfo_cache[cpuinfo_cache_level_3]; } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l4_caches(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l4_caches"); } return cpuinfo_cache[cpuinfo_cache_level_4]; } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1i_cache(uint32_t index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l1i_cache"); } - if CPUINFO_UNLIKELY(index >= cpuinfo_cache_count[cpuinfo_cache_level_1i]) { + if CPUINFO_UNLIKELY (index >= cpuinfo_cache_count[cpuinfo_cache_level_1i]) { return NULL; } return &cpuinfo_cache[cpuinfo_cache_level_1i][index]; } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1d_cache(uint32_t index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l1d_cache"); } - if CPUINFO_UNLIKELY(index >= cpuinfo_cache_count[cpuinfo_cache_level_1d]) { + if CPUINFO_UNLIKELY (index >= cpuinfo_cache_count[cpuinfo_cache_level_1d]) { return NULL; } return &cpuinfo_cache[cpuinfo_cache_level_1d][index]; } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l2_cache(uint32_t index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l2_cache"); } - if CPUINFO_UNLIKELY(index >= cpuinfo_cache_count[cpuinfo_cache_level_2]) { + if CPUINFO_UNLIKELY (index >= cpuinfo_cache_count[cpuinfo_cache_level_2]) { return NULL; } return &cpuinfo_cache[cpuinfo_cache_level_2][index]; } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l3_cache(uint32_t index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l3_cache"); } - if CPUINFO_UNLIKELY(index >= cpuinfo_cache_count[cpuinfo_cache_level_3]) { + if CPUINFO_UNLIKELY (index >= cpuinfo_cache_count[cpuinfo_cache_level_3]) { return NULL; } return &cpuinfo_cache[cpuinfo_cache_level_3][index]; } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l4_cache(uint32_t index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l4_cache"); } - if CPUINFO_UNLIKELY(index >= cpuinfo_cache_count[cpuinfo_cache_level_4]) { + if CPUINFO_UNLIKELY (index >= cpuinfo_cache_count[cpuinfo_cache_level_4]) { return NULL; } return &cpuinfo_cache[cpuinfo_cache_level_4][index]; } uint32_t CPUINFO_ABI cpuinfo_get_l1i_caches_count(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l1i_caches_count"); } return cpuinfo_cache_count[cpuinfo_cache_level_1i]; } uint32_t CPUINFO_ABI cpuinfo_get_l1d_caches_count(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l1d_caches_count"); } return cpuinfo_cache_count[cpuinfo_cache_level_1d]; } uint32_t CPUINFO_ABI cpuinfo_get_l2_caches_count(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l2_caches_count"); } return cpuinfo_cache_count[cpuinfo_cache_level_2]; } uint32_t CPUINFO_ABI cpuinfo_get_l3_caches_count(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l3_caches_count"); } return cpuinfo_cache_count[cpuinfo_cache_level_3]; } uint32_t CPUINFO_ABI cpuinfo_get_l4_caches_count(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l4_caches_count"); } return cpuinfo_cache_count[cpuinfo_cache_level_4]; } uint32_t CPUINFO_ABI cpuinfo_get_max_cache_size(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "max_cache_size"); } return cpuinfo_max_cache_size; } const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_current_processor(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "current_processor"); } - #ifdef __linux__ - /* Initializing this variable silences a MemorySanitizer error. */ - unsigned cpu = 0; - if CPUINFO_UNLIKELY(syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { - return 0; - } - if CPUINFO_UNLIKELY((uint32_t) cpu >= cpuinfo_linux_cpu_max) { - return 0; - } - return cpuinfo_linux_cpu_to_processor_map[cpu]; - #else - return NULL; - #endif +#ifdef __linux__ + /* Initializing this variable silences a MemorySanitizer error. */ + unsigned cpu = 0; + if CPUINFO_UNLIKELY (syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { + return 0; + } + if CPUINFO_UNLIKELY ((uint32_t)cpu >= cpuinfo_linux_cpu_max) { + return 0; + } + return cpuinfo_linux_cpu_to_processor_map[cpu]; +#else + return NULL; +#endif } const struct cpuinfo_core* CPUINFO_ABI cpuinfo_get_current_core(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "current_core"); } - #ifdef __linux__ - /* Initializing this variable silences a MemorySanitizer error. */ - unsigned cpu = 0; - if CPUINFO_UNLIKELY(syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { - return 0; - } - if CPUINFO_UNLIKELY((uint32_t) cpu >= cpuinfo_linux_cpu_max) { - return 0; - } - return cpuinfo_linux_cpu_to_core_map[cpu]; - #else - return NULL; - #endif +#ifdef __linux__ + /* Initializing this variable silences a MemorySanitizer error. */ + unsigned cpu = 0; + if CPUINFO_UNLIKELY (syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { + return 0; + } + if CPUINFO_UNLIKELY ((uint32_t)cpu >= cpuinfo_linux_cpu_max) { + return 0; + } + return cpuinfo_linux_cpu_to_core_map[cpu]; +#else + return NULL; +#endif } uint32_t CPUINFO_ABI cpuinfo_get_current_uarch_index(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "current_uarch_index"); } - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ - || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - #ifdef __linux__ - if (cpuinfo_linux_cpu_to_uarch_index_map == NULL) { - /* Special case: avoid syscall on systems with only a single type of cores */ - return 0; - } - - /* General case */ - /* Initializing this variable silences a MemorySanitizer error. */ - unsigned cpu = 0; - if CPUINFO_UNLIKELY(syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { - return 0; - } - if CPUINFO_UNLIKELY((uint32_t) cpu >= cpuinfo_linux_cpu_max) { - return 0; - } - return cpuinfo_linux_cpu_to_uarch_index_map[cpu]; - #else - /* Fallback: pretend to be on the big core. */ - return 0; - #endif - #else - /* Only ARM/ARM64/RISCV processors may include cores of different types in the same package. */ +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 +#ifdef __linux__ + if (cpuinfo_linux_cpu_to_uarch_index_map == NULL) { + /* Special case: avoid syscall on systems with only a single + * type of cores + */ return 0; - #endif + } + + /* General case */ + /* Initializing this variable silences a MemorySanitizer error. */ + unsigned cpu = 0; + if CPUINFO_UNLIKELY (syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { + return 0; + } + if CPUINFO_UNLIKELY ((uint32_t)cpu >= cpuinfo_linux_cpu_max) { + return 0; + } + return cpuinfo_linux_cpu_to_uarch_index_map[cpu]; +#else + /* Fallback: pretend to be on the big core. */ + return 0; +#endif +#else + /* Only ARM/ARM64/RISCV processors may include cores of different types + * in the same package. */ + return 0; +#endif } uint32_t CPUINFO_ABI cpuinfo_get_current_uarch_index_with_default(uint32_t default_uarch_index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { - cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "current_uarch_index_with_default"); + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { + cpuinfo_log_fatal( + "cpuinfo_get_%s called before cpuinfo is initialized", "current_uarch_index_with_default"); } - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ - || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - #ifdef __linux__ - if (cpuinfo_linux_cpu_to_uarch_index_map == NULL) { - /* Special case: avoid syscall on systems with only a single type of cores */ - return 0; - } - - /* General case */ - /* Initializing this variable silences a MemorySanitizer error. */ - unsigned cpu = 0; - if CPUINFO_UNLIKELY(syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { - return default_uarch_index; - } - if CPUINFO_UNLIKELY((uint32_t) cpu >= cpuinfo_linux_cpu_max) { - return default_uarch_index; - } - return cpuinfo_linux_cpu_to_uarch_index_map[cpu]; - #else - /* Fallback: no API to query current core, use default uarch index. */ - return default_uarch_index; - #endif - #else - /* Only ARM/ARM64/RISCV processors may include cores of different types in the same package. */ +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 +#ifdef __linux__ + if (cpuinfo_linux_cpu_to_uarch_index_map == NULL) { + /* Special case: avoid syscall on systems with only a single + * type of cores + */ return 0; - #endif + } + + /* General case */ + /* Initializing this variable silences a MemorySanitizer error. */ + unsigned cpu = 0; + if CPUINFO_UNLIKELY (syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { + return default_uarch_index; + } + if CPUINFO_UNLIKELY ((uint32_t)cpu >= cpuinfo_linux_cpu_max) { + return default_uarch_index; + } + return cpuinfo_linux_cpu_to_uarch_index_map[cpu]; +#else + /* Fallback: no API to query current core, use default uarch index. */ + return default_uarch_index; +#endif +#else + /* Only ARM/ARM64/RISCV processors may include cores of different types + * in the same package. */ + return 0; +#endif } diff --git a/3rdparty/cpuinfo/src/arm/android/api.h b/3rdparty/cpuinfo/src/arm/android/api.h index 228632acee..48ef14279e 100644 --- a/3rdparty/cpuinfo/src/arm/android/api.h +++ b/3rdparty/cpuinfo/src/arm/android/api.h @@ -1,9 +1,9 @@ #pragma once -#include -#include #include #include +#include +#include enum cpuinfo_android_chipset_property { cpuinfo_android_chipset_property_proc_cpuinfo_hardware = 0, diff --git a/3rdparty/cpuinfo/src/arm/android/properties.c b/3rdparty/cpuinfo/src/arm/android/properties.c index 5f93889d73..51a2def952 100644 --- a/3rdparty/cpuinfo/src/arm/android/properties.c +++ b/3rdparty/cpuinfo/src/arm/android/properties.c @@ -1,42 +1,42 @@ #include +#include #include #include -#include #include #include -#include #include #include #include +#include #if CPUINFO_MOCK - #include +#include - static struct cpuinfo_mock_property* cpuinfo_mock_properties = NULL; +static struct cpuinfo_mock_property* cpuinfo_mock_properties = NULL; - void CPUINFO_ABI cpuinfo_mock_android_properties(struct cpuinfo_mock_property* properties) { - cpuinfo_log_info("Android properties mocking enabled"); - cpuinfo_mock_properties = properties; - } +void CPUINFO_ABI cpuinfo_mock_android_properties(struct cpuinfo_mock_property* properties) { + cpuinfo_log_info("Android properties mocking enabled"); + cpuinfo_mock_properties = properties; +} - static int cpuinfo_android_property_get(const char* key, char* value) { - if (cpuinfo_mock_properties != NULL) { - for (const struct cpuinfo_mock_property* prop = cpuinfo_mock_properties; prop->key != NULL; prop++) { - if (strncmp(key, prop->key, CPUINFO_BUILD_PROP_NAME_MAX) == 0) { - strncpy(value, prop->value, CPUINFO_BUILD_PROP_VALUE_MAX); - return (int) strnlen(prop->value, CPUINFO_BUILD_PROP_VALUE_MAX); - } +static int cpuinfo_android_property_get(const char* key, char* value) { + if (cpuinfo_mock_properties != NULL) { + for (const struct cpuinfo_mock_property* prop = cpuinfo_mock_properties; prop->key != NULL; prop++) { + if (strncmp(key, prop->key, CPUINFO_BUILD_PROP_NAME_MAX) == 0) { + strncpy(value, prop->value, CPUINFO_BUILD_PROP_VALUE_MAX); + return (int)strnlen(prop->value, CPUINFO_BUILD_PROP_VALUE_MAX); } } - *value = '\0'; - return 0; } + *value = '\0'; + return 0; +} #else - static inline int cpuinfo_android_property_get(const char* key, char* value) { - return __system_property_get(key, value); - } +static inline int cpuinfo_android_property_get(const char* key, char* value) { + return __system_property_get(key, value); +} #endif void cpuinfo_arm_android_parse_properties(struct cpuinfo_android_properties properties[restrict static 1]) { @@ -50,18 +50,17 @@ void cpuinfo_arm_android_parse_properties(struct cpuinfo_android_properties prop const int ro_mediatek_platform_length = cpuinfo_android_property_get("ro.mediatek.platform", properties->ro_mediatek_platform); - cpuinfo_log_debug("read ro.mediatek.platform = \"%.*s\"", - ro_mediatek_platform_length, properties->ro_mediatek_platform); + cpuinfo_log_debug( + "read ro.mediatek.platform = \"%.*s\"", ro_mediatek_platform_length, properties->ro_mediatek_platform); - const int ro_arch_length = - cpuinfo_android_property_get("ro.arch", properties->ro_arch); + const int ro_arch_length = cpuinfo_android_property_get("ro.arch", properties->ro_arch); cpuinfo_log_debug("read ro.arch = \"%.*s\"", ro_arch_length, properties->ro_arch); - const int ro_chipname_length = - cpuinfo_android_property_get("ro.chipname", properties->ro_chipname); + const int ro_chipname_length = cpuinfo_android_property_get("ro.chipname", properties->ro_chipname); cpuinfo_log_debug("read ro.chipname = \"%.*s\"", ro_chipname_length, properties->ro_chipname); const int ro_hardware_chipname_length = cpuinfo_android_property_get("ro.hardware.chipname", properties->ro_hardware_chipname); - cpuinfo_log_debug("read ro.hardware.chipname = \"%.*s\"", ro_hardware_chipname_length, properties->ro_hardware_chipname); + cpuinfo_log_debug( + "read ro.hardware.chipname = \"%.*s\"", ro_hardware_chipname_length, properties->ro_hardware_chipname); } diff --git a/3rdparty/cpuinfo/src/arm/api.h b/3rdparty/cpuinfo/src/arm/api.h index 469c84bd5c..9cfedf60da 100644 --- a/3rdparty/cpuinfo/src/arm/api.h +++ b/3rdparty/cpuinfo/src/arm/api.h @@ -80,45 +80,47 @@ struct cpuinfo_arm_chipset { #define CPUINFO_ARM_CHIPSET_NAME_MAX CPUINFO_PACKAGE_NAME_MAX #ifndef __cplusplus - CPUINFO_INTERNAL void cpuinfo_arm_chipset_to_string( - const struct cpuinfo_arm_chipset chipset[restrict static 1], - char name[restrict static CPUINFO_ARM_CHIPSET_NAME_MAX]); +CPUINFO_INTERNAL void cpuinfo_arm_chipset_to_string( + const struct cpuinfo_arm_chipset chipset[restrict static 1], + char name[restrict static CPUINFO_ARM_CHIPSET_NAME_MAX]); - CPUINFO_INTERNAL void cpuinfo_arm_fixup_chipset( - struct cpuinfo_arm_chipset chipset[restrict static 1], uint32_t cores, uint32_t max_cpu_freq_max); +CPUINFO_INTERNAL void cpuinfo_arm_fixup_chipset( + struct cpuinfo_arm_chipset chipset[restrict static 1], + uint32_t cores, + uint32_t max_cpu_freq_max); - CPUINFO_INTERNAL void cpuinfo_arm_decode_vendor_uarch( - uint32_t midr, - #if CPUINFO_ARCH_ARM - bool has_vfpv4, - #endif - enum cpuinfo_vendor vendor[restrict static 1], - enum cpuinfo_uarch uarch[restrict static 1]); - - CPUINFO_INTERNAL void cpuinfo_arm_decode_cache( - enum cpuinfo_uarch uarch, - uint32_t cluster_cores, - uint32_t midr, - const struct cpuinfo_arm_chipset chipset[restrict static 1], - uint32_t cluster_id, - uint32_t arch_version, - struct cpuinfo_cache l1i[restrict static 1], - struct cpuinfo_cache l1d[restrict static 1], - struct cpuinfo_cache l2[restrict static 1], - struct cpuinfo_cache l3[restrict static 1]); - - CPUINFO_INTERNAL uint32_t cpuinfo_arm_compute_max_cache_size( - const struct cpuinfo_processor processor[restrict static 1]); -#else /* defined(__cplusplus) */ - CPUINFO_INTERNAL void cpuinfo_arm_decode_cache( - enum cpuinfo_uarch uarch, - uint32_t cluster_cores, - uint32_t midr, - const struct cpuinfo_arm_chipset chipset[1], - uint32_t cluster_id, - uint32_t arch_version, - struct cpuinfo_cache l1i[1], - struct cpuinfo_cache l1d[1], - struct cpuinfo_cache l2[1], - struct cpuinfo_cache l3[1]); +CPUINFO_INTERNAL void cpuinfo_arm_decode_vendor_uarch( + uint32_t midr, +#if CPUINFO_ARCH_ARM + bool has_vfpv4, +#endif + enum cpuinfo_vendor vendor[restrict static 1], + enum cpuinfo_uarch uarch[restrict static 1]); + +CPUINFO_INTERNAL void cpuinfo_arm_decode_cache( + enum cpuinfo_uarch uarch, + uint32_t cluster_cores, + uint32_t midr, + const struct cpuinfo_arm_chipset chipset[restrict static 1], + uint32_t cluster_id, + uint32_t arch_version, + struct cpuinfo_cache l1i[restrict static 1], + struct cpuinfo_cache l1d[restrict static 1], + struct cpuinfo_cache l2[restrict static 1], + struct cpuinfo_cache l3[restrict static 1]); + +CPUINFO_INTERNAL uint32_t +cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor processor[restrict static 1]); +#else /* defined(__cplusplus) */ +CPUINFO_INTERNAL void cpuinfo_arm_decode_cache( + enum cpuinfo_uarch uarch, + uint32_t cluster_cores, + uint32_t midr, + const struct cpuinfo_arm_chipset chipset[1], + uint32_t cluster_id, + uint32_t arch_version, + struct cpuinfo_cache l1i[1], + struct cpuinfo_cache l1d[1], + struct cpuinfo_cache l2[1], + struct cpuinfo_cache l3[1]); #endif diff --git a/3rdparty/cpuinfo/src/arm/cache.c b/3rdparty/cpuinfo/src/arm/cache.c index 953abb72f6..dd19919311 100644 --- a/3rdparty/cpuinfo/src/arm/cache.c +++ b/3rdparty/cpuinfo/src/arm/cache.c @@ -1,11 +1,10 @@ #include +#include +#include #include #include #include -#include -#include - void cpuinfo_arm_decode_cache( enum cpuinfo_uarch uarch, @@ -17,8 +16,7 @@ void cpuinfo_arm_decode_cache( struct cpuinfo_cache l1i[restrict static 1], struct cpuinfo_cache l1d[restrict static 1], struct cpuinfo_cache l2[restrict static 1], - struct cpuinfo_cache l3[restrict static 1]) -{ + struct cpuinfo_cache l3[restrict static 1]) { switch (uarch) { #if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_7A__) && !defined(__ARM_ARCH_8A__) case cpuinfo_uarch_xscale: @@ -27,238 +25,221 @@ void cpuinfo_arm_decode_cache( /* * PXA 210/25X/26X * - * See "Computer Organization and Design, Revised Printing: The Hardware/Software Interface" - * by David A. Patterson, John L. Hennessy + * See "Computer Organization and + * Design, Revised Printing: The + * Hardware/Software Interface" by David + * A. Patterson, John L. Hennessy */ - *l1i = (struct cpuinfo_cache) { - .size = 16 * 1024, - .associativity = 32, - .line_size = 32 - }; - *l1d = (struct cpuinfo_cache) { - .size = 16 * 1024, - .associativity = 4, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){ + .size = 16 * 1024, .associativity = 32, .line_size = 32}; + *l1d = (struct cpuinfo_cache){ + .size = 16 * 1024, .associativity = 4, .line_size = 64}; break; case 4: /* PXA 27X */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 32, - .line_size = 32 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 32, - .line_size = 32 - }; + *l1i = (struct cpuinfo_cache){ + .size = 32 * 1024, .associativity = 32, .line_size = 32}; + *l1d = (struct cpuinfo_cache){ + .size = 32 * 1024, .associativity = 32, .line_size = 32}; break; case 6: /* * PXA 3XX * - * See http://download.intel.com/design/intelxscale/31628302.pdf + * See + * http://download.intel.com/design/intelxscale/31628302.pdf */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 32 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 32 - }; - *l2 = (struct cpuinfo_cache) { - .size = 256 * 1024, - .associativity = 8, - .line_size = 32 - }; + *l1i = (struct cpuinfo_cache){ + .size = 32 * 1024, .associativity = 4, .line_size = 32}; + *l1d = (struct cpuinfo_cache){ + .size = 32 * 1024, .associativity = 4, .line_size = 32}; + *l2 = (struct cpuinfo_cache){ + .size = 256 * 1024, .associativity = 8, .line_size = 32}; break; } break; case cpuinfo_uarch_arm11: - *l1i = (struct cpuinfo_cache) { - .size = 16 * 1024, - .associativity = 4, - .line_size = 32 - }; - *l1d = (struct cpuinfo_cache) { - .size = 16 * 1024, - .associativity = 4, - .line_size = 32 - }; + *l1i = (struct cpuinfo_cache){.size = 16 * 1024, .associativity = 4, .line_size = 32}; + *l1d = (struct cpuinfo_cache){.size = 16 * 1024, .associativity = 4, .line_size = 32}; break; -#endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_7A__) && !defined(__ARM_ARCH_8A__) */ +#endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_7A__) && \ + !defined(__ARM_ARCH_8A__) */ #if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__) case cpuinfo_uarch_cortex_a5: /* * Cortex-A5 Technical Reference Manual: * 7.1.1. Memory system - * The Cortex-A5 processor has separate instruction and data caches. - * The caches have the following features: + * The Cortex-A5 processor has separate instruction + * and data caches. The caches have the following + * features: * - Data cache is 4-way set-associative. * - Instruction cache is 2-way set-associative. * - The cache line length is eight words. - * - You can configure the instruction and data caches independently during implementation - * to sizes of 4KB, 8KB, 16KB, 32KB, or 64KB. - * 1.1.3. System design components - * PrimeCell Level 2 Cache Controller (PL310) - * The addition of an on-chip secondary cache, also referred to as a Level 2 or L2 cache, is a - * recognized method of improving the performance of ARM-based systems when significant memory traffic - * is generated by the processor. The PrimeCell Level 2 Cache Controller reduces the number of external - * memory accesses and has been optimized for use with the Cortex-A5 processor. - * 8.1.7. Exclusive L2 cache - * The Cortex-A5 processor can be connected to an L2 cache that supports an exclusive cache mode. - * This mode must be activated both in the Cortex-A5 processor and in the L2 cache controller. + * - You can configure the instruction and data + * caches independently during implementation to sizes + * of 4KB, 8KB, 16KB, 32KB, or 64KB. 1.1.3. System + * design components PrimeCell Level 2 Cache Controller + * (PL310) The addition of an on-chip secondary cache, + * also referred to as a Level 2 or L2 cache, is a + * recognized method of improving the performance of + * ARM-based systems when significant memory traffic is + * generated by the processor. The PrimeCell Level 2 + * Cache Controller reduces the number of external + * memory accesses and has been optimized for use with + * the Cortex-A5 processor. 8.1.7. Exclusive L2 cache + * The Cortex-A5 processor can be connected to an L2 + * cache that supports an exclusive cache mode. This + * mode must be activated both in the Cortex-A5 + * processor and in the L2 cache controller. * * +--------------------+-----------+-----------+----------+-----------+ - * | Processor model | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | L1D cache | L1I cache | L2 + * cache | Reference | * +--------------------+-----------+-----------+----------+-----------+ - * | Qualcomm MSM7225A | | | | | - * | Qualcomm MSM7625A | | | | | - * | Qualcomm MSM7227A | | | | | - * | Qualcomm MSM7627A | 32K | 32K | 256K | Wiki [1] | - * | Qualcomm MSM7225AB | | | | | - * | Qualcomm MSM7225AB | | | | | - * | Qualcomm QSD8250 | | | | | - * | Qualcomm QSD8650 | | | | | + * | Qualcomm MSM7225A | | | | | + * | Qualcomm MSM7625A | | | | | + * | Qualcomm MSM7227A | | | | | + * | Qualcomm MSM7627A | 32K | 32K | 256K + * | Wiki [1] | | Qualcomm MSM7225AB | | | | + * | | Qualcomm MSM7225AB | | | | | + * | Qualcomm QSD8250 | | | | | + * | Qualcomm QSD8650 | | | | | * +--------------------+-----------+-----------+----------+-----------+ - * | Spreadtrum SC6821 | 32K | 32K | ? | | - * | Spreadtrum SC6825 | 32K | 32K | 256K | Wiki [2] | - * | Spreadtrum SC8810 | ? | ? | ? | | - * | Spreadtrum SC8825 | 32K | 32K | ? | | + * | Spreadtrum SC6821 | 32K | 32K | ? + * | | | Spreadtrum SC6825 | 32K | 32K + * | 256K | Wiki [2] | | Spreadtrum SC8810 | ? + * | ? | ? | | | Spreadtrum + * SC8825 | 32K | 32K | ? | | * +--------------------+-----------+-----------+----------+-----------+ * - * [1] https://en.wikipedia.org/wiki/List_of_Qualcomm_Snapdragon_systems-on-chip#Snapdragon_S1 + * [1] + * https://en.wikipedia.org/wiki/List_of_Qualcomm_Snapdragon_systems-on-chip#Snapdragon_S1 * [2] https://en.wikipedia.org/wiki/Spreadtrum */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 2, - .line_size = 32 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 32 - }; - *l2 = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 32}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 32}; + *l2 = (struct cpuinfo_cache){ .size = 256 * 1024, /* - * Follow NXP specification: "Eight-way set-associative 512 kB L2 cache with 32B line size" - * Reference: http://www.nxp.com/assets/documents/data/en/application-notes/AN4947.pdf + * Follow NXP specification: "Eight-way + * set-associative 512 kB L2 cache with 32B line + * size" Reference: + * http://www.nxp.com/assets/documents/data/en/application-notes/AN4947.pdf */ .associativity = 8, - .line_size = 32 - }; + .line_size = 32}; break; case cpuinfo_uarch_cortex_a7: /* * Cortex-A7 MPCore Technical Reference Manual: * 6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. You can configure the - * instruction and data caches independently during implementation to sizes of 8KB, 16KB, 32KB, or 64KB. + * The L1 memory system consists of separate + * instruction and data caches. You can configure the + * instruction and data caches independently during + * implementation to sizes of 8KB, 16KB, 32KB, or 64KB. * - * The L1 instruction memory system has the following features: + * The L1 instruction memory system has the following + * features: * - Instruction side cache line length of 32-bytes. * - 2-way set-associative instruction cache. * - * The L1 data memory system has the following features: + * The L1 data memory system has the following + * features: * - Data side cache line length of 64-bytes. * - 4-way set-associative data cache. * * 7.1. About the L2 Memory system * The L2 memory system consists of an: * - Optional tightly-coupled L2 cache that includes: - * - Configurable L2 cache size of 128KB, 256KB, 512KB, and 1MB. + * - Configurable L2 cache size of 128KB, 256KB, + * 512KB, and 1MB. * - Fixed line length of 64 bytes * - 8-way set-associative cache structure * * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Allwinner A20 | 2 | 32K | 32K | 256K | [1] | - * | Allwinner A23 | 2 | 32K | 32K | 256K | [2] | - * | Allwinner A31 | 4 | 32K | 32K | 1M | [3] | - * | Allwinner A31s | 4 | 32K | 32K | 1M | [4] | - * | Allwinner A33 | 4 | 32K | 32K | 512K | [5] | - * | Allwinner A80 Octa | 4(+4) | 32K | 32K | 512K(+2M) | [6] | - * | Allwinner A81T | 8 | 32K | 32K | 1M | [7] | + * | Allwinner A20 | 2 | 32K | 32K | + * 256K | [1] | | Allwinner A23 | 2 | 32K + * | 32K | 256K | [2] | | Allwinner A31 | + * 4 | 32K | 32K | 1M | [3] | | + * Allwinner A31s | 4 | 32K | 32K | + * 1M | [4] | | Allwinner A33 | 4 | 32K + * | 32K | 512K | [5] | | Allwinner A80 + * Octa | 4(+4) | 32K | 32K | 512K(+2M) | [6] + * | | Allwinner A81T | 8 | 32K | 32K | + * 1M | [7] | * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Broadcom BCM2836 | 4 | 32K | 32K | 512K | [8] | + * | Broadcom BCM2836 | 4 | 32K | 32K | + * 512K | [8] + * | * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Kirin 920 | 4(+4) | ? | ? | 512K | [9] | + * | Kirin 920 | 4(+4) | ? | ? | + * 512K | [9] + * | * +--------------------+-------+-----------+-----------+-----------+-----------+ * * [1] https://linux-sunxi.org/A20 * [2] https://linux-sunxi.org/A23 - * [3] http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20datasheet%20V1.3%2020131106.pdf - * [4] https://github.com/allwinner-zh/documents/blob/master/A31s/A31s_Datasheet_v1.5_20150510.pdf - * [5] http://dl.linux-sunxi.org/A33/A33_Datasheet_release1.0.pdf - * [6] https://linux-sunxi.org/images/1/10/A80_Datasheet_Revision_1.0_0404.pdf - * [7] http://dl.linux-sunxi.org/A83T/A83T_datasheet_Revision_1.1.pdf - * [8] https://www.raspberrypi.org/forums/viewtopic.php?t=98428 - * [9] http://www.gizmochina.com/2014/10/07/hisilicon-kirin-920-tear-down/ + * [3] + * http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20datasheet%20V1.3%2020131106.pdf + * [4] + * https://github.com/allwinner-zh/documents/blob/master/A31s/A31s_Datasheet_v1.5_20150510.pdf + * [5] + * http://dl.linux-sunxi.org/A33/A33_Datasheet_release1.0.pdf + * [6] + * https://linux-sunxi.org/images/1/10/A80_Datasheet_Revision_1.0_0404.pdf + * [7] + * http://dl.linux-sunxi.org/A83T/A83T_datasheet_Revision_1.1.pdf + * [8] + * https://www.raspberrypi.org/forums/viewtopic.php?t=98428 + * [9] + * http://www.gizmochina.com/2014/10/07/hisilicon-kirin-920-tear-down/ */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 2, - .line_size = 32 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = 128 * 1024 * cluster_cores, - .associativity = 8, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 32}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64}; + *l2 = (struct cpuinfo_cache){ + .size = 128 * 1024 * cluster_cores, .associativity = 8, .line_size = 64}; break; case cpuinfo_uarch_cortex_a8: /* * Cortex-A8 Technical Reference Manual: * 7.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches in a Harvard arrangement. - * The L1 memory system provides the core with: + * The L1 memory system consists of separate + * instruction and data caches in a Harvard arrangement. + * The L1 memory system provides the core with: * - fixed line length of 64 bytes * - support for 16KB or 32KB caches * - 4-way set associative cache structure * 8.1. About the L2 memory system - * The L2 memory system is tightly coupled to the L1 data cache and L1 instruction cache. - * The key features of the L2 memory system include: - * - configurable cache size of 0KB, 128KB, 256KB, 512KB, and 1MB + * The L2 memory system is tightly coupled to the L1 + * data cache and L1 instruction cache. The key features + * of the L2 memory system include: + * - configurable cache size of 0KB, 128KB, 256KB, + * 512KB, and 1MB * - fixed line length of 64 bytes * - 8-way set associative cache structure * * +----------------------+-----------+-----------+-----------+-----------+ - * | Processor model | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | L1D cache | L1I cache | L2 + * cache | Reference + * | * +----------------------+-----------+-----------+-----------+-----------+ - * | Exynos 3 Single 3110 | 32K | 32K | 512K | [1] | + * | Exynos 3 Single 3110 | 32K | 32K | + * 512K | [1] | * +----------------------+-----------+-----------+-----------+-----------+ - * | TI DM 3730 | 32K | 32K | 256K | [2] | + * | TI DM 3730 | 32K | 32K | + * 256K | [2] | * +----------------------+-----------+-----------+-----------+-----------+ * - * [1] https://en.wikichip.org/w/images/0/04/Exynos_3110.pdf + * [1] + * https://en.wikichip.org/w/images/0/04/Exynos_3110.pdf * [2] https://www.ti.com/lit/ds/symlink/dm3725.pdf */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .associativity = 8, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64}; + *l2 = (struct cpuinfo_cache){.associativity = 8, .line_size = 64}; switch (chipset->vendor) { case cpuinfo_arm_chipset_vendor_samsung: l2->size = 512 * 1024; @@ -273,111 +254,117 @@ void cpuinfo_arm_decode_cache( /* * ARM Cortex‑A9 Technical Reference Manual: * 7.1.1 Memory system - * The Cortex‑A9 processor has separate instruction and data caches. - * The caches have the following features: + * The Cortex‑A9 processor has separate instruction + * and data caches. The caches have the following + * features: * - Both caches are 4-way set-associative. * - The cache line length is eight words. - * - You can configure the instruction and data caches independently during implementation - * to sizes of 16KB, 32KB, or 64KB. - * 8.1.5 Exclusive L2 cache - * The Cortex‑A9 processor can be connected to an L2 cache that supports an exclusive cache mode. - * This mode must be activated both in the Cortex‑A9 processor and in the L2 cache controller. + * - You can configure the instruction and data + * caches independently during implementation to sizes + * of 16KB, 32KB, or 64KB. 8.1.5 Exclusive L2 cache The + * Cortex‑A9 processor can be connected to an L2 cache + * that supports an exclusive cache mode. This mode must + * be activated both in the Cortex‑A9 processor and in + * the L2 cache controller. * * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Exynos 4 Dual 4210 | 2 | 32K | 32K | 1M | [1] | - * | Exynos 4 Dual 4212 | 2 | 32K | 32K | 1M | [2] | - * | Exynos 4 Quad 4412 | 4 | 32K | 32K | 1M | [3] | - * | Exynos 4 Quad 4415 | 4 | 32K | 32K | 1M | | - * | TI OMAP 4430 | 2 | 32K | 32K | 1M | [4] | - * | TI OMAP 4460 | 2 | 32K | 32K | 1M | [5] | + * | Exynos 4 Dual 4210 | 2 | 32K | 32K | + * 1M | [1] | | Exynos 4 Dual 4212 | 2 | 32K + * | 32K | 1M | [2] | | Exynos 4 Quad + * 4412 | 4 | 32K | 32K | 1M | [3] + * | | Exynos 4 Quad 4415 | 4 | 32K | 32K + * | 1M | | | TI OMAP 4430 | 2 | 32K + * | 32K | 1M | [4] | | TI OMAP 4460 | + * 2 | 32K | 32K | 1M | [5] | * +--------------------+-------+-----------+-----------+-----------+-----------+ * - * [1] http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Dual_45nm_User_Manaul_Public_REV1.00-0.pdf - * [2] http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Dual_32nm_User_Manaul_Public_REV100-0.pdf - * [3] http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Quad_User_Manaul_Public_REV1.00-0.pdf - * [4] https://www.hotchips.org/wp-content/uploads/hc_archives/hc21/2_mon/HC21.24.400.ClientProcessors-Epub/HC21.24.421.Witt-OMAP4430.pdf - * [5] http://www.anandtech.com/show/5310/samsung-galaxy-nexus-ice-cream-sandwich-review/9 + * [1] + * http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Dual_45nm_User_Manaul_Public_REV1.00-0.pdf + * [2] + * http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Dual_32nm_User_Manaul_Public_REV100-0.pdf + * [3] + * http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Quad_User_Manaul_Public_REV1.00-0.pdf + * [4] + * https://www.hotchips.org/wp-content/uploads/hc_archives/hc21/2_mon/HC21.24.400.ClientProcessors-Epub/HC21.24.421.Witt-OMAP4430.pdf + * [5] + * http://www.anandtech.com/show/5310/samsung-galaxy-nexus-ice-cream-sandwich-review/9 */ /* Use Exynos 4 specs */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 32 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 32 - }; - *l2 = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 32}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 32}; + *l2 = (struct cpuinfo_cache){ .size = 1024 * 1024, - /* OMAP4460 in Pandaboard ES has 16-way set-associative L2 cache */ + /* OMAP4460 in Pandaboard ES has 16-way + set-associative L2 cache */ .associativity = 16, - .line_size = 32 - }; + .line_size = 32}; break; case cpuinfo_uarch_cortex_a15: /* * 6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. - * The L1 instruction memory system has the following features: + * The L1 memory system consists of separate + * instruction and data caches. The L1 instruction + * memory system has the following features: * - 32KB 2-way set-associative instruction cache. * - Fixed line length of 64 bytes. - * The L1 data memory system has the following features: + * The L1 data memory system has the following + * features: * - 32KB 2-way set-associative data cache. * - Fixed line length of 64 bytes. * 7.1. About the L2 memory system * The features of the L2 memory system include: - * - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB. + * - Configurable L2 cache size of 512KB, 1MB, 2MB + * and 4MB. * - Fixed line length of 64 bytes. * - 16-way set-associative cache structure. * * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Exynos 5 Dual 5250 | 2 | 32K | 32K | 1M | [1] | - * | Exynos 5 Hexa 5260 | 2(+4) | 32K | 32K | 1M(+512K) | [2] | - * | Exynos 5 Octa 5410 | 4(+4) | 32K | 32K | 2M(+512K) | [3] | - * | Exynos 5 Octa 5420 | 4(+4) | 32K | 32K | 2M(+512K) | [3] | - * | Exynos 5 Octa 5422 | 4(+4) | 32K | 32K | 2M(+512K) | [3] | - * | Exynos 5 Octa 5430 | 4(+4) | 32K | 32K | 2M(+512K) | [3] | - * | Exynos 5 Octa 5800 | 4(+4) | 32K | 32K | 2M(+512K) | [3] | - * | Kirin 920 | 4(+4) | ? | ? | 2M(+512K) | [4] | + * | Exynos 5 Dual 5250 | 2 | 32K | 32K | + * 1M | [1] | | Exynos 5 Hexa 5260 | 2(+4) | 32K + * | 32K | 1M(+512K) | [2] | | Exynos 5 Octa + * 5410 | 4(+4) | 32K | 32K | 2M(+512K) | + * [3] | | Exynos 5 Octa 5420 | 4(+4) | 32K | + * 32K | 2M(+512K) | [3] | | Exynos 5 Octa 5422 | + * 4(+4) | 32K | 32K | 2M(+512K) | [3] | + * | Exynos 5 Octa 5430 | 4(+4) | 32K | 32K | + * 2M(+512K) | [3] | | Exynos 5 Octa 5800 | 4(+4) + * | 32K | 32K | 2M(+512K) | [3] | | + * Kirin 920 | 4(+4) | ? | ? | + * 2M(+512K) | [4] | * +--------------------+-------+-----------+-----------+-----------+-----------+ * - * [1] http://www.arndaleboard.org/wiki/downloads/supports/Exynos_5_Dual_User_Manaul_Public_REV1.00.pdf - * [2] http://www.yicsystem.com/wp-content/uploads/2014/08/Espresso5260P-Guide-Book.pdf - * [3] http://www.anandtech.com/show/6768/samsung-details-exynos-5-octa-architecture-power-at-isscc-13 - * [4] http://www.gizmochina.com/2014/10/07/hisilicon-kirin-920-tear-down/ + * [1] + * http://www.arndaleboard.org/wiki/downloads/supports/Exynos_5_Dual_User_Manaul_Public_REV1.00.pdf + * [2] + * http://www.yicsystem.com/wp-content/uploads/2014/08/Espresso5260P-Guide-Book.pdf + * [3] + * http://www.anandtech.com/show/6768/samsung-details-exynos-5-octa-architecture-power-at-isscc-13 + * [4] + * http://www.gizmochina.com/2014/10/07/hisilicon-kirin-920-tear-down/ */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 2, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 2, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = cluster_cores * 512 * 1024, - .associativity = 16, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 64}; + *l2 = (struct cpuinfo_cache){ + .size = cluster_cores * 512 * 1024, .associativity = 16, .line_size = 64}; break; case cpuinfo_uarch_cortex_a17: /* - * ARM Cortex-A17 MPCore Processor Technical Reference Manual: - * 6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. - * The size of the instruction cache is implemented as either 32KB or 64KB. - * The size of the data cache is 32KB. + * ARM Cortex-A17 MPCore Processor Technical Reference + * Manual: 6.1. About the L1 memory system The L1 memory + * system consists of separate instruction and data + * caches. The size of the instruction cache is + * implemented as either 32KB or 64KB. The size of the + * data cache is 32KB. * - * The L1 instruction cache has the following features: + * The L1 instruction cache has the following + * features: * - Instruction side cache line length of 64-bytes. * - 4-way set-associative instruction cache. * @@ -387,138 +374,158 @@ void cpuinfo_arm_decode_cache( * * 7.1. About the L2 Memory system * An integrated L2 cache: - * - The cache size is implemented as either 256KB, 512KB, 1MB, 2MB, 4MB or 8MB. + * - The cache size is implemented as either 256KB, + * 512KB, 1MB, 2MB, 4MB or 8MB. * - A fixed line length of 64 bytes. * - 16-way set-associative cache structure. * * +------------------+-------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache | + * L2 cache | Reference | * +------------------+-------+-----------+-----------+-----------+-----------+ - * | MediaTek MT6595 | 4(+4) | 32K | 32K | 2M(+512K) | [1] | + * | MediaTek MT6595 | 4(+4) | 32K | 32K | + * 2M(+512K) | [1] | * +------------------+-------+-----------+-----------+-----------+-----------+ * * [1] https://blog.osakana.net/archives/5268 */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = cluster_cores * 512 * 1024, - .associativity = 16, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64}; + *l2 = (struct cpuinfo_cache){ + .size = cluster_cores * 512 * 1024, .associativity = 16, .line_size = 64}; break; #endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__) */ case cpuinfo_uarch_cortex_a35: /* * ARM Cortex‑A35 Processor Technical Reference Manual: * 6.1. About the L1 memory system - * The L1 memory system includes several power-saving and performance-enhancing features. - * These include separate instruction and data caches, which can be configured - * independently during implementation to sizes of 8KB, 16KB, 32KB, or 64KB. + * The L1 memory system includes several power-saving + * and performance-enhancing features. These include + * separate instruction and data caches, which can be + * configured independently during implementation to + * sizes of 8KB, 16KB, 32KB, or 64KB. * * L1 instruction-side memory system * A dedicated instruction cache that: * - is virtually indexed and physically tagged. * - is 2-way set associative. - * - is configurable to be 8KB, 16KB, 32KB, or 64KB. + * - is configurable to be 8KB, 16KB, 32KB, or + * 64KB. * - uses a cache line length of 64 bytes. * * L1 data-side memory system * A dedicated data cache that: * - is physically indexed and physically tagged. * - is 4-way set associative. - * - is configurable to be 8KB, 16KB, 32KB, or 64KB. + * - is configurable to be 8KB, 16KB, 32KB, or + * 64KB. * - uses a cache line length of 64 bytes. * * 7.1. About the L2 memory system * The L2 cache is 8-way set associative. * Further features of the L2 cache are: - * - Configurable size of 128KB, 256KB, 512KB, and 1MB. + * - Configurable size of 128KB, 256KB, 512KB, and + * 1MB. * - Fixed line length of 64 bytes. * - Physically indexed and tagged. * * +-----------------+---------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | Reference | * +-----------------+---------+-----------+-----------+-----------+-----------+ - * | MediaTek MT6599 | 4(+4+2) | ? | ? | ? | | + * | MediaTek MT6599 | 4(+4+2) | ? | ? | ? + * | | * +-----------------+---------+-----------+-----------+-----------+-----------+ */ - *l1i = (struct cpuinfo_cache) { - .size = 16 * 1024, /* assumption based on low-end Cortex-A53 */ + *l1i = (struct cpuinfo_cache){ + .size = 16 * 1024, /* assumption based on + low-end Cortex-A53 */ .associativity = 2, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 16 * 1024, /* assumption based on low-end Cortex-A53 */ + .line_size = 64}; + *l1d = (struct cpuinfo_cache){ + .size = 16 * 1024, /* assumption based on + low-end Cortex-A53 */ .associativity = 4, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = 256 * 1024, /* assumption based on low-end Cortex-A53 */ + .line_size = 64}; + *l2 = (struct cpuinfo_cache){ + .size = 256 * 1024, /* assumption based on + low-end Cortex-A53 */ .associativity = 8, - .line_size = 64 - }; + .line_size = 64}; break; case cpuinfo_uarch_cortex_a53: /* - * ARM Cortex-A53 MPCore Processor Technical Reference Manual: - * 6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. The implementer configures the - * instruction and data caches independently during implementation, to sizes of 8KB, 16KB, 32KB, or 64KB. + * ARM Cortex-A53 MPCore Processor Technical Reference + * Manual: 6.1. About the L1 memory system The L1 memory + * system consists of separate instruction and data + * caches. The implementer configures the instruction + * and data caches independently during implementation, + * to sizes of 8KB, 16KB, 32KB, or 64KB. * - * The L1 Instruction memory system has the following key features: + * The L1 Instruction memory system has the following + * key features: * - Instruction side cache line length of 64 bytes. * - 2-way set associative L1 Instruction cache. * - * The L1 Data memory system has the following features: + * The L1 Data memory system has the following + * features: * - Data side cache line length of 64 bytes. * - 4-way set associative L1 Data cache. * * 7.1. About the L2 memory system * The L2 memory system consists of an: * - Optional tightly-coupled L2 cache that includes: - * - Configurable L2 cache size of 128KB, 256KB, 512KB, 1MB and 2MB. + * - Configurable L2 cache size of 128KB, 256KB, + * 512KB, 1MB and 2MB. * - Fixed line length of 64 bytes. * - 16-way set-associative cache structure. * * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Broadcom BCM2837 | 4 | 16K | 16K | 512K | [1] | - * | Exynos 7420 | 4(+4) | 32K | 32K | 256K | [2, 3] | - * | Exynos 8890 | 4(+4) | 32K | 32K | 256K | [4] | - * | Rochchip RK3368 | 4+4 | 32K | 32K | 512K+256K | sysfs | - * | MediaTek MT8173C | 2(+2) | 32K | 32K | 512K(+1M) | sysfs | - * | Snapdragon 410 | 4 | 32K | 32K | 512K | [3] | - * | Snapdragon 630 | 4+4 | 32K | 32K | 1M+512K | sysfs | - * | Snapdragon 636 | 4(+4) | 32K+64K | 32K+64K | 1M+1M | sysfs | - * | Snapdragon 660 | 4(+4) | 32K+64K | 32K+64K | 1M+1M | sysfs | - * | Snapdragon 835 | 4(+4) | 32K+64K | 32K+64K | 1M(+2M) | sysfs | - * | Kirin 620 | 4+4 | 32K | 32K | 512K | [5] | + * | Broadcom BCM2837 | 4 | 16K | 16K | + * 512K | [1] | | Exynos 7420 | 4(+4) | 32K + * | 32K | 256K | [2, 3] | | Exynos 8890 | + * 4(+4) | 32K | 32K | 256K | [4] | | + * Rochchip RK3368 | 4+4 | 32K | 32K | + * 512K+256K | sysfs | | MediaTek MT8173C | 2(+2) + * | 32K | 32K | 512K(+1M) | sysfs | | + * Snapdragon 410 | 4 | 32K | 32K | + * 512K | [3] | | Snapdragon 630 | 4+4 | + * 32K | 32K | 1M+512K | sysfs | | + * Snapdragon 636 | 4(+4) | 32K+64K | 32K+64K | + * 1M+1M | sysfs | | Snapdragon 660 | 4(+4) | + * 32K+64K | 32K+64K | 1M+1M | sysfs | | + * Snapdragon 835 | 4(+4) | 32K+64K | 32K+64K | + * 1M(+2M) | sysfs | | Kirin 620 | 4+4 | + * 32K | 32K | 512K | [5] + * | * +--------------------+-------+-----------+-----------+-----------+-----------+ * - * [1] https://www.raspberrypi.org/forums/viewtopic.php?f=91&t=145766 - * [2] http://www.anandtech.com/show/9330/exynos-7420-deep-dive/2 - * [3] https://www.usenix.org/system/files/conference/usenixsecurity16/sec16_paper_lipp.pdf - * [4] http://www.boardset.com/products/products_v8890.php - * [5] http://mirror.lemaker.org/Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf + * [1] + * https://www.raspberrypi.org/forums/viewtopic.php?f=91&t=145766 + * [2] + * http://www.anandtech.com/show/9330/exynos-7420-deep-dive/2 + * [3] + * https://www.usenix.org/system/files/conference/usenixsecurity16/sec16_paper_lipp.pdf + * [4] + * http://www.boardset.com/products/products_v8890.php + * [5] + * http://mirror.lemaker.org/Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf */ if (midr_is_qualcomm_cortex_a53_silver(midr)) { - /* Qualcomm-modified Cortex-A53 in Snapdragon 630/660/835 */ + /* Qualcomm-modified Cortex-A53 in Snapdragon + * 630/660/835 */ uint32_t l2_size = 512 * 1024; switch (chipset->series) { case cpuinfo_arm_chipset_series_qualcomm_msm: if (chipset->model == 8998) { - /* Snapdragon 835 (MSM8998): 1 MB L2 (little cores only) */ + /* Snapdragon 835 + * (MSM8998): 1 MB L2 + * (little cores only) + */ l2_size = 1024 * 1024; } break; @@ -526,16 +533,30 @@ void cpuinfo_arm_decode_cache( switch (chipset->model) { case 630: if (cluster_id == 0) { - /* Snapdragon 630: 1 MB L2 for the big cores */ + /* Snapdragon + * 630: + * 1 MB + * L2 + * for + * the + * big + * cores + */ l2_size = 1024 * 1024; } break; case 636: - /* Snapdragon 636: 1 MB L2 (little cores only) */ + /* Snapdragon + * 636: 1 MB L2 + * (little cores + * only) */ l2_size = 1024 * 1024; break; case 660: - /* Snapdragon 660: 1 MB L2 (little cores only) */ + /* Snapdragon + * 660: 1 MB L2 + * (little cores + * only) */ l2_size = 1024 * 1024; break; } @@ -544,21 +565,9 @@ void cpuinfo_arm_decode_cache( break; } - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 2, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = l2_size, - .associativity = 16, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64}; + *l2 = (struct cpuinfo_cache){.size = l2_size, .associativity = 16, .line_size = 64}; } else { /* Standard Cortex-A53 */ @@ -570,22 +579,42 @@ void cpuinfo_arm_decode_cache( l1_size = 32 * 1024; l2_size = 512 * 1024; switch (chipset->model) { - case 8937: /* Snapdragon 430 */ - case 8940: /* Snapdragon 435 */ - case 8953: /* Snapdragon 625 or 626 (8953PRO) */ + case 8937: /* Snapdragon + 430 */ + case 8940: /* Snapdragon + 435 */ + case 8953: /* Snapdragon + 625 or 626 + (8953PRO) + */ if (cluster_id == 0) { - /* 1M L2 for big cluster */ + /* 1M L2 + * for + * big + * cluster + */ l2_size = 1024 * 1024; } break; - case 8952: /* Snapdragon 617 */ + case 8952: /* Snapdragon + 617 */ if (cluster_id != 0) { - /* 256K L2 for LITTLE cluster */ + /* 256K + * L2 + * for + * LITTLE + * cluster + */ l2_size = 256 * 1024; } break; default: - /* Silence compiler warning about unhandled enum values */ + /* Silence + * compiler + * warning about + * unhandled + * enum values + */ break; } break; @@ -597,7 +626,8 @@ void cpuinfo_arm_decode_cache( l1_size = 32 * 1024; l2_size = 512 * 1024; if (chipset->model == 450 && cluster_id == 0) { - /* Snapdragon 450: 1M L2 for big cluster */ + /* Snapdragon 450: 1M L2 + * for big cluster */ l2_size = 1024 * 1024; } break; @@ -608,7 +638,8 @@ void cpuinfo_arm_decode_cache( case cpuinfo_arm_chipset_series_hisilicon_kirin: l1_size = 32 * 1024; switch (chipset->model) { - case 970: /* Kirin 970 */ + case 970: /* Kirin 970 + */ l2_size = 1024 * 1024; break; default: @@ -629,7 +660,14 @@ void cpuinfo_arm_decode_cache( switch (chipset->model) { case 3368: if (cluster_id == 0) { - /* RK3368: 512 KB L2 for the big cores */ + /* RK3368: + * 512 + * KB L2 + * for + * the + * big + * cores + */ l2_size = 512 * 1024; } break; @@ -646,24 +684,14 @@ void cpuinfo_arm_decode_cache( l1_size = 32 * 1024; break; default: - /* Silence compiler warning about unhandled enum values */ + /* Silence compiler warning + * about unhandled enum values + */ break; } - *l1i = (struct cpuinfo_cache) { - .size = l1_size, - .associativity = 2, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = l1_size, - .associativity = 4, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = l2_size, - .associativity = 16, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = l1_size, .associativity = 2, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = l1_size, .associativity = 4, .line_size = 64}; + *l2 = (struct cpuinfo_cache){.size = l2_size, .associativity = 16, .line_size = 64}; } break; case cpuinfo_uarch_cortex_a55r0: @@ -671,12 +699,16 @@ void cpuinfo_arm_decode_cache( /* * ARM Cortex-A55 Core Technical Reference Manual * A6.1. About the L1 memory system - * The Cortex®-A55 core's L1 memory system enhances core performance and power efficiency. - * It consists of separate instruction and data caches. You can configure instruction and data caches - * independently during implementation to sizes of 16KB, 32KB, or 64KB. + * The Cortex®-A55 core's L1 memory system enhances + * core performance and power efficiency. It consists of + * separate instruction and data caches. You can + * configure instruction and data caches independently + * during implementation to sizes of 16KB, 32KB, or + * 64KB. * * L1 instruction-side memory system - * The L1 instruction-side memory system provides an instruction stream to the DPU. Its key features are: + * The L1 instruction-side memory system provides an + * instruction stream to the DPU. Its key features are: * - 64-byte instruction side cache line length. * - 4-way set associative L1 instruction cache. * @@ -685,10 +717,12 @@ void cpuinfo_arm_decode_cache( * - 4-way set associative L1 data cache. * * A7.1 About the L2 memory system - * The Cortex-A55 L2 memory system is required to interface the Cortex-A55 cores to the L3 memory system. - * The L2 memory subsystem consists of: - * - An optional 4-way, set-associative L2 cache with a configurable size of 64KB, 128KB or 256KB. Cache - * lines have a fixed length of 64 bytes. + * The Cortex-A55 L2 memory system is required to + * interface the Cortex-A55 cores to the L3 memory + * system. The L2 memory subsystem consists of: + * - An optional 4-way, set-associative L2 cache with + * a configurable size of 64KB, 128KB or 256KB. Cache + * lines have a fixed length of 64 bytes. * * The main features of the L2 memory system are: * - Strictly exclusive with L1 data cache. @@ -696,23 +730,30 @@ void cpuinfo_arm_decode_cache( * - Private per-core unified L2 cache. * * +--------------------+-------+-----------+-----------+-----------+----------+------------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | L3 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+----------+------------+ - * | Snapdragon 845 | 4(+4) | 32K | 32K | 128K | 2M | [1], sysfs | - * | Exynos 9810 | 4(+4) | ? | ? | None | 512K | [2] | - * | Kirin 980 | 4(+4) | 32K | 32K | 128K | 4M | [3] | + * | Snapdragon 845 | 4(+4) | 32K | 32K | + * 128K | 2M | [1], sysfs | | Exynos 9810 | + * 4(+4) | ? | ? | None | 512K | + * [2] | | Kirin 980 | 4(+4) | 32K | 32K + * | 128K | 4M | [3] | * +--------------------+-------+-----------+-----------+-----------+----------+------------+ * - * [1] https://www.anandtech.com/show/12114/qualcomm-announces-snapdragon-845-soc - * [2] https://www.anandtech.com/show/12478/exynos-9810-handson-awkward-first-results + * [1] + * https://www.anandtech.com/show/12114/qualcomm-announces-snapdragon-845-soc + * [2] + * https://www.anandtech.com/show/12478/exynos-9810-handson-awkward-first-results * [3] https://en.wikichip.org/wiki/hisilicon/kirin/980 */ if (midr_is_qualcomm_cortex_a55_silver(midr)) { - /* Qualcomm-modified Cortex-A55 in Snapdragon 670 / 710 / 845 */ + /* Qualcomm-modified Cortex-A55 in Snapdragon + * 670 / 710 / 845 */ uint32_t l3_size = 1024 * 1024; switch (chipset->series) { case cpuinfo_arm_chipset_series_qualcomm_snapdragon: - /* Snapdragon 845: 2M L3 cache */ + /* Snapdragon 845: 2M L3 cache + */ if (chipset->model == 845) { l3_size = 2 * 1024 * 1024; } @@ -721,22 +762,22 @@ void cpuinfo_arm_decode_cache( break; } - *l1i = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){ .size = 32 * 1024, .associativity = 4, .line_size = 64, }; - *l1d = (struct cpuinfo_cache) { + *l1d = (struct cpuinfo_cache){ .size = 32 * 1024, .associativity = 4, .line_size = 64, }; - *l2 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ .size = 128 * 1024, .associativity = 4, .line_size = 64, }; - *l3 = (struct cpuinfo_cache) { + *l3 = (struct cpuinfo_cache){ .size = l3_size, .associativity = 16, .line_size = 64, @@ -744,18 +785,18 @@ void cpuinfo_arm_decode_cache( } else { /* Standard Cortex-A55 */ - *l1i = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){ .size = 32 * 1024, .associativity = 4, .line_size = 64, }; - *l1d = (struct cpuinfo_cache) { + *l1d = (struct cpuinfo_cache){ .size = 32 * 1024, .associativity = 4, .line_size = 64, }; if (chipset->series == cpuinfo_arm_chipset_series_samsung_exynos) { - *l2 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ .size = 512 * 1024, /* DynamIQ */ .associativity = 16, @@ -765,7 +806,8 @@ void cpuinfo_arm_decode_cache( uint32_t l3_size = 1024 * 1024; switch (chipset->series) { case cpuinfo_arm_chipset_series_hisilicon_kirin: - /* Kirin 980: 4M L3 cache */ + /* Kirin 980: 4M L3 + * cache */ if (chipset->model == 980) { l3_size = 4 * 1024 * 1024; } @@ -773,12 +815,12 @@ void cpuinfo_arm_decode_cache( default: break; } - *l2 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ .size = 128 * 1024, .associativity = 4, .line_size = 64, }; - *l3 = (struct cpuinfo_cache) { + *l3 = (struct cpuinfo_cache){ .size = l3_size, /* DynamIQ */ .associativity = 16, @@ -789,65 +831,67 @@ void cpuinfo_arm_decode_cache( break; case cpuinfo_uarch_cortex_a57: /* - * ARM Cortex-A57 MPCore Processor Technical Reference Manual: - * 6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. + * ARM Cortex-A57 MPCore Processor Technical Reference + * Manual: 6.1. About the L1 memory system The L1 memory + * system consists of separate instruction and data + * caches. * - * The L1 instruction memory system has the following features: + * The L1 instruction memory system has the following + * features: * - 48KB 3-way set-associative instruction cache. * - Fixed line length of 64 bytes. * - * The L1 data memory system has the following features: + * The L1 data memory system has the following + * features: * - 32KB 2-way set-associative data cache. * - Fixed line length of 64 bytes. * * 7.1 About the L2 memory system * The features of the L2 memory system include: - * - Configurable L2 cache size of 512KB, 1MB, and 2MB. + * - Configurable L2 cache size of 512KB, 1MB, and + * 2MB. * - Fixed line length of 64 bytes. * - 16-way set-associative cache structure. * - Inclusion property with L1 data caches. * * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Snapdragon 810 | 4(+4) | 32K | 48K | 2M | [1] | - * | Exynos 7420 | 4(+4) | 32K | 48K | 2M | [2] | - * | Jetson TX1 | 4 | 32K | 48K | 2M | [3] | + * | Snapdragon 810 | 4(+4) | 32K | 48K | + * 2M | [1] | | Exynos 7420 | 4(+4) | 32K + * | 48K | 2M | [2] | | Jetson TX1 | 4 + * | 32K | 48K | 2M | [3] | * +--------------------+-------+-----------+-----------+-----------+-----------+ * - * [1] http://www.anandtech.com/show/9837/snapdragon-820-preview - * [2] http://www.anandtech.com/show/9330/exynos-7420-deep-dive/2 - * [3] https://devblogs.nvidia.com/parallelforall/jetson-tx2-delivers-twice-intelligence-edge/ + * [1] + * http://www.anandtech.com/show/9837/snapdragon-820-preview + * [2] + * http://www.anandtech.com/show/9330/exynos-7420-deep-dive/2 + * [3] + * https://devblogs.nvidia.com/parallelforall/jetson-tx2-delivers-twice-intelligence-edge/ */ - *l1i = (struct cpuinfo_cache) { - .size = 48 * 1024, - .associativity = 3, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 2, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){.size = 48 * 1024, .associativity = 3, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 64}; + *l2 = (struct cpuinfo_cache){ .size = cluster_cores * 512 * 1024, .associativity = 16, .line_size = 64, - .flags = CPUINFO_CACHE_INCLUSIVE - }; + .flags = CPUINFO_CACHE_INCLUSIVE}; break; - case cpuinfo_uarch_cortex_a65: - { + case cpuinfo_uarch_cortex_a65: { /* * ARM Cortex‑A65 Core Technical Reference Manual * A6.1. About the L1 memory system - * The L1 memory system enhances the performance and power efficiency in the Cortex‑A65 core. - * It consists of separate instruction and data caches. You can configure instruction and data caches - * independently during implementation to sizes of 32KB or 64KB. + * The L1 memory system enhances the performance and + * power efficiency in the Cortex‑A65 core. It consists + * of separate instruction and data caches. You can + * configure instruction and data caches independently + * during implementation to sizes of 32KB or 64KB. * * L1 instruction-side memory system - * The L1 instruction-side memory system provides an instruction stream to the DPU. Its key features are: + * The L1 instruction-side memory system provides an + * instruction stream to the DPU. Its key features are: * - 64-byte instruction side cache line length. * - 4-way set associative L1 instruction cache. * @@ -856,10 +900,12 @@ void cpuinfo_arm_decode_cache( * - 4-way set associative L1 data cache. * * A7.1 About the L2 memory system - * The Cortex‑A65 L2 memory system is required to interface the Cortex‑A65 cores to the L3 memory system. - * The L2 memory subsystem consists of: - * - An optional 4-way, set-associative L2 cache with a configurable size of 64KB, 128KB, or 256KB. - * Cache lines have a fixed length of 64 bytes. + * The Cortex‑A65 L2 memory system is required to + * interface the Cortex‑A65 cores to the L3 memory + * system. The L2 memory subsystem consists of: + * - An optional 4-way, set-associative L2 cache with + * a configurable size of 64KB, 128KB, or 256KB. Cache + * lines have a fixed length of 64 bytes. * * The main features of the L2 memory system are: * - Strictly exclusive with L1 data cache. @@ -869,23 +915,19 @@ void cpuinfo_arm_decode_cache( const uint32_t l1_size = 32 * 1024; const uint32_t l2_size = 128 * 1024; const uint32_t l3_size = 512 * 1024; - *l1i = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){ .size = l1_size, .associativity = 4, .line_size = 64, }; - *l1d = (struct cpuinfo_cache) { + *l1d = (struct cpuinfo_cache){ .size = l1_size, .associativity = 4, .line_size = 64, }; - *l2 = (struct cpuinfo_cache) { - .size = l2_size, - .associativity = 4, - .line_size = 64, - .flags = CPUINFO_CACHE_INCLUSIVE - }; - *l3 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ + .size = l2_size, .associativity = 4, .line_size = 64, .flags = CPUINFO_CACHE_INCLUSIVE}; + *l3 = (struct cpuinfo_cache){ .size = l3_size, /* DynamIQ */ .associativity = 16, @@ -893,49 +935,63 @@ void cpuinfo_arm_decode_cache( }; break; } - case cpuinfo_uarch_cortex_a72: - { + case cpuinfo_uarch_cortex_a72: { /* - * ARM Cortex-A72 MPCore Processor Technical Reference Manual - * 6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. + * ARM Cortex-A72 MPCore Processor Technical Reference + * Manual 6.1. About the L1 memory system The L1 memory + * system consists of separate instruction and data + * caches. * - * The L1 instruction memory system has the following features: + * The L1 instruction memory system has the following + * features: * - 48KB 3-way set-associative instruction cache. * - Fixed line length of 64 bytes. * - * The L1 data memory system has the following features: + * The L1 data memory system has the following + * features: * - 32KB 2-way set-associative data cache. * - Fixed cache line length of 64 bytes. * * 7.1 About the L2 memory system * The features of the L2 memory system include: - * - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB. + * - Configurable L2 cache size of 512KB, 1MB, 2MB + * and 4MB. * - Fixed line length of 64 bytes. * - Banked pipeline structures. * - Inclusion property with L1 data caches. * - 16-way set-associative cache structure. * * +---------------------+---------+-----------+-----------+------------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I + * cache | L2 cache | Reference | * +---------------------+---------+-----------+-----------+------------+-----------+ - * | Snapdragon 650 | 2(+4) | 32K(+32K) | 48K(+32K) | 1M(+512K) | [1] | - * | Snapdragon 652 | 4(+4) | 32K(+32K) | 48K(+32K) | 1M(+512K) | [2] | - * | Snapdragon 653 | 4(+4) | 32K(+32K) | 48K(+32K) | 1M(+512K) | [3] | - * | HiSilicon Kirin 950 | 4(+4) | 32K+32K | 48K+32K | ? | | - * | HiSilicon Kirin 955 | 4(+4) | 32K+32K | 48K+32K | ? | | - * | MediaTek MT8173C | 2(+2) | 32K(+32K) | 48K(+32K) | 1M(+512K) | sysfs | - * | MediaTek Helio X20 | 2(+4+4) | ? | ? | ? | | - * | MediaTek Helio X23 | 2(+4+4) | ? | ? | ? | | - * | MediaTek Helio X25 | 2(+4+4) | ? | ? | ? | | - * | MediaTek Helio X27 | 2(+4+4) | ? | ? | ? | | - * | Broadcom BCM2711 | 4 | 32K | 48K | 1M | [4] | + * | Snapdragon 650 | 2(+4) | 32K(+32K) | + * 48K(+32K) | 1M(+512K) | [1] | | Snapdragon 652 | + * 4(+4) | 32K(+32K) | 48K(+32K) | 1M(+512K) | [2] + * | | Snapdragon 653 | 4(+4) | 32K(+32K) | + * 48K(+32K) | 1M(+512K) | [3] | | HiSilicon + * Kirin 950 | 4(+4) | 32K+32K | 48K+32K | ? | + * | | HiSilicon Kirin 955 | 4(+4) | 32K+32K | + * 48K+32K | ? | | | MediaTek + * MT8173C | 2(+2) | 32K(+32K) | 48K(+32K) | + * 1M(+512K) | sysfs | | MediaTek Helio X20 | + * 2(+4+4) | ? | ? | ? | | | + * MediaTek Helio X23 | 2(+4+4) | ? | ? | + * ? | | | MediaTek Helio X25 | 2(+4+4) | ? | + * ? | ? | | | MediaTek Helio X27 | + * 2(+4+4) | ? | ? | ? | | | + * Broadcom BCM2711 | 4 | 32K | 48K | + * 1M | [4] | * +---------------------+---------+-----------+-----------+------------+-----------+ * - * [1] http://pdadb.net/index.php?m=processor&id=578&c=qualcomm_snapdragon_618_msm8956__snapdragon_650 - * [2] http://pdadb.net/index.php?m=processor&id=667&c=qualcomm_snapdragon_620_apq8076__snapdragon_652 - * [3] http://pdadb.net/index.php?m=processor&id=692&c=qualcomm_snapdragon_653_msm8976sg__msm8976_pro - * [4] https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/README.md + * [1] + * http://pdadb.net/index.php?m=processor&id=578&c=qualcomm_snapdragon_618_msm8956__snapdragon_650 + * [2] + * http://pdadb.net/index.php?m=processor&id=667&c=qualcomm_snapdragon_620_apq8076__snapdragon_652 + * [3] + * http://pdadb.net/index.php?m=processor&id=692&c=qualcomm_snapdragon_653_msm8976sg__msm8976_pro + * [4] + * https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/README.md */ uint32_t l2_size; switch (chipset->series) { @@ -947,66 +1003,72 @@ void cpuinfo_arm_decode_cache( break; } - *l1i = (struct cpuinfo_cache) { - .size = 48 * 1024, - .associativity = 3, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 2, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){.size = 48 * 1024, .associativity = 3, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 64}; + *l2 = (struct cpuinfo_cache){ .size = l2_size, .associativity = 16, .line_size = 64, - .flags = CPUINFO_CACHE_INCLUSIVE - }; + .flags = CPUINFO_CACHE_INCLUSIVE}; break; } - case cpuinfo_uarch_cortex_a73: - { + case cpuinfo_uarch_cortex_a73: { /* - * ARM Cortex‑A73 MPCore Processor Technical Reference Manual - * 6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. - * The size of the instruction cache is 64KB. - * The size of the data cache is configurable to either 32KB or 64KB. + * ARM Cortex‑A73 MPCore Processor Technical Reference + * Manual 6.1. About the L1 memory system The L1 memory + * system consists of separate instruction and data + * caches. The size of the instruction cache is 64KB. + * The size of the data cache is configurable to either + * 32KB or 64KB. * - * The L1 instruction memory system has the following key features: - * - Virtually Indexed, Physically Tagged (VIPT), four-way set-associative instruction cache. + * The L1 instruction memory system has the following + * key features: + * - Virtually Indexed, Physically Tagged (VIPT), + * four-way set-associative instruction cache. * - Fixed cache line length of 64 bytes. * - * The L1 data memory system has the following features: - * - ...the data cache behaves like an eight-way set associative PIPT cache (for 32KB configurations) - * and a 16-way set associative PIPT cache (for 64KB configurations). + * The L1 data memory system has the following + * features: + * - ...the data cache behaves like an eight-way set + * associative PIPT cache (for 32KB configurations) and + * a 16-way set associative PIPT cache (for 64KB + * configurations). * - Fixed cache line length of 64 bytes. * * 7.1 About the L2 memory system * The L2 memory system consists of: * - A tightly-integrated L2 cache with: - * - A configurable size of 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB. + * - A configurable size of 256KB, 512KB, 1MB, 2MB, + * 4MB, or 8MB. * - A 16-way, set-associative structure. * - A fixed line length of 64 bytes. * * The ARM Cortex A73 - Artemis Unveiled [1] - * "ARM still envisions that most vendors will choose to use configurations of 1 to - * 2MB in consumer products. The L2 cache is inclusive of the L1 cache. " + * "ARM still envisions that most vendors will choose + * to use configurations of 1 to 2MB in consumer + * products. The L2 cache is inclusive of the L1 cache. + * " * * +---------------------+---------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I + * cache | L2 cache | Reference | * +---------------------+---------+-----------+-----------+-----------+-----------+ - * | HiSilicon Kirin 960 | 4(+4) | 64K+32K | 64K+32K | ? | [2] | - * | MediaTek Helio X30 | 2(+4+4) | ? | 64K+ ? | ? | | - * | Snapdragon 636 | 4(+4) | 64K(+32K) | 64K(+32K) | 1M(+1M) | sysfs | - * | Snapdragon 660 | 4(+4) | 64K+32K | 64K+32K | 1M(+1M) | [3] | - * | Snapdragon 835 | 4(+4) | 64K+32K | 64K+32K | 2M(+1M) | sysfs | + * | HiSilicon Kirin 960 | 4(+4) | 64K+32K | + * 64K+32K | ? | [2] | | MediaTek Helio X30 + * | 2(+4+4) | ? | 64K+ ? | ? | | | + * Snapdragon 636 | 4(+4) | 64K(+32K) | 64K(+32K) + * | 1M(+1M) | sysfs | | Snapdragon 660 | 4(+4) + * | 64K+32K | 64K+32K | 1M(+1M) | [3] | | + * Snapdragon 835 | 4(+4) | 64K+32K | 64K+32K + * | 2M(+1M) | sysfs | * +---------------------+---------+-----------+-----------+-----------+-----------+ * - * [1] http://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2 - * [2] http://www.anandtech.com/show/11088/hisilicon-kirin-960-performance-and-power/3 - * [3] https://arstechnica.com/gadgets/2017/05/qualcomms-snapdragon-660-and-630-bring-more-high-end-features-to-midrange-chips/ + * [1] + * http://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2 + * [2] + * http://www.anandtech.com/show/11088/hisilicon-kirin-960-performance-and-power/3 + * [3] + * https://arstechnica.com/gadgets/2017/05/qualcomms-snapdragon-660-and-630-bring-more-high-end-features-to-midrange-chips/ */ uint32_t l1d_size = 32 * 1024; uint32_t l2_size = 512 * 1024; @@ -1017,69 +1079,73 @@ void cpuinfo_arm_decode_cache( break; case cpuinfo_arm_chipset_series_mediatek_mt: l1d_size = 64 * 1024; - l2_size = 1 * 1024 * 1024; /* TODO: verify assumption */ + l2_size = 1 * 1024 * 1024; /* TODO: verify assumption + */ break; default: switch (midr) { - case UINT32_C(0x51AF8001): /* Kryo 280 Gold */ + case UINT32_C(0x51AF8001): /* Kryo 280 + Gold */ l1d_size = 64 * 1024; l2_size = 2 * 1024 * 1024; break; - case UINT32_C(0x51AF8002): /* Kryo 260 Gold */ + case UINT32_C(0x51AF8002): /* Kryo 260 + Gold */ l1d_size = 64 * 1024; l2_size = 1 * 1024 * 1024; break; } } - *l1i = (struct cpuinfo_cache) { - .size = 64 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = l1d_size, - .associativity = (l1d_size >> 12), - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){.size = 64 * 1024, .associativity = 4, .line_size = 64}; + *l1d = (struct cpuinfo_cache){ + .size = l1d_size, .associativity = (l1d_size >> 12), .line_size = 64}; + *l2 = (struct cpuinfo_cache){ .size = l2_size, .associativity = 16, .line_size = 64, - .flags = CPUINFO_CACHE_INCLUSIVE - }; + .flags = CPUINFO_CACHE_INCLUSIVE}; break; } - case cpuinfo_uarch_cortex_a75: - { + case cpuinfo_uarch_cortex_a75: { /* * ARM Cortex-A75 Core Technical Reference Manual * A6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB. + * The L1 memory system consists of separate + * instruction and data caches. Both have a fixed size + * of 64KB. * * A6.1.1 L1 instruction-side memory system - * The L1 instruction memory system has the following key features: - * - Virtually Indexed, Physically Tagged (VIPT), four-way set-associative instruction cache. + * The L1 instruction memory system has the following + * key features: + * - Virtually Indexed, Physically Tagged (VIPT), + * four-way set-associative instruction cache. * - Fixed cache line length of 64 bytes. * * A6.1.2 L1 data-side memory system - * The L1 data memory system has the following features: - * - Physically Indexed, Physically Tagged (PIPT), 16-way set-associative L1 data cache. + * The L1 data memory system has the following + * features: + * - Physically Indexed, Physically Tagged (PIPT), + * 16-way set-associative L1 data cache. * - Fixed cache line length of 64 bytes. * - Pseudo-random cache replacement policy. * * A7.1 About the L2 memory system * The L2 memory subsystem consist of: - * - An 8-way set associative L2 cache with a configurable size of 256KB or 512KB. - * Cache lines have a fixed length of 64 bytes. + * - An 8-way set associative L2 cache with a + * configurable size of 256KB or 512KB. Cache lines have + * a fixed length of 64 bytes. * * +--------------------+-------+-----------+-----------+-----------+----------+------------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | L3 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+----------+------------+ - * | Snapdragon 845 | 4(+4) | 64K | 64K | 256K | 2M | [1], sysfs | + * | Snapdragon 845 | 4(+4) | 64K | 64K | + * 256K | 2M | [1], sysfs | * +--------------------+-------+-----------+-----------+-----------+----------+------------+ * - * [1] https://www.anandtech.com/show/12114/qualcomm-announces-snapdragon-845-soc + * [1] + * https://www.anandtech.com/show/12114/qualcomm-announces-snapdragon-845-soc */ uint32_t l3_size = 1024 * 1024; switch (chipset->series) { @@ -1092,70 +1158,66 @@ void cpuinfo_arm_decode_cache( default: break; } - *l1i = (struct cpuinfo_cache) { - .size = 64 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 64 * 1024, - .associativity = 16, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = 256 * 1024, - .associativity = 8, - .line_size = 64 - }; - *l3 = (struct cpuinfo_cache) { - .size = l3_size, - .associativity = 16, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 64 * 1024, .associativity = 4, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 64 * 1024, .associativity = 16, .line_size = 64}; + *l2 = (struct cpuinfo_cache){.size = 256 * 1024, .associativity = 8, .line_size = 64}; + *l3 = (struct cpuinfo_cache){.size = l3_size, .associativity = 16, .line_size = 64}; break; } - case cpuinfo_uarch_cortex_a76: - { + case cpuinfo_uarch_cortex_a76: { /* * ARM Cortex-A76 Core Technical Reference Manual * A6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB. + * The L1 memory system consists of separate + * instruction and data caches. Both have a fixed size + * of 64KB. * * A6.1.1 L1 instruction-side memory system - * The L1 instruction memory system has the following key features: - * - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed, - * Physically Tagged (PIPT) 4-way set-associative L1 data cache. + * The L1 instruction memory system has the following + * key features: + * - Virtually Indexed, Physically Tagged (VIPT), + * which behaves as a Physically Indexed, Physically + * Tagged (PIPT) 4-way set-associative L1 data cache. * - Fixed cache line length of 64 bytes. * * A6.1.2 L1 data-side memory system - * The L1 data memory system has the following features: - * - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed, - * Physically Tagged (PIPT) 4-way set-associative L1 data cache. + * The L1 data memory system has the following + * features: + * - Virtually Indexed, Physically Tagged (VIPT), + * which behaves as a Physically Indexed, Physically + * Tagged (PIPT) 4-way set-associative L1 data cache. * - Fixed cache line length of 64 bytes. * - Pseudo-LRU cache replacement policy. * * A7.1 About the L2 memory system * The L2 memory subsystem consist of: - * - An 8-way set associative L2 cache with a configurable size of 128KB, 256KB or 512KB. - * Cache lines have a fixed length of 64 bytes. - * - Strictly inclusive with L1 data cache. Weakly inclusive with L1 instruction cache. + * - An 8-way set associative L2 cache with a + * configurable size of 128KB, 256KB or 512KB. Cache + * lines have a fixed length of 64 bytes. + * - Strictly inclusive with L1 data cache. Weakly + * inclusive with L1 instruction cache. * - Dynamic biased replacement policy. - * - Modified Exclusive Shared Invalid (MESI) coherency. + * - Modified Exclusive Shared Invalid (MESI) + * coherency. * * +--------------------+-------+-----------+-----------+-----------+----------+------------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | L3 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+----------+------------+ - * | Kirin 980 | 4(+4) | 64K | 64K | 512K | 4M | [1], [2] | + * | Kirin 980 | 4(+4) | 64K | 64K | + * 512K | 4M | [1], [2] | * +--------------------+-------+-----------+-----------+-----------+----------+------------+ * - * [1] https://www.anandtech.com/show/13298/hisilicon-announces-the-kirin-980-first-a76-g76-on-7nm + * [1] + * https://www.anandtech.com/show/13298/hisilicon-announces-the-kirin-980-first-a76-g76-on-7nm * [2] https://en.wikichip.org/wiki/hisilicon/kirin/980 */ uint32_t l2_size = 256 * 1024; uint32_t l3_size = 1024 * 1024; switch (chipset->series) { case cpuinfo_arm_chipset_series_hisilicon_kirin: - /* Kirin 980: 512K L2 cache + 4M L3 cache */ + /* Kirin 980: 512K L2 cache + 4M L3 + * cache */ if (chipset->model == 980) { l2_size = 512 * 1024; l3_size = 4 * 1024 * 1024; @@ -1164,74 +1226,81 @@ void cpuinfo_arm_decode_cache( default: break; } - *l1i = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){ .size = 64 * 1024, .associativity = 4, .line_size = 64, }; - *l1d = (struct cpuinfo_cache) { + *l1d = (struct cpuinfo_cache){ .size = 64 * 1024, .associativity = 4, .line_size = 64, }; - *l2 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ .size = l2_size, .associativity = 8, .line_size = 64, .flags = CPUINFO_CACHE_INCLUSIVE, }; - *l3 = (struct cpuinfo_cache) { + *l3 = (struct cpuinfo_cache){ .size = l3_size, .associativity = 16, .line_size = 64, }; break; } - case cpuinfo_uarch_cortex_a77: - { + case cpuinfo_uarch_cortex_a77: { /* * ARM Cortex-A77 Core Technical Reference Manual * A6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB. + * The L1 memory system consists of separate + * instruction and data caches. Both have a fixed size + * of 64KB. * * A6.1.1 L1 instruction-side memory system - * The L1 instruction memory system has the following key features: - * - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed, - * Physically Tagged (PIPT) 4-way set-associative L1 data cache. + * The L1 instruction memory system has the following + * key features: + * - Virtually Indexed, Physically Tagged (VIPT), + * which behaves as a Physically Indexed, Physically + * Tagged (PIPT) 4-way set-associative L1 data cache. * - Fixed cache line length of 64 bytes. * * A6.1.2 L1 data-side memory system - * The L1 data memory system has the following features: - * - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed, - * Physically Tagged (PIPT) 4-way set-associative L1 data cache. + * The L1 data memory system has the following + * features: + * - Virtually Indexed, Physically Tagged (VIPT), + * which behaves as a Physically Indexed, Physically + * Tagged (PIPT) 4-way set-associative L1 data cache. * - Fixed cache line length of 64 bytes. * - Pseudo-LRU cache replacement policy. * * A7.1 About the L2 memory system * The L2 memory subsystem consist of: - * - An 8-way set associative L2 cache with a configurable size of 128KB, 256KB or 512KB. Cache lines - * have a fixed length of 64 bytes. - * - Strictly inclusive with L1 data cache. Weakly inclusive with L1 instruction cache. + * - An 8-way set associative L2 cache with a + * configurable size of 128KB, 256KB or 512KB. Cache + * lines have a fixed length of 64 bytes. + * - Strictly inclusive with L1 data cache. Weakly + * inclusive with L1 instruction cache. */ const uint32_t l2_size = 256 * 1024; const uint32_t l3_size = 1024 * 1024; - *l1i = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){ .size = 64 * 1024, .associativity = 4, .line_size = 64, }; - *l1d = (struct cpuinfo_cache) { + *l1d = (struct cpuinfo_cache){ .size = 64 * 1024, .associativity = 4, .line_size = 64, }; - *l2 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ .size = l2_size, .associativity = 8, .line_size = 64, .flags = CPUINFO_CACHE_INCLUSIVE, }; - *l3 = (struct cpuinfo_cache) { + *l3 = (struct cpuinfo_cache){ .size = l3_size, .associativity = 16, .line_size = 64, @@ -1241,48 +1310,57 @@ void cpuinfo_arm_decode_cache( case cpuinfo_uarch_neoverse_n1: case cpuinfo_uarch_neoverse_v1: case cpuinfo_uarch_neoverse_n2: - case cpuinfo_uarch_neoverse_v2: - { + case cpuinfo_uarch_neoverse_v2: { /* - * The specifications here below are taken from the - * Arm Core Technical Reference Manuals for - * - Neoverse N1: https://developer.arm.com/documentation/100616/0401/?lang=en - * - Neoverse N2: https://developer.arm.com/documentation/102099/0003/?lang=en - * - Neoverse V1: https://developer.arm.com/documentation/101427/0102/?lang=en - * - Neoverse V2: https://developer.arm.com/documentation/102375/0002/?lang=en - * - * All four Arm architectures have L1 memory system with instruction and data caches, - * both of fixed size of 64KB. The instruction side memory system is 4-way set associative - * with a cache line length of 64 bytes. The data cache is also 4-way set associative with - * a cache line length of 64 bytes. - * - * The L2 memory system differs across the four Architectures in the minimum - * length of the L2 cache. Namely: - * - Arm Neoverse N1/N2/V1 have a L2 cache of configurable size of 256KB, 512KB, or 1024KB - * - Arm Neoverse V2 has a L2 cache of configurable size of 1MB or 2MB - * For all four architectures, the L2 cache is 8-way set associative - * For all other information, please refer to the technical manuals linked above - */ + * The specifications here below are taken from the + * Arm Core Technical Reference Manuals for + * - Neoverse N1: + * https://developer.arm.com/documentation/100616/0401/?lang=en + * - Neoverse N2: + * https://developer.arm.com/documentation/102099/0003/?lang=en + * - Neoverse V1: + * https://developer.arm.com/documentation/101427/0102/?lang=en + * - Neoverse V2: + * https://developer.arm.com/documentation/102375/0002/?lang=en + * + * All four Arm architectures have L1 memory system with + * instruction and data caches, both of fixed size of + * 64KB. The instruction side memory system is 4-way set + * associative with a cache line length of 64 bytes. The + * data cache is also 4-way set associative with a cache + * line length of 64 bytes. + * + * The L2 memory system differs across the four + * Architectures in the minimum length of the L2 cache. + * Namely: + * - Arm Neoverse N1/N2/V1 have a L2 cache of + * configurable size of 256KB, 512KB, or 1024KB + * - Arm Neoverse V2 has a L2 cache of configurable + * size of 1MB or 2MB For all four architectures, the L2 + * cache is 8-way set associative For all other + * information, please refer to the technical manuals + * linked above + */ const uint32_t min_l2_size_KB = uarch == cpuinfo_uarch_neoverse_v2 ? 1024 : 256; const uint32_t min_l3_size_KB = 0; - *l1i = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){ .size = 64 * 1024, .associativity = 4, .line_size = 64, }; - *l1d = (struct cpuinfo_cache) { + *l1d = (struct cpuinfo_cache){ .size = 64 * 1024, .associativity = 4, .line_size = 64, }; - *l2 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ .size = min_l2_size_KB * 1024, .associativity = 8, .line_size = 64, .flags = CPUINFO_CACHE_INCLUSIVE, }; - *l3 = (struct cpuinfo_cache) { + *l3 = (struct cpuinfo_cache){ .size = min_l3_size_KB * 1024, .associativity = 16, .line_size = 64, @@ -1292,37 +1370,29 @@ void cpuinfo_arm_decode_cache( #if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__) case cpuinfo_uarch_scorpion: /* - * - "The CPU includes 32KB instruction and data caches as - * well as a complete memory-management unit (MMU) suitable - * for high-level operating systems. The CPU also has - * 256KB of SRAM that can be allocated in 64KB increments - * to level-two (L2) cache or tightly coupled memory (TCM)." [1] - * We interpret it as L2 cache being 4-way set-associative on single-core Scorpion. + * - "The CPU includes 32KB instruction and data caches + * as well as a complete memory-management unit (MMU) + * suitable for high-level operating systems. The CPU + * also has 256KB of SRAM that can be allocated in 64KB + * increments to level-two (L2) cache or tightly coupled + * memory (TCM)." [1] We interpret it as L2 cache being + * 4-way set-associative on single-core Scorpion. * - L1 Data Cache = 32 KB. 32 B/line. [2] - * - L2 Cache = 256 KB. 128 B/line. [2] - * - 256 KB (single-core) or 512 KB (dual-core) L2 cache [3] + * - L2 Cache = 256 KB. 128 B/line. [2] + * - 256 KB (single-core) or 512 KB (dual-core) L2 cache + * [3] * - Single or dual-core configuration [3] * - For L1 cache assume the same associativity as Krait * - * [1] https://www.qualcomm.com/media/documents/files/linley-report-on-dual-core-snapdragon.pdf + * [1] + * https://www.qualcomm.com/media/documents/files/linley-report-on-dual-core-snapdragon.pdf * [2] http://www.7-cpu.com/cpu/Snapdragon.html * [3] https://en.wikipedia.org/wiki/Scorpion_(CPU) */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 32 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 32 - }; - *l2 = (struct cpuinfo_cache) { - .size = cluster_cores * 256 * 1024, - .associativity = 4, - .line_size = 128 - }; + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 32}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 32}; + *l2 = (struct cpuinfo_cache){ + .size = cluster_cores * 256 * 1024, .associativity = 4, .line_size = 128}; break; case cpuinfo_uarch_krait: /* @@ -1330,155 +1400,141 @@ void cpuinfo_arm_decode_cache( * - L0 Instruction cache = 4 KB. [1] * - L1 Data cache = 16 KB. 64 B/line, 4-way [1] * - L1 Instruction cache = 16 KB, 4-way [1] - * - L2 Cache = 1 MB, 128 B/line, 8-way. Each core has fast access only to 512 KB of L2 cache. [1] - * - L2 = 1MB (dual core) or 2MB (quad core), 8-way set associative [2] + * - L2 Cache = 1 MB, 128 B/line, 8-way. Each core has + * fast access only to 512 KB of L2 cache. [1] + * - L2 = 1MB (dual core) or 2MB (quad core), 8-way set + * associative [2] * * [1] http://www.7-cpu.com/cpu/Krait.html - * [2] http://www.anandtech.com/show/4940/qualcomm-new-snapdragon-s4-msm8960-krait-architecture/2 + * [2] + * http://www.anandtech.com/show/4940/qualcomm-new-snapdragon-s4-msm8960-krait-architecture/2 */ - *l1i = (struct cpuinfo_cache) { - .size = 16 * 1024, - .associativity = 4, - .line_size = 64 /* assume same as L1D */ - }; - *l1d = (struct cpuinfo_cache) { - .size = 16 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = cluster_cores * 512 * 1024, - .associativity = 8, - .line_size = 128 + *l1i = (struct cpuinfo_cache){ + .size = 16 * 1024, .associativity = 4, .line_size = 64 /* assume same as L1D */ }; + *l1d = (struct cpuinfo_cache){.size = 16 * 1024, .associativity = 4, .line_size = 64}; + *l2 = (struct cpuinfo_cache){ + .size = cluster_cores * 512 * 1024, .associativity = 8, .line_size = 128}; break; #endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__) */ case cpuinfo_uarch_kryo: /* * +-----------------+-------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache | + * L2 cache | Reference | * +-----------------+-------+-----------+-----------+-----------+-----------+ - * | Snapdragon 820 | 2+2 | 24K | 32K | 1M+512K | [1, 2] | - * | Snapdragon 821 | 2+2 | ? | ? | 1M+512K | [1] | + * | Snapdragon 820 | 2+2 | 24K | 32K | + * 1M+512K | [1, 2] | | Snapdragon 821 | 2+2 | ? + * | ? | 1M+512K | [1] | * +-----------------+-------+-----------+-----------+-----------+-----------+ * - * [1] http://www.anandtech.com/show/9837/snapdragon-820-preview/2 - * [2] https://www.inforcecomputing.com/public_docs/Inforce6601/Inforce_6601_Micro-SOM_FAQs_04-2016-1.pdf + * [1] + * http://www.anandtech.com/show/9837/snapdragon-820-preview/2 + * [2] + * https://www.inforcecomputing.com/public_docs/Inforce6601/Inforce_6601_Micro-SOM_FAQs_04-2016-1.pdf */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 24 * 1024, - .associativity = 3, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 24 * 1024, .associativity = 3, .line_size = 64}; if (midr_is_kryo_silver(midr)) { /* Kryo "Silver" */ - *l2 = (struct cpuinfo_cache) { - .size = 512 * 1024, - .associativity = 8, - .line_size = 128 - }; + *l2 = (struct cpuinfo_cache){.size = 512 * 1024, .associativity = 8, .line_size = 128}; } else { /* Kryo "Gold" */ - *l2 = (struct cpuinfo_cache) { - .size = 1024 * 1024, - .associativity = 8, - .line_size = 128 - }; + *l2 = (struct cpuinfo_cache){.size = 1024 * 1024, .associativity = 8, .line_size = 128}; } break; case cpuinfo_uarch_denver: case cpuinfo_uarch_denver2: /* - * The Denver chip includes a 128KB, 4-way level 1 instruction cache, a 64KB, 4-way level 2 data cache, - * and a 2MB, 16-way level 2 cache, all of which can service both cores. [1] + * The Denver chip includes a 128KB, 4-way level 1 + * instruction cache, a 64KB, 4-way level 2 data cache, + * and a 2MB, 16-way level 2 cache, all of which can + * service both cores. [1] * * All the caches have 64-byte lines. [2] * - * [1] http://www.pcworld.com/article/2463900/nvidia-reveals-pc-like-performance-for-denver-tegra-k1.html - * [2] http://linleygroup.com/newsletters/newsletter_detail.php?num=5205&year=2014 + * [1] + * http://www.pcworld.com/article/2463900/nvidia-reveals-pc-like-performance-for-denver-tegra-k1.html + * [2] + * http://linleygroup.com/newsletters/newsletter_detail.php?num=5205&year=2014 */ - *l1i = (struct cpuinfo_cache) { - .size = 128 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 64 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = 2 * 1024 * 1024, - .associativity = 16, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 128 * 1024, .associativity = 4, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 64 * 1024, .associativity = 4, .line_size = 64}; + *l2 = (struct cpuinfo_cache){.size = 2 * 1024 * 1024, .associativity = 16, .line_size = 64}; break; case cpuinfo_uarch_exynos_m1: case cpuinfo_uarch_exynos_m2: /* - * - "Moving past branch prediction we can see some elements of how the cache is set up for the L1 I$, - * namely 64 KB split into four sets with 128-byte line sizes for 128 cache lines per set" [1] - * - "For loads and stores, a 32 KB, 8-way set associative cache with 64 byte line size is used" [1] - * - "The L2 cache here is 2MB shared across all cores split into 16 sets. This memory is also split - * into 4 banks and has a 22 cycle latency" [1] + * - "Moving past branch prediction we can see some + * elements of how the cache is set up for the L1 I$, + * namely 64 KB split into four sets with 128-byte line + * sizes for 128 cache lines per set" [1] + * - "For loads and stores, a 32 KB, 8-way set + * associative cache with 64 byte line size is used" [1] + * - "The L2 cache here is 2MB shared across all cores + * split into 16 sets. This memory is also split into 4 + * banks and has a 22 cycle latency" [1] * * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Exynos 8 Octa 8890 | 4(+4) | 64K | 32K | 2M | [1] | - * | Exynos 8 Octa 8895 | 4(+4) | 64K | 32K | 2M | [2] | + * | Exynos 8 Octa 8890 | 4(+4) | 64K | 32K | + * 2M | [1] | | Exynos 8 Octa 8895 | 4(+4) | 64K + * | 32K | 2M | [2] | * +--------------------+-------+-----------+-----------+-----------+-----------+ * - * [1] http://www.anandtech.com/show/10590/hot-chips-2016-exynos-m1-architecture-disclosed - * [2] https://www.extremetech.com/mobile/244949-samsungs-exynos-8895-features-custom-cpu-cores-first-10nm-chip-market + * [1] + * http://www.anandtech.com/show/10590/hot-chips-2016-exynos-m1-architecture-disclosed + * [2] + * https://www.extremetech.com/mobile/244949-samsungs-exynos-8895-features-custom-cpu-cores-first-10nm-chip-market */ - *l1i = (struct cpuinfo_cache) { - .size = 64 * 1024, - .associativity = 4, - .line_size = 128 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 8, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = 2 * 1024 * 1024, - .associativity = 16, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 64 * 1024, .associativity = 4, .line_size = 128}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 8, .line_size = 64}; + *l2 = (struct cpuinfo_cache){.size = 2 * 1024 * 1024, .associativity = 16, .line_size = 64}; break; case cpuinfo_uarch_exynos_m3: /* * +--------------------+-------+-----------+-----------+-----------+----------+------------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | L3 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+----------+------------+ - * | Exynos 9810 | 4(+4) | 64K | ? | 512K | 4M | [1] | + * | Exynos 9810 | 4(+4) | 64K | ? | + * 512K | 4M | [1] | * +--------------------+-------+-----------+-----------+-----------+----------+------------+ * - * [1] https://www.anandtech.com/show/12478/exynos-9810-handson-awkward-first-results + * [1] + * https://www.anandtech.com/show/12478/exynos-9810-handson-awkward-first-results */ - *l1i = (struct cpuinfo_cache) { - .size = 64 * 1024 /* assume same as in Exynos M1/M2 cores */, - .associativity = 4 /* assume same as in Exynos M1/M2 cores */, - .line_size = 128 /* assume same as in Exynos M1/M2 cores */ + *l1i = (struct cpuinfo_cache){ + .size = 64 * 1024 /* assume same as in Exynos + M1/M2 cores */ + , + .associativity = 4 /* assume same as in Exynos + M1/M2 cores */ + , + .line_size = 128 /* assume same as in Exynos + M1/M2 cores */ }; - *l1d = (struct cpuinfo_cache) { + *l1d = (struct cpuinfo_cache){ .size = 64 * 1024, - .associativity = 8 /* assume same as in Exynos M1/M2 cores */, - .line_size = 64 /* assume same as in Exynos M1/M2 cores */, + .associativity = 8 /* assume same as in Exynos + M1/M2 cores */ + , + .line_size = 64 /* assume same as in Exynos + M1/M2 cores */ + , }; - *l2 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ .size = 512 * 1024, - .associativity = 16 /* assume same as in Exynos M1/M2 cores */, - .line_size = 64 /* assume same as in Exynos M1/M2 cores */, + .associativity = 16 /* assume same as in Exynos + M1/M2 cores */ + , + .line_size = 64 /* assume same as in Exynos + M1/M2 cores */ + , }; - *l3 = (struct cpuinfo_cache) { + *l3 = (struct cpuinfo_cache){ .size = 4 * 1024 * 1024, .associativity = 16 /* assume DynamIQ cache */, .line_size = 64 /* assume DynamIQ cache */, @@ -1487,21 +1543,19 @@ void cpuinfo_arm_decode_cache( #if CPUINFO_ARCH_ARM64 && !defined(__ANDROID__) case cpuinfo_uarch_thunderx: /* - * "78K-Icache and 32K-D cache per core, 16 MB shared L2 cache" [1] + * "78K-Icache and 32K-D cache per core, 16 MB shared L2 + * cache" [1] * - * [1] https://www.cavium.com/pdfFiles/ThunderX_CP_PB_Rev1.pdf + * [1] + * https://www.cavium.com/pdfFiles/ThunderX_CP_PB_Rev1.pdf */ - *l1i = (struct cpuinfo_cache) { - .size = 78 * 1024, - .associativity = 4 /* assumption */, - .line_size = 64 /* assumption */ + *l1i = (struct cpuinfo_cache){ + .size = 78 * 1024, .associativity = 4 /* assumption */, .line_size = 64 /* assumption */ }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4 /* assumption */, - .line_size = 64 /* assumption */ + *l1d = (struct cpuinfo_cache){ + .size = 32 * 1024, .associativity = 4 /* assumption */, .line_size = 64 /* assumption */ }; - *l2 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ .size = 16 * 1024 * 1024, .associativity = 8 /* assumption */, .line_size = 64 /* assumption */ @@ -1509,40 +1563,50 @@ void cpuinfo_arm_decode_cache( break; case cpuinfo_uarch_taishan_v110: /* - * It features private 64 KiB L1 instruction and data caches as well as 512 KiB of private L2. [1] + * It features private 64 KiB L1 instruction and data + * caches as well as 512 KiB of private L2. [1] * * +------------------+-------+-----------+-----------+-----------+----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache | + * L2 cache | L3 cache | Reference | * +------------------+-------+-----------+-----------+-----------+----------+-----------+ - * | Kunpeng 920-3226 | 32 | 64K | 64K | 512K | 32M | [2] | + * | Kunpeng 920-3226 | 32 | 64K | 64K | + * 512K | 32M | [2] | * +------------------+-------+-----------+-----------+-----------+----------+-----------+ - * | Kunpeng 920-4826 | 48 | 64K | 64K | 512K | 48M | [3] | + * | Kunpeng 920-4826 | 48 | 64K | 64K | + * 512K | 48M | [3] | * +------------------+-------+-----------+-----------+-----------+----------+-----------+ - * | Kunpeng 920-6426 | 64 | 64K | 64K | 512K | 64M | [4] | + * | Kunpeng 920-6426 | 64 | 64K | 64K | + * 512K | 64M | [4] | * +------------------+-------+-----------+-----------+-----------+----------+-----------+ * - * [1] https://en.wikichip.org/wiki/hisilicon/microarchitectures/taishan_v110 - * [2] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-3226 - * [3] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-4826 - * [4] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-6426 + * [1] + * https://en.wikichip.org/wiki/hisilicon/microarchitectures/taishan_v110 + * [2] + * https://en.wikichip.org/wiki/hisilicon/kunpeng/920-3226 + * [3] + * https://en.wikichip.org/wiki/hisilicon/kunpeng/920-4826 + * [4] + * https://en.wikichip.org/wiki/hisilicon/kunpeng/920-6426 */ - *l1i = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){ .size = 64 * 1024, .associativity = 4 /* assumption */, .line_size = 128 /* assumption */, }; - *l1d = (struct cpuinfo_cache) { + *l1d = (struct cpuinfo_cache){ .size = 64 * 1024, .associativity = 4 /* assumption */, .line_size = 128 /* assumption */, }; - *l2 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ .size = 512 * 1024, .associativity = 8 /* assumption */, .line_size = 128 /* assumption */, - .flags = CPUINFO_CACHE_INCLUSIVE /* assumption */, + .flags = CPUINFO_CACHE_INCLUSIVE /* assumption */ + , }; - *l3 = (struct cpuinfo_cache) { + *l3 = (struct cpuinfo_cache){ .size = cluster_cores * 1024 * 1024, .associativity = 16 /* assumption */, .line_size = 128 /* assumption */, @@ -1555,38 +1619,18 @@ void cpuinfo_arm_decode_cache( cpuinfo_log_warning("target uarch not recognized; using generic cache parameters"); /* Follow OpenBLAS */ if (arch_version >= 8) { - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = cluster_cores * 256 * 1024, - .associativity = 8, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64}; + *l2 = (struct cpuinfo_cache){ + .size = cluster_cores * 256 * 1024, .associativity = 8, .line_size = 64}; } else { - *l1i = (struct cpuinfo_cache) { - .size = 16 * 1024, - .associativity = 4, - .line_size = 32 - }; - *l1d = (struct cpuinfo_cache) { - .size = 16 * 1024, - .associativity = 4, - .line_size = 32 - }; + *l1i = (struct cpuinfo_cache){.size = 16 * 1024, .associativity = 4, .line_size = 32}; + *l1d = (struct cpuinfo_cache){.size = 16 * 1024, .associativity = 4, .line_size = 32}; if (arch_version >= 7) { - *l2 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ .size = cluster_cores * 128 * 1024, .associativity = 8, - .line_size = 32 - }; + .line_size = 32}; } } break; @@ -1607,8 +1651,9 @@ void cpuinfo_arm_decode_cache( uint32_t cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor* processor) { /* - * There is no precise way to detect cache size on ARM/ARM64, and cache size reported by cpuinfo - * may underestimate the actual cache size. Thus, we use microarchitecture-specific maximum. + * There is no precise way to detect cache size on ARM/ARM64, and cache + * size reported by cpuinfo may underestimate the actual cache size. + * Thus, we use microarchitecture-specific maximum. */ switch (processor->core->uarch) { case cpuinfo_uarch_xscale: @@ -1630,7 +1675,8 @@ uint32_t cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor* proc * 7.1. About the L2 Memory system * The L2 memory system consists of an: * - Optional tightly-coupled L2 cache that includes: - * - Configurable L2 cache size of 128KB, 256KB, 512KB, and 1MB. + * - Configurable L2 cache size of 128KB, 256KB, + * 512KB, and 1MB. */ return 1024 * 1024; case cpuinfo_uarch_cortex_a8: @@ -1638,7 +1684,8 @@ uint32_t cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor* proc * Cortex-A8 Technical Reference Manual: * 8.1. About the L2 memory system * The key features of the L2 memory system include: - * - configurable cache size of 0KB, 128KB, 256KB, 512KB, and 1MB + * - configurable cache size of 0KB, 128KB, 256KB, + * 512KB, and 1MB */ return 1024 * 1024; case cpuinfo_uarch_cortex_a9: @@ -1647,19 +1694,21 @@ uint32_t cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor* proc case cpuinfo_uarch_cortex_a12: case cpuinfo_uarch_cortex_a17: /* - * ARM Cortex-A17 MPCore Processor Technical Reference Manual: - * 7.1. About the L2 Memory system - * The key features of the L2 memory system include: + * ARM Cortex-A17 MPCore Processor Technical Reference + * Manual: 7.1. About the L2 Memory system The key + * features of the L2 memory system include: * - An integrated L2 cache: - * - The cache size is implemented as either 256KB, 512KB, 1MB, 2MB, 4MB or 8MB. + * - The cache size is implemented as either 256KB, + * 512KB, 1MB, 2MB, 4MB or 8MB. */ return 8 * 1024 * 1024; case cpuinfo_uarch_cortex_a15: /* - * ARM Cortex-A15 MPCore Processor Technical Reference Manual: - * 7.1. About the L2 memory system - * The features of the L2 memory system include: - * - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB. + * ARM Cortex-A15 MPCore Processor Technical Reference + * Manual: 7.1. About the L2 memory system The features + * of the L2 memory system include: + * - Configurable L2 cache size of 512KB, 1MB, 2MB + * and 4MB. */ return 4 * 1024 * 1024; case cpuinfo_uarch_cortex_a35: @@ -1668,41 +1717,46 @@ uint32_t cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor* proc * 7.1 About the L2 memory system * L2 cache * - Further features of the L2 cache are: - * - Configurable size of 128KB, 256KB, 512KB, and 1MB. + * - Configurable size of 128KB, 256KB, 512KB, and + * 1MB. */ return 1024 * 1024; case cpuinfo_uarch_cortex_a53: /* - * ARM Cortex-A53 MPCore Processor Technical Reference Manual: - * 7.1. About the L2 memory system - * The L2 memory system consists of an: + * ARM Cortex-A53 MPCore Processor Technical Reference + * Manual: 7.1. About the L2 memory system The L2 memory + * system consists of an: * - Optional tightly-coupled L2 cache that includes: - * - Configurable L2 cache size of 128KB, 256KB, 512KB, 1MB and 2MB. + * - Configurable L2 cache size of 128KB, 256KB, + * 512KB, 1MB and 2MB. */ return 2 * 1024 * 1024; case cpuinfo_uarch_cortex_a57: /* - * ARM Cortex-A57 MPCore Processor Technical Reference Manual: - * 7.1 About the L2 memory system - * The features of the L2 memory system include: - * - Configurable L2 cache size of 512KB, 1MB, and 2MB. + * ARM Cortex-A57 MPCore Processor Technical Reference + * Manual: 7.1 About the L2 memory system The features + * of the L2 memory system include: + * - Configurable L2 cache size of 512KB, 1MB, and + * 2MB. */ return 2 * 1024 * 1024; case cpuinfo_uarch_cortex_a72: /* - * ARM Cortex-A72 MPCore Processor Technical Reference Manual: - * 7.1 About the L2 memory system - * The features of the L2 memory system include: - * - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB. + * ARM Cortex-A72 MPCore Processor Technical Reference + * Manual: 7.1 About the L2 memory system The features + * of the L2 memory system include: + * - Configurable L2 cache size of 512KB, 1MB, 2MB + * and 4MB. */ return 4 * 1024 * 1024; case cpuinfo_uarch_cortex_a73: /* - * ARM Cortex‑A73 MPCore Processor Technical Reference Manual - * 7.1 About the L2 memory system - * The L2 memory system consists of: + * ARM Cortex‑A73 MPCore Processor Technical Reference + * Manual 7.1 About the L2 memory system The L2 memory + * system consists of: * - A tightly-integrated L2 cache with: - * - A configurable size of 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB. + * - A configurable size of 256KB, 512KB, 1MB, + * 2MB, 4MB, or 8MB. */ return 8 * 1024 * 1024; case cpuinfo_uarch_cortex_a55: diff --git a/3rdparty/cpuinfo/src/arm/linux/aarch32-isa.c b/3rdparty/cpuinfo/src/arm/linux/aarch32-isa.c index 65c7826fce..bd5020c7c2 100644 --- a/3rdparty/cpuinfo/src/arm/linux/aarch32-isa.c +++ b/3rdparty/cpuinfo/src/arm/linux/aarch32-isa.c @@ -1,29 +1,27 @@ #include #if CPUINFO_MOCK - #include +#include #endif #include #include #include #include - #if CPUINFO_MOCK - uint32_t cpuinfo_arm_fpsid = 0; - uint32_t cpuinfo_arm_mvfr0 = 0; - uint32_t cpuinfo_arm_wcid = 0; +uint32_t cpuinfo_arm_fpsid = 0; +uint32_t cpuinfo_arm_mvfr0 = 0; +uint32_t cpuinfo_arm_wcid = 0; - void cpuinfo_set_fpsid(uint32_t fpsid) { - cpuinfo_arm_fpsid = fpsid; - } +void cpuinfo_set_fpsid(uint32_t fpsid) { + cpuinfo_arm_fpsid = fpsid; +} - void cpuinfo_set_wcid(uint32_t wcid) { - cpuinfo_arm_wcid = wcid; - } +void cpuinfo_set_wcid(uint32_t wcid) { + cpuinfo_arm_wcid = wcid; +} #endif - void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( uint32_t features, uint32_t features2, @@ -31,27 +29,27 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( uint32_t architecture_version, uint32_t architecture_flags, const struct cpuinfo_arm_chipset chipset[restrict static 1], - struct cpuinfo_arm_isa isa[restrict static 1]) -{ + struct cpuinfo_arm_isa isa[restrict static 1]) { if (architecture_version < 8) { - const uint32_t armv8_features2_mask = CPUINFO_ARM_LINUX_FEATURE2_AES | CPUINFO_ARM_LINUX_FEATURE2_PMULL | - CPUINFO_ARM_LINUX_FEATURE2_SHA1 | CPUINFO_ARM_LINUX_FEATURE2_SHA2 | CPUINFO_ARM_LINUX_FEATURE2_CRC32; + const uint32_t armv8_features2_mask = CPUINFO_ARM_LINUX_FEATURE2_AES | + CPUINFO_ARM_LINUX_FEATURE2_PMULL | CPUINFO_ARM_LINUX_FEATURE2_SHA1 | + CPUINFO_ARM_LINUX_FEATURE2_SHA2 | CPUINFO_ARM_LINUX_FEATURE2_CRC32; if (features2 & armv8_features2_mask) { architecture_version = 8; } } if (architecture_version >= 8) { /* - * ARMv7 code running on ARMv8: IDIV, VFP, NEON are always supported, - * but may be not reported in /proc/cpuinfo features. + * ARMv7 code running on ARMv8: IDIV, VFP, NEON are always + * supported, but may be not reported in /proc/cpuinfo features. */ - isa->armv5e = true; - isa->armv6 = true; - isa->armv6k = true; - isa->armv7 = true; + isa->armv5e = true; + isa->armv6 = true; + isa->armv6k = true; + isa->armv7 = true; isa->armv7mp = true; - isa->armv8 = true; - isa->thumb = true; + isa->armv8 = true; + isa->thumb = true; isa->thumb2 = true; isa->idiv = true; isa->vfpv3 = true; @@ -61,8 +59,10 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( isa->neon = true; /* - * NEON FP16 compute extension and VQRDMLAH/VQRDMLSH instructions are not indicated in /proc/cpuinfo. - * Use a MIDR-based heuristic to whitelist processors known to support it: + * NEON FP16 compute extension and VQRDMLAH/VQRDMLSH + * instructions are not indicated in /proc/cpuinfo. Use a + * MIDR-based heuristic to whitelist processors known to support + * it: * - Processors with Cortex-A55 cores * - Processors with Cortex-A75 cores * - Processors with Cortex-A76 cores @@ -82,8 +82,10 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( * - Neoverse V2 cores */ if (chipset->series == cpuinfo_arm_chipset_series_samsung_exynos && chipset->model == 9810) { - /* Only little cores of Exynos 9810 support FP16 & RDM */ - cpuinfo_log_warning("FP16 arithmetics and RDM disabled: only little cores in Exynos 9810 support these extensions"); + /* Only little cores of Exynos 9810 support FP16 & RDM + */ + cpuinfo_log_warning( + "FP16 arithmetics and RDM disabled: only little cores in Exynos 9810 support these extensions"); } else { switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { case UINT32_C(0x4100D050): /* Cortex-A55 */ @@ -102,11 +104,16 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( case UINT32_C(0x4100D4D0): /* Cortex-A715 */ case UINT32_C(0x4100D4E0): /* Cortex-X3 */ case UINT32_C(0x4100D4F0): /* Neoverse V2 */ - case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */ - case UINT32_C(0x51008020): /* Kryo 385 Gold (Cortex-A75) */ - case UINT32_C(0x51008030): /* Kryo 385 Silver (Cortex-A55) */ - case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */ - case UINT32_C(0x51008050): /* Kryo 485 Silver (Cortex-A55) */ + case UINT32_C(0x4800D400): /* Cortex-A76 + (HiSilicon) */ + case UINT32_C(0x51008020): /* Kryo 385 Gold + (Cortex-A75) */ + case UINT32_C(0x51008030): /* Kryo 385 Silver + (Cortex-A55) */ + case UINT32_C(0x51008040): /* Kryo 485 Gold + (Cortex-A76) */ + case UINT32_C(0x51008050): /* Kryo 485 Silver + (Cortex-A55) */ case UINT32_C(0x53000030): /* Exynos M4 */ case UINT32_C(0x53000040): /* Exynos M5 */ isa->fp16arith = true; @@ -117,7 +124,8 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( /* * NEON VDOT instructions are not indicated in /proc/cpuinfo. - * Use a MIDR-based heuristic to whitelist processors known to support it: + * Use a MIDR-based heuristic to whitelist processors known to + * support it: * - Processors with Cortex-A76 cores * - Processors with Cortex-A77 cores * - Processors with Cortex-A78 cores @@ -135,7 +143,8 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( * - Neoverse V2 cores */ if (chipset->series == cpuinfo_arm_chipset_series_spreadtrum_sc && chipset->model == 9863) { - cpuinfo_log_warning("VDOT instructions disabled: cause occasional SIGILL on Spreadtrum SC9863A"); + cpuinfo_log_warning( + "VDOT instructions disabled: cause occasional SIGILL on Spreadtrum SC9863A"); } else if (chipset->series == cpuinfo_arm_chipset_series_unisoc_t && chipset->model == 310) { cpuinfo_log_warning("VDOT instructions disabled: cause occasional SIGILL on Unisoc T310"); } else { @@ -154,41 +163,52 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( case UINT32_C(0x4100D4D0): /* Cortex-A715 */ case UINT32_C(0x4100D4E0): /* Cortex-X3 */ case UINT32_C(0x4100D4F0): /* Neoverse V2 */ - case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */ - case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */ - case UINT32_C(0x51008050): /* Kryo 485 Silver (Cortex-A55) */ + case UINT32_C(0x4800D400): /* Cortex-A76 + (HiSilicon) */ + case UINT32_C(0x51008040): /* Kryo 485 Gold + (Cortex-A76) */ + case UINT32_C(0x51008050): /* Kryo 485 Silver + (Cortex-A55) */ case UINT32_C(0x53000030): /* Exynos M4 */ case UINT32_C(0x53000040): /* Exynos M5 */ isa->dot = true; break; - case UINT32_C(0x4100D050): /* Cortex A55: revision 1 or later only */ + case UINT32_C(0x4100D050): /* Cortex A55: revision 1 + or later only */ isa->dot = !!(midr_get_variant(midr) >= 1); break; - case UINT32_C(0x4100D0A0): /* Cortex A75: revision 2 or later only */ + case UINT32_C(0x4100D0A0): /* Cortex A75: revision 2 + or later only */ isa->dot = !!(midr_get_variant(midr) >= 2); break; } } } else { - /* ARMv7 or lower: use feature flags to detect optional features */ + /* ARMv7 or lower: use feature flags to detect optional features + */ /* - * ARM11 (ARM 1136/1156/1176/11 MPCore) processors can report v7 architecture - * even though they support only ARMv6 instruction set. + * ARM11 (ARM 1136/1156/1176/11 MPCore) processors can report v7 + * architecture even though they support only ARMv6 instruction + * set. */ if (architecture_version == 7 && midr_is_arm11(midr)) { - cpuinfo_log_warning("kernel-reported architecture ARMv7 ignored due to mismatch with processor microarchitecture (ARM11)"); + cpuinfo_log_warning( + "kernel-reported architecture ARMv7 ignored due to mismatch with processor microarchitecture (ARM11)"); architecture_version = 6; } if (architecture_version < 7) { - const uint32_t armv7_features_mask = CPUINFO_ARM_LINUX_FEATURE_VFPV3 | CPUINFO_ARM_LINUX_FEATURE_VFPV3D16 | CPUINFO_ARM_LINUX_FEATURE_VFPD32 | - CPUINFO_ARM_LINUX_FEATURE_VFPV4 | CPUINFO_ARM_LINUX_FEATURE_NEON | CPUINFO_ARM_LINUX_FEATURE_IDIVT | CPUINFO_ARM_LINUX_FEATURE_IDIVA; + const uint32_t armv7_features_mask = CPUINFO_ARM_LINUX_FEATURE_VFPV3 | + CPUINFO_ARM_LINUX_FEATURE_VFPV3D16 | CPUINFO_ARM_LINUX_FEATURE_VFPD32 | + CPUINFO_ARM_LINUX_FEATURE_VFPV4 | CPUINFO_ARM_LINUX_FEATURE_NEON | + CPUINFO_ARM_LINUX_FEATURE_IDIVT | CPUINFO_ARM_LINUX_FEATURE_IDIVA; if (features & armv7_features_mask) { architecture_version = 7; } } - if ((architecture_version >= 6) || (features & CPUINFO_ARM_LINUX_FEATURE_EDSP) || (architecture_flags & CPUINFO_ARM_LINUX_ARCH_E)) { + if ((architecture_version >= 6) || (features & CPUINFO_ARM_LINUX_FEATURE_EDSP) || + (architecture_flags & CPUINFO_ARM_LINUX_ARCH_E)) { isa->armv5e = true; } if (architecture_version >= 6) { @@ -199,13 +219,16 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( isa->armv7 = true; /* - * ARMv7 MP extension (PLDW instruction) is not indicated in /proc/cpuinfo. - * Use heuristic list of supporting processors: - * - Processors supporting UDIV/SDIV instructions ("idiva" + "idivt" features in /proc/cpuinfo) + * ARMv7 MP extension (PLDW instruction) is not + * indicated in /proc/cpuinfo. Use heuristic list of + * supporting processors: + * - Processors supporting UDIV/SDIV instructions + * ("idiva" + "idivt" features in /proc/cpuinfo) * - Cortex-A5 * - Cortex-A9 * - Dual-Core Scorpion - * - Krait (supports UDIV/SDIV, but kernels may not report it in /proc/cpuinfo) + * - Krait (supports UDIV/SDIV, but kernels may not + * report it in /proc/cpuinfo) * * TODO: check single-core Qualcomm Scorpion. */ @@ -218,31 +241,35 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( isa->armv7mp = true; break; default: - /* In practice IDIV instruction implies ARMv7+MP ISA */ - isa->armv7mp = (features & CPUINFO_ARM_LINUX_FEATURE_IDIV) == CPUINFO_ARM_LINUX_FEATURE_IDIV; + /* In practice IDIV instruction implies + * ARMv7+MP ISA */ + isa->armv7mp = (features & CPUINFO_ARM_LINUX_FEATURE_IDIV) == + CPUINFO_ARM_LINUX_FEATURE_IDIV; break; } } if (features & CPUINFO_ARM_LINUX_FEATURE_IWMMXT) { - #if !defined(__ARM_ARCH_8A__) && !(defined(__ARM_ARCH) && (__ARM_ARCH >= 8)) - const uint32_t wcid = read_wcid(); - cpuinfo_log_debug("WCID = 0x%08"PRIx32, wcid); - const uint32_t coprocessor_type = (wcid >> 8) & UINT32_C(0xFF); - if (coprocessor_type >= 0x10) { - isa->wmmx = true; - if (coprocessor_type >= 0x20) { - isa->wmmx2 = true; - } - } else { - cpuinfo_log_warning("WMMX ISA disabled: OS reported iwmmxt feature, " - "but WCID coprocessor type 0x%"PRIx32" indicates no WMMX support", - coprocessor_type); +#if !defined(__ARM_ARCH_8A__) && !(defined(__ARM_ARCH) && (__ARM_ARCH >= 8)) + const uint32_t wcid = read_wcid(); + cpuinfo_log_debug("WCID = 0x%08" PRIx32, wcid); + const uint32_t coprocessor_type = (wcid >> 8) & UINT32_C(0xFF); + if (coprocessor_type >= 0x10) { + isa->wmmx = true; + if (coprocessor_type >= 0x20) { + isa->wmmx2 = true; } - #else - cpuinfo_log_warning("WMMX ISA disabled: OS reported iwmmxt feature, " - "but there is no iWMMXt coprocessor"); - #endif + } else { + cpuinfo_log_warning( + "WMMX ISA disabled: OS reported iwmmxt feature, " + "but WCID coprocessor type 0x%" PRIx32 " indicates no WMMX support", + coprocessor_type); + } +#else + cpuinfo_log_warning( + "WMMX ISA disabled: OS reported iwmmxt feature, " + "but there is no iWMMXt coprocessor"); +#endif } if ((features & CPUINFO_ARM_LINUX_FEATURE_THUMB) || (architecture_flags & CPUINFO_ARM_LINUX_ARCH_T)) { @@ -263,35 +290,39 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( isa->jazelle = true; } - /* Qualcomm Krait may have buggy kernel configuration that doesn't report IDIV */ - if ((features & CPUINFO_ARM_LINUX_FEATURE_IDIV) == CPUINFO_ARM_LINUX_FEATURE_IDIV || midr_is_krait(midr)) { + /* Qualcomm Krait may have buggy kernel configuration that + * doesn't report IDIV */ + if ((features & CPUINFO_ARM_LINUX_FEATURE_IDIV) == CPUINFO_ARM_LINUX_FEATURE_IDIV || + midr_is_krait(midr)) { isa->idiv = true; } - const uint32_t vfp_mask = \ - CPUINFO_ARM_LINUX_FEATURE_VFP | CPUINFO_ARM_LINUX_FEATURE_VFPV3 | CPUINFO_ARM_LINUX_FEATURE_VFPV3D16 | \ - CPUINFO_ARM_LINUX_FEATURE_VFPD32 | CPUINFO_ARM_LINUX_FEATURE_VFPV4 | CPUINFO_ARM_LINUX_FEATURE_NEON; + const uint32_t vfp_mask = CPUINFO_ARM_LINUX_FEATURE_VFP | CPUINFO_ARM_LINUX_FEATURE_VFPV3 | + CPUINFO_ARM_LINUX_FEATURE_VFPV3D16 | CPUINFO_ARM_LINUX_FEATURE_VFPD32 | + CPUINFO_ARM_LINUX_FEATURE_VFPV4 | CPUINFO_ARM_LINUX_FEATURE_NEON; if (features & vfp_mask) { - const uint32_t vfpv3_mask = CPUINFO_ARM_LINUX_FEATURE_VFPV3 | CPUINFO_ARM_LINUX_FEATURE_VFPV3D16 | \ - CPUINFO_ARM_LINUX_FEATURE_VFPD32 | CPUINFO_ARM_LINUX_FEATURE_VFPV4 | CPUINFO_ARM_LINUX_FEATURE_NEON; + const uint32_t vfpv3_mask = CPUINFO_ARM_LINUX_FEATURE_VFPV3 | + CPUINFO_ARM_LINUX_FEATURE_VFPV3D16 | CPUINFO_ARM_LINUX_FEATURE_VFPD32 | + CPUINFO_ARM_LINUX_FEATURE_VFPV4 | CPUINFO_ARM_LINUX_FEATURE_NEON; if ((architecture_version >= 7) || (features & vfpv3_mask)) { isa->vfpv3 = true; - const uint32_t d32_mask = CPUINFO_ARM_LINUX_FEATURE_VFPD32 | CPUINFO_ARM_LINUX_FEATURE_NEON; + const uint32_t d32_mask = + CPUINFO_ARM_LINUX_FEATURE_VFPD32 | CPUINFO_ARM_LINUX_FEATURE_NEON; if (features & d32_mask) { isa->d32 = true; } } else { - #if defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH) && (__ARM_ARCH >= 7) - isa->vfpv3 = true; - #else - const uint32_t fpsid = read_fpsid(); - cpuinfo_log_debug("FPSID = 0x%08"PRIx32, fpsid); - const uint32_t subarchitecture = (fpsid >> 16) & UINT32_C(0x7F); - if (subarchitecture >= 0x01) { - isa->vfpv2 = true; - } - #endif +#if defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH) && (__ARM_ARCH >= 7) + isa->vfpv3 = true; +#else + const uint32_t fpsid = read_fpsid(); + cpuinfo_log_debug("FPSID = 0x%08" PRIx32, fpsid); + const uint32_t subarchitecture = (fpsid >> 16) & UINT32_C(0x7F); + if (subarchitecture >= 0x01) { + isa->vfpv2 = true; + } +#endif } } if (features & CPUINFO_ARM_LINUX_FEATURE_NEON) { @@ -300,8 +331,9 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( /* * There is no separate feature flag for FP16 support. - * VFPv4 implies VFPv3-FP16 support (and in practice, NEON-HP as well). - * Additionally, ARM Cortex-A9 and Qualcomm Scorpion support FP16. + * VFPv4 implies VFPv3-FP16 support (and in practice, NEON-HP as + * well). Additionally, ARM Cortex-A9 and Qualcomm Scorpion + * support FP16. */ if ((features & CPUINFO_ARM_LINUX_FEATURE_VFPV4) || midr_is_cortex_a9(midr) || midr_is_scorpion(midr)) { isa->fp16 = true; diff --git a/3rdparty/cpuinfo/src/arm/linux/aarch64-isa.c b/3rdparty/cpuinfo/src/arm/linux/aarch64-isa.c index 5dd4c4d07a..db5349ecf8 100644 --- a/3rdparty/cpuinfo/src/arm/linux/aarch64-isa.c +++ b/3rdparty/cpuinfo/src/arm/linux/aarch64-isa.c @@ -3,14 +3,12 @@ #include #include - void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( uint32_t features, uint32_t features2, uint32_t midr, const struct cpuinfo_arm_chipset chipset[restrict static 1], - struct cpuinfo_arm_isa isa[restrict static 1]) -{ + struct cpuinfo_arm_isa isa[restrict static 1]) { if (features & CPUINFO_ARM_LINUX_FEATURE_AES) { isa->aes = true; } @@ -31,8 +29,10 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( } /* - * Some phones ship with an old kernel configuration that doesn't report NEON FP16 compute extension and SQRDMLAH/SQRDMLSH/UQRDMLAH/UQRDMLSH instructions. - * Use a MIDR-based heuristic to whitelist processors known to support it: + * Some phones ship with an old kernel configuration that doesn't report + * NEON FP16 compute extension and SQRDMLAH/SQRDMLSH/UQRDMLAH/UQRDMLSH + * instructions. Use a MIDR-based heuristic to whitelist processors + * known to support it: * - Processors with Cortex-A55 cores * - Processors with Cortex-A65 cores * - Processors with Cortex-A75 cores @@ -46,8 +46,10 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( * - Neoverse V2 cores */ if (chipset->series == cpuinfo_arm_chipset_series_samsung_exynos && chipset->model == 9810) { - /* Exynos 9810 reports that it supports FP16 compute, but in fact only little cores do */ - cpuinfo_log_warning("FP16 arithmetics and RDM disabled: only little cores in Exynos 9810 support these extensions"); + /* Exynos 9810 reports that it supports FP16 compute, but in + * fact only little cores do */ + cpuinfo_log_warning( + "FP16 arithmetics and RDM disabled: only little cores in Exynos 9810 support these extensions"); } else { const uint32_t fp16arith_mask = CPUINFO_ARM_LINUX_FEATURE_FPHP | CPUINFO_ARM_LINUX_FEATURE_ASIMDHP; switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { @@ -75,9 +77,11 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( if ((features & fp16arith_mask) == fp16arith_mask) { isa->fp16arith = true; } else if (features & CPUINFO_ARM_LINUX_FEATURE_FPHP) { - cpuinfo_log_warning("FP16 arithmetics disabled: detected support only for scalar operations"); + cpuinfo_log_warning( + "FP16 arithmetics disabled: detected support only for scalar operations"); } else if (features & CPUINFO_ARM_LINUX_FEATURE_ASIMDHP) { - cpuinfo_log_warning("FP16 arithmetics disabled: detected support only for SIMD operations"); + cpuinfo_log_warning( + "FP16 arithmetics disabled: detected support only for SIMD operations"); } if (features & CPUINFO_ARM_LINUX_FEATURE_ASIMDRDM) { isa->rdm = true; @@ -90,8 +94,9 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( } /* - * Many phones ship with an old kernel configuration that doesn't report UDOT/SDOT instructions. - * Use a MIDR-based heuristic to whitelist processors known to support it. + * Many phones ship with an old kernel configuration that doesn't report + * UDOT/SDOT instructions. Use a MIDR-based heuristic to whitelist + * processors known to support it. */ switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { case UINT32_C(0x4100D060): /* Cortex-A65 */ @@ -137,8 +142,9 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( if (features2 & CPUINFO_ARM_LINUX_FEATURE2_SVE2) { isa->sve2 = true; } - // SVEBF16 is set iff SVE and BF16 are both supported, but the SVEBF16 feature flag - // was added in Linux kernel before the BF16 feature flag, so we check for either. + // SVEBF16 is set iff SVE and BF16 are both supported, but the SVEBF16 + // feature flag was added in Linux kernel before the BF16 feature flag, + // so we check for either. if (features2 & (CPUINFO_ARM_LINUX_FEATURE2_BF16 | CPUINFO_ARM_LINUX_FEATURE2_SVEBF16)) { isa->bf16 = true; } @@ -146,4 +152,3 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( isa->fhm = true; } } - diff --git a/3rdparty/cpuinfo/src/arm/linux/api.h b/3rdparty/cpuinfo/src/arm/linux/api.h index 2e849431d3..365fea6c7a 100644 --- a/3rdparty/cpuinfo/src/arm/linux/api.h +++ b/3rdparty/cpuinfo/src/arm/linux/api.h @@ -3,38 +3,40 @@ #include #include +#include +#include #include #include -#include -#include #include -/* No hard limit in the kernel, maximum length observed on non-rogue kernels is 64 */ +/* No hard limit in the kernel, maximum length observed on non-rogue kernels is + * 64 */ #define CPUINFO_HARDWARE_VALUE_MAX 64 -/* No hard limit in the kernel, maximum length on Raspberry Pi is 8. Add 1 symbol to detect overly large revision strings */ +/* No hard limit in the kernel, maximum length on Raspberry Pi is 8. Add 1 + * symbol to detect overly large revision strings */ #define CPUINFO_REVISION_VALUE_MAX 9 #ifdef __ANDROID__ - /* As per include/sys/system_properties.h in Android NDK */ - #define CPUINFO_BUILD_PROP_NAME_MAX 32 - #define CPUINFO_BUILD_PROP_VALUE_MAX 92 +/* As per include/sys/system_properties.h in Android NDK */ +#define CPUINFO_BUILD_PROP_NAME_MAX 32 +#define CPUINFO_BUILD_PROP_VALUE_MAX 92 - struct cpuinfo_android_properties { - char proc_cpuinfo_hardware[CPUINFO_HARDWARE_VALUE_MAX]; - char ro_product_board[CPUINFO_BUILD_PROP_VALUE_MAX]; - char ro_board_platform[CPUINFO_BUILD_PROP_VALUE_MAX]; - char ro_mediatek_platform[CPUINFO_BUILD_PROP_VALUE_MAX]; - char ro_arch[CPUINFO_BUILD_PROP_VALUE_MAX]; - char ro_chipname[CPUINFO_BUILD_PROP_VALUE_MAX]; - char ro_hardware_chipname[CPUINFO_BUILD_PROP_VALUE_MAX]; - }; +struct cpuinfo_android_properties { + char proc_cpuinfo_hardware[CPUINFO_HARDWARE_VALUE_MAX]; + char ro_product_board[CPUINFO_BUILD_PROP_VALUE_MAX]; + char ro_board_platform[CPUINFO_BUILD_PROP_VALUE_MAX]; + char ro_mediatek_platform[CPUINFO_BUILD_PROP_VALUE_MAX]; + char ro_arch[CPUINFO_BUILD_PROP_VALUE_MAX]; + char ro_chipname[CPUINFO_BUILD_PROP_VALUE_MAX]; + char ro_hardware_chipname[CPUINFO_BUILD_PROP_VALUE_MAX]; +}; #endif -#define CPUINFO_ARM_LINUX_ARCH_T UINT32_C(0x00000001) -#define CPUINFO_ARM_LINUX_ARCH_E UINT32_C(0x00000002) -#define CPUINFO_ARM_LINUX_ARCH_J UINT32_C(0x00000004) +#define CPUINFO_ARM_LINUX_ARCH_T UINT32_C(0x00000001) +#define CPUINFO_ARM_LINUX_ARCH_E UINT32_C(0x00000002) +#define CPUINFO_ARM_LINUX_ARCH_J UINT32_C(0x00000004) -#define CPUINFO_ARM_LINUX_ARCH_TE UINT32_C(0x00000003) +#define CPUINFO_ARM_LINUX_ARCH_TE UINT32_C(0x00000003) #define CPUINFO_ARM_LINUX_ARCH_TEJ UINT32_C(0x00000007) struct cpuinfo_arm_linux_proc_cpuinfo_cache { @@ -49,116 +51,118 @@ struct cpuinfo_arm_linux_proc_cpuinfo_cache { }; #if CPUINFO_ARCH_ARM - /* arch/arm/include/uapi/asm/hwcap.h */ +/* arch/arm/include/uapi/asm/hwcap.h */ - #define CPUINFO_ARM_LINUX_FEATURE_SWP UINT32_C(0x00000001) - #define CPUINFO_ARM_LINUX_FEATURE_HALF UINT32_C(0x00000002) - #define CPUINFO_ARM_LINUX_FEATURE_THUMB UINT32_C(0x00000004) - #define CPUINFO_ARM_LINUX_FEATURE_26BIT UINT32_C(0x00000008) - #define CPUINFO_ARM_LINUX_FEATURE_FASTMULT UINT32_C(0x00000010) - #define CPUINFO_ARM_LINUX_FEATURE_FPA UINT32_C(0x00000020) - #define CPUINFO_ARM_LINUX_FEATURE_VFP UINT32_C(0x00000040) - #define CPUINFO_ARM_LINUX_FEATURE_EDSP UINT32_C(0x00000080) - #define CPUINFO_ARM_LINUX_FEATURE_JAVA UINT32_C(0x00000100) - #define CPUINFO_ARM_LINUX_FEATURE_IWMMXT UINT32_C(0x00000200) - #define CPUINFO_ARM_LINUX_FEATURE_CRUNCH UINT32_C(0x00000400) - #define CPUINFO_ARM_LINUX_FEATURE_THUMBEE UINT32_C(0x00000800) - #define CPUINFO_ARM_LINUX_FEATURE_NEON UINT32_C(0x00001000) - #define CPUINFO_ARM_LINUX_FEATURE_VFPV3 UINT32_C(0x00002000) - #define CPUINFO_ARM_LINUX_FEATURE_VFPV3D16 UINT32_C(0x00004000) /* Also set for VFPv4 with 16 double-precision registers */ - #define CPUINFO_ARM_LINUX_FEATURE_TLS UINT32_C(0x00008000) - #define CPUINFO_ARM_LINUX_FEATURE_VFPV4 UINT32_C(0x00010000) - #define CPUINFO_ARM_LINUX_FEATURE_IDIVA UINT32_C(0x00020000) - #define CPUINFO_ARM_LINUX_FEATURE_IDIVT UINT32_C(0x00040000) - #define CPUINFO_ARM_LINUX_FEATURE_IDIV UINT32_C(0x00060000) - #define CPUINFO_ARM_LINUX_FEATURE_VFPD32 UINT32_C(0x00080000) - #define CPUINFO_ARM_LINUX_FEATURE_LPAE UINT32_C(0x00100000) - #define CPUINFO_ARM_LINUX_FEATURE_EVTSTRM UINT32_C(0x00200000) +#define CPUINFO_ARM_LINUX_FEATURE_SWP UINT32_C(0x00000001) +#define CPUINFO_ARM_LINUX_FEATURE_HALF UINT32_C(0x00000002) +#define CPUINFO_ARM_LINUX_FEATURE_THUMB UINT32_C(0x00000004) +#define CPUINFO_ARM_LINUX_FEATURE_26BIT UINT32_C(0x00000008) +#define CPUINFO_ARM_LINUX_FEATURE_FASTMULT UINT32_C(0x00000010) +#define CPUINFO_ARM_LINUX_FEATURE_FPA UINT32_C(0x00000020) +#define CPUINFO_ARM_LINUX_FEATURE_VFP UINT32_C(0x00000040) +#define CPUINFO_ARM_LINUX_FEATURE_EDSP UINT32_C(0x00000080) +#define CPUINFO_ARM_LINUX_FEATURE_JAVA UINT32_C(0x00000100) +#define CPUINFO_ARM_LINUX_FEATURE_IWMMXT UINT32_C(0x00000200) +#define CPUINFO_ARM_LINUX_FEATURE_CRUNCH UINT32_C(0x00000400) +#define CPUINFO_ARM_LINUX_FEATURE_THUMBEE UINT32_C(0x00000800) +#define CPUINFO_ARM_LINUX_FEATURE_NEON UINT32_C(0x00001000) +#define CPUINFO_ARM_LINUX_FEATURE_VFPV3 UINT32_C(0x00002000) +#define CPUINFO_ARM_LINUX_FEATURE_VFPV3D16 \ + UINT32_C(0x00004000) /* Also set for VFPv4 with 16 double-precision \ + registers */ +#define CPUINFO_ARM_LINUX_FEATURE_TLS UINT32_C(0x00008000) +#define CPUINFO_ARM_LINUX_FEATURE_VFPV4 UINT32_C(0x00010000) +#define CPUINFO_ARM_LINUX_FEATURE_IDIVA UINT32_C(0x00020000) +#define CPUINFO_ARM_LINUX_FEATURE_IDIVT UINT32_C(0x00040000) +#define CPUINFO_ARM_LINUX_FEATURE_IDIV UINT32_C(0x00060000) +#define CPUINFO_ARM_LINUX_FEATURE_VFPD32 UINT32_C(0x00080000) +#define CPUINFO_ARM_LINUX_FEATURE_LPAE UINT32_C(0x00100000) +#define CPUINFO_ARM_LINUX_FEATURE_EVTSTRM UINT32_C(0x00200000) - #define CPUINFO_ARM_LINUX_FEATURE2_AES UINT32_C(0x00000001) - #define CPUINFO_ARM_LINUX_FEATURE2_PMULL UINT32_C(0x00000002) - #define CPUINFO_ARM_LINUX_FEATURE2_SHA1 UINT32_C(0x00000004) - #define CPUINFO_ARM_LINUX_FEATURE2_SHA2 UINT32_C(0x00000008) - #define CPUINFO_ARM_LINUX_FEATURE2_CRC32 UINT32_C(0x00000010) +#define CPUINFO_ARM_LINUX_FEATURE2_AES UINT32_C(0x00000001) +#define CPUINFO_ARM_LINUX_FEATURE2_PMULL UINT32_C(0x00000002) +#define CPUINFO_ARM_LINUX_FEATURE2_SHA1 UINT32_C(0x00000004) +#define CPUINFO_ARM_LINUX_FEATURE2_SHA2 UINT32_C(0x00000008) +#define CPUINFO_ARM_LINUX_FEATURE2_CRC32 UINT32_C(0x00000010) #elif CPUINFO_ARCH_ARM64 - /* arch/arm64/include/uapi/asm/hwcap.h */ - #define CPUINFO_ARM_LINUX_FEATURE_FP UINT32_C(0x00000001) - #define CPUINFO_ARM_LINUX_FEATURE_ASIMD UINT32_C(0x00000002) - #define CPUINFO_ARM_LINUX_FEATURE_EVTSTRM UINT32_C(0x00000004) - #define CPUINFO_ARM_LINUX_FEATURE_AES UINT32_C(0x00000008) - #define CPUINFO_ARM_LINUX_FEATURE_PMULL UINT32_C(0x00000010) - #define CPUINFO_ARM_LINUX_FEATURE_SHA1 UINT32_C(0x00000020) - #define CPUINFO_ARM_LINUX_FEATURE_SHA2 UINT32_C(0x00000040) - #define CPUINFO_ARM_LINUX_FEATURE_CRC32 UINT32_C(0x00000080) - #define CPUINFO_ARM_LINUX_FEATURE_ATOMICS UINT32_C(0x00000100) - #define CPUINFO_ARM_LINUX_FEATURE_FPHP UINT32_C(0x00000200) - #define CPUINFO_ARM_LINUX_FEATURE_ASIMDHP UINT32_C(0x00000400) - #define CPUINFO_ARM_LINUX_FEATURE_CPUID UINT32_C(0x00000800) - #define CPUINFO_ARM_LINUX_FEATURE_ASIMDRDM UINT32_C(0x00001000) - #define CPUINFO_ARM_LINUX_FEATURE_JSCVT UINT32_C(0x00002000) - #define CPUINFO_ARM_LINUX_FEATURE_FCMA UINT32_C(0x00004000) - #define CPUINFO_ARM_LINUX_FEATURE_LRCPC UINT32_C(0x00008000) - #define CPUINFO_ARM_LINUX_FEATURE_DCPOP UINT32_C(0x00010000) - #define CPUINFO_ARM_LINUX_FEATURE_SHA3 UINT32_C(0x00020000) - #define CPUINFO_ARM_LINUX_FEATURE_SM3 UINT32_C(0x00040000) - #define CPUINFO_ARM_LINUX_FEATURE_SM4 UINT32_C(0x00080000) - #define CPUINFO_ARM_LINUX_FEATURE_ASIMDDP UINT32_C(0x00100000) - #define CPUINFO_ARM_LINUX_FEATURE_SHA512 UINT32_C(0x00200000) - #define CPUINFO_ARM_LINUX_FEATURE_SVE UINT32_C(0x00400000) - #define CPUINFO_ARM_LINUX_FEATURE_ASIMDFHM UINT32_C(0x00800000) - #define CPUINFO_ARM_LINUX_FEATURE_DIT UINT32_C(0x01000000) - #define CPUINFO_ARM_LINUX_FEATURE_USCAT UINT32_C(0x02000000) - #define CPUINFO_ARM_LINUX_FEATURE_ILRCPC UINT32_C(0x04000000) - #define CPUINFO_ARM_LINUX_FEATURE_FLAGM UINT32_C(0x08000000) - #define CPUINFO_ARM_LINUX_FEATURE_SSBS UINT32_C(0x10000000) - #define CPUINFO_ARM_LINUX_FEATURE_SB UINT32_C(0x20000000) - #define CPUINFO_ARM_LINUX_FEATURE_PACA UINT32_C(0x40000000) - #define CPUINFO_ARM_LINUX_FEATURE_PACG UINT32_C(0x80000000) +/* arch/arm64/include/uapi/asm/hwcap.h */ +#define CPUINFO_ARM_LINUX_FEATURE_FP UINT32_C(0x00000001) +#define CPUINFO_ARM_LINUX_FEATURE_ASIMD UINT32_C(0x00000002) +#define CPUINFO_ARM_LINUX_FEATURE_EVTSTRM UINT32_C(0x00000004) +#define CPUINFO_ARM_LINUX_FEATURE_AES UINT32_C(0x00000008) +#define CPUINFO_ARM_LINUX_FEATURE_PMULL UINT32_C(0x00000010) +#define CPUINFO_ARM_LINUX_FEATURE_SHA1 UINT32_C(0x00000020) +#define CPUINFO_ARM_LINUX_FEATURE_SHA2 UINT32_C(0x00000040) +#define CPUINFO_ARM_LINUX_FEATURE_CRC32 UINT32_C(0x00000080) +#define CPUINFO_ARM_LINUX_FEATURE_ATOMICS UINT32_C(0x00000100) +#define CPUINFO_ARM_LINUX_FEATURE_FPHP UINT32_C(0x00000200) +#define CPUINFO_ARM_LINUX_FEATURE_ASIMDHP UINT32_C(0x00000400) +#define CPUINFO_ARM_LINUX_FEATURE_CPUID UINT32_C(0x00000800) +#define CPUINFO_ARM_LINUX_FEATURE_ASIMDRDM UINT32_C(0x00001000) +#define CPUINFO_ARM_LINUX_FEATURE_JSCVT UINT32_C(0x00002000) +#define CPUINFO_ARM_LINUX_FEATURE_FCMA UINT32_C(0x00004000) +#define CPUINFO_ARM_LINUX_FEATURE_LRCPC UINT32_C(0x00008000) +#define CPUINFO_ARM_LINUX_FEATURE_DCPOP UINT32_C(0x00010000) +#define CPUINFO_ARM_LINUX_FEATURE_SHA3 UINT32_C(0x00020000) +#define CPUINFO_ARM_LINUX_FEATURE_SM3 UINT32_C(0x00040000) +#define CPUINFO_ARM_LINUX_FEATURE_SM4 UINT32_C(0x00080000) +#define CPUINFO_ARM_LINUX_FEATURE_ASIMDDP UINT32_C(0x00100000) +#define CPUINFO_ARM_LINUX_FEATURE_SHA512 UINT32_C(0x00200000) +#define CPUINFO_ARM_LINUX_FEATURE_SVE UINT32_C(0x00400000) +#define CPUINFO_ARM_LINUX_FEATURE_ASIMDFHM UINT32_C(0x00800000) +#define CPUINFO_ARM_LINUX_FEATURE_DIT UINT32_C(0x01000000) +#define CPUINFO_ARM_LINUX_FEATURE_USCAT UINT32_C(0x02000000) +#define CPUINFO_ARM_LINUX_FEATURE_ILRCPC UINT32_C(0x04000000) +#define CPUINFO_ARM_LINUX_FEATURE_FLAGM UINT32_C(0x08000000) +#define CPUINFO_ARM_LINUX_FEATURE_SSBS UINT32_C(0x10000000) +#define CPUINFO_ARM_LINUX_FEATURE_SB UINT32_C(0x20000000) +#define CPUINFO_ARM_LINUX_FEATURE_PACA UINT32_C(0x40000000) +#define CPUINFO_ARM_LINUX_FEATURE_PACG UINT32_C(0x80000000) - #define CPUINFO_ARM_LINUX_FEATURE2_DCPODP UINT32_C(0x00000001) - #define CPUINFO_ARM_LINUX_FEATURE2_SVE2 UINT32_C(0x00000002) - #define CPUINFO_ARM_LINUX_FEATURE2_SVEAES UINT32_C(0x00000004) - #define CPUINFO_ARM_LINUX_FEATURE2_SVEPMULL UINT32_C(0x00000008) - #define CPUINFO_ARM_LINUX_FEATURE2_SVEBITPERM UINT32_C(0x00000010) - #define CPUINFO_ARM_LINUX_FEATURE2_SVESHA3 UINT32_C(0x00000020) - #define CPUINFO_ARM_LINUX_FEATURE2_SVESM4 UINT32_C(0x00000040) - #define CPUINFO_ARM_LINUX_FEATURE2_FLAGM2 UINT32_C(0x00000080) - #define CPUINFO_ARM_LINUX_FEATURE2_FRINT UINT32_C(0x00000100) - #define CPUINFO_ARM_LINUX_FEATURE2_SVEI8MM UINT32_C(0x00000200) - #define CPUINFO_ARM_LINUX_FEATURE2_SVEF32MM UINT32_C(0x00000400) - #define CPUINFO_ARM_LINUX_FEATURE2_SVEF64MM UINT32_C(0x00000800) - #define CPUINFO_ARM_LINUX_FEATURE2_SVEBF16 UINT32_C(0x00001000) - #define CPUINFO_ARM_LINUX_FEATURE2_I8MM UINT32_C(0x00002000) - #define CPUINFO_ARM_LINUX_FEATURE2_BF16 UINT32_C(0x00004000) - #define CPUINFO_ARM_LINUX_FEATURE2_DGH UINT32_C(0x00008000) - #define CPUINFO_ARM_LINUX_FEATURE2_RNG UINT32_C(0x00010000) - #define CPUINFO_ARM_LINUX_FEATURE2_BTI UINT32_C(0x00020000) +#define CPUINFO_ARM_LINUX_FEATURE2_DCPODP UINT32_C(0x00000001) +#define CPUINFO_ARM_LINUX_FEATURE2_SVE2 UINT32_C(0x00000002) +#define CPUINFO_ARM_LINUX_FEATURE2_SVEAES UINT32_C(0x00000004) +#define CPUINFO_ARM_LINUX_FEATURE2_SVEPMULL UINT32_C(0x00000008) +#define CPUINFO_ARM_LINUX_FEATURE2_SVEBITPERM UINT32_C(0x00000010) +#define CPUINFO_ARM_LINUX_FEATURE2_SVESHA3 UINT32_C(0x00000020) +#define CPUINFO_ARM_LINUX_FEATURE2_SVESM4 UINT32_C(0x00000040) +#define CPUINFO_ARM_LINUX_FEATURE2_FLAGM2 UINT32_C(0x00000080) +#define CPUINFO_ARM_LINUX_FEATURE2_FRINT UINT32_C(0x00000100) +#define CPUINFO_ARM_LINUX_FEATURE2_SVEI8MM UINT32_C(0x00000200) +#define CPUINFO_ARM_LINUX_FEATURE2_SVEF32MM UINT32_C(0x00000400) +#define CPUINFO_ARM_LINUX_FEATURE2_SVEF64MM UINT32_C(0x00000800) +#define CPUINFO_ARM_LINUX_FEATURE2_SVEBF16 UINT32_C(0x00001000) +#define CPUINFO_ARM_LINUX_FEATURE2_I8MM UINT32_C(0x00002000) +#define CPUINFO_ARM_LINUX_FEATURE2_BF16 UINT32_C(0x00004000) +#define CPUINFO_ARM_LINUX_FEATURE2_DGH UINT32_C(0x00008000) +#define CPUINFO_ARM_LINUX_FEATURE2_RNG UINT32_C(0x00010000) +#define CPUINFO_ARM_LINUX_FEATURE2_BTI UINT32_C(0x00020000) #endif #define CPUINFO_ARM_LINUX_VALID_ARCHITECTURE UINT32_C(0x00010000) -#define CPUINFO_ARM_LINUX_VALID_IMPLEMENTER UINT32_C(0x00020000) -#define CPUINFO_ARM_LINUX_VALID_VARIANT UINT32_C(0x00040000) -#define CPUINFO_ARM_LINUX_VALID_PART UINT32_C(0x00080000) -#define CPUINFO_ARM_LINUX_VALID_REVISION UINT32_C(0x00100000) -#define CPUINFO_ARM_LINUX_VALID_PROCESSOR UINT32_C(0x00200000) -#define CPUINFO_ARM_LINUX_VALID_FEATURES UINT32_C(0x00400000) +#define CPUINFO_ARM_LINUX_VALID_IMPLEMENTER UINT32_C(0x00020000) +#define CPUINFO_ARM_LINUX_VALID_VARIANT UINT32_C(0x00040000) +#define CPUINFO_ARM_LINUX_VALID_PART UINT32_C(0x00080000) +#define CPUINFO_ARM_LINUX_VALID_REVISION UINT32_C(0x00100000) +#define CPUINFO_ARM_LINUX_VALID_PROCESSOR UINT32_C(0x00200000) +#define CPUINFO_ARM_LINUX_VALID_FEATURES UINT32_C(0x00400000) #if CPUINFO_ARCH_ARM - #define CPUINFO_ARM_LINUX_VALID_ICACHE_SIZE UINT32_C(0x01000000) - #define CPUINFO_ARM_LINUX_VALID_ICACHE_SETS UINT32_C(0x02000000) - #define CPUINFO_ARM_LINUX_VALID_ICACHE_WAYS UINT32_C(0x04000000) - #define CPUINFO_ARM_LINUX_VALID_ICACHE_LINE UINT32_C(0x08000000) - #define CPUINFO_ARM_LINUX_VALID_DCACHE_SIZE UINT32_C(0x10000000) - #define CPUINFO_ARM_LINUX_VALID_DCACHE_SETS UINT32_C(0x20000000) - #define CPUINFO_ARM_LINUX_VALID_DCACHE_WAYS UINT32_C(0x40000000) - #define CPUINFO_ARM_LINUX_VALID_DCACHE_LINE UINT32_C(0x80000000) +#define CPUINFO_ARM_LINUX_VALID_ICACHE_SIZE UINT32_C(0x01000000) +#define CPUINFO_ARM_LINUX_VALID_ICACHE_SETS UINT32_C(0x02000000) +#define CPUINFO_ARM_LINUX_VALID_ICACHE_WAYS UINT32_C(0x04000000) +#define CPUINFO_ARM_LINUX_VALID_ICACHE_LINE UINT32_C(0x08000000) +#define CPUINFO_ARM_LINUX_VALID_DCACHE_SIZE UINT32_C(0x10000000) +#define CPUINFO_ARM_LINUX_VALID_DCACHE_SETS UINT32_C(0x20000000) +#define CPUINFO_ARM_LINUX_VALID_DCACHE_WAYS UINT32_C(0x40000000) +#define CPUINFO_ARM_LINUX_VALID_DCACHE_LINE UINT32_C(0x80000000) #endif -#define CPUINFO_ARM_LINUX_VALID_INFO UINT32_C(0x007F0000) -#define CPUINFO_ARM_LINUX_VALID_MIDR UINT32_C(0x003F0000) +#define CPUINFO_ARM_LINUX_VALID_INFO UINT32_C(0x007F0000) +#define CPUINFO_ARM_LINUX_VALID_MIDR UINT32_C(0x003F0000) #if CPUINFO_ARCH_ARM - #define CPUINFO_ARM_LINUX_VALID_ICACHE UINT32_C(0x0F000000) - #define CPUINFO_ARM_LINUX_VALID_DCACHE UINT32_C(0xF0000000) - #define CPUINFO_ARM_LINUX_VALID_CACHE_LINE UINT32_C(0x88000000) +#define CPUINFO_ARM_LINUX_VALID_ICACHE UINT32_C(0x0F000000) +#define CPUINFO_ARM_LINUX_VALID_DCACHE UINT32_C(0xF0000000) +#define CPUINFO_ARM_LINUX_VALID_CACHE_LINE UINT32_C(0x88000000) #endif struct cpuinfo_arm_linux_processor { @@ -178,13 +182,15 @@ struct cpuinfo_arm_linux_processor { uint32_t uarch_index; /** * ID of the physical package which includes this logical processor. - * The value is parsed from /sys/devices/system/cpu/cpu/topology/physical_package_id + * The value is parsed from + * /sys/devices/system/cpu/cpu/topology/physical_package_id */ uint32_t package_id; /** - * Minimum processor ID on the package which includes this logical processor. - * This value can serve as an ID for the cluster of logical processors: it is the - * same for all logical processors on the same package. + * Minimum processor ID on the package which includes this logical + * processor. This value can serve as an ID for the cluster of logical + * processors: it is the same for all logical processors on the same + * package. */ uint32_t package_leader_id; /** @@ -193,14 +199,16 @@ struct cpuinfo_arm_linux_processor { uint32_t package_processor_count; /** * Maximum frequency, in kHZ. - * The value is parsed from /sys/devices/system/cpu/cpu/cpufreq/cpuinfo_max_freq - * If failed to read or parse the file, the value is 0. + * The value is parsed from + * /sys/devices/system/cpu/cpu/cpufreq/cpuinfo_max_freq If failed to + * read or parse the file, the value is 0. */ uint32_t max_frequency; /** * Minimum frequency, in kHZ. - * The value is parsed from /sys/devices/system/cpu/cpu/cpufreq/cpuinfo_min_freq - * If failed to read or parse the file, the value is 0. + * The value is parsed from + * /sys/devices/system/cpu/cpu/cpufreq/cpuinfo_min_freq If failed to + * read or parse the file, the value is 0. */ uint32_t min_frequency; /** Linux processor ID */ @@ -216,8 +224,7 @@ struct cpuinfo_arm_linux_cluster { /* Returns true if the two processors do belong to the same cluster */ static inline bool cpuinfo_arm_linux_processor_equals( struct cpuinfo_arm_linux_processor processor_i[restrict static 1], - struct cpuinfo_arm_linux_processor processor_j[restrict static 1]) -{ + struct cpuinfo_arm_linux_processor processor_j[restrict static 1]) { const uint32_t joint_flags = processor_i->flags & processor_j->flags; bool same_max_frequency = false; @@ -251,11 +258,11 @@ static inline bool cpuinfo_arm_linux_processor_equals( return same_max_frequency && same_min_frequency; } -/* Returns true if the two processors certainly don't belong to the same cluster */ +/* Returns true if the two processors certainly don't belong to the same cluster + */ static inline bool cpuinfo_arm_linux_processor_not_equals( struct cpuinfo_arm_linux_processor processor_i[restrict static 1], - struct cpuinfo_arm_linux_processor processor_j[restrict static 1]) -{ + struct cpuinfo_arm_linux_processor processor_j[restrict static 1]) { const uint32_t joint_flags = processor_i->flags & processor_j->flags; if (joint_flags & CPUINFO_LINUX_FLAG_MAX_FREQUENCY) { @@ -286,79 +293,73 @@ CPUINFO_INTERNAL bool cpuinfo_arm_linux_parse_proc_cpuinfo( struct cpuinfo_arm_linux_processor processors[restrict static max_processors_count]); #if CPUINFO_ARCH_ARM - CPUINFO_INTERNAL bool cpuinfo_arm_linux_hwcap_from_getauxval( - uint32_t hwcap[restrict static 1], - uint32_t hwcap2[restrict static 1]); - CPUINFO_INTERNAL bool cpuinfo_arm_linux_hwcap_from_procfs( - uint32_t hwcap[restrict static 1], - uint32_t hwcap2[restrict static 1]); +CPUINFO_INTERNAL bool cpuinfo_arm_linux_hwcap_from_getauxval( + uint32_t hwcap[restrict static 1], + uint32_t hwcap2[restrict static 1]); +CPUINFO_INTERNAL bool cpuinfo_arm_linux_hwcap_from_procfs( + uint32_t hwcap[restrict static 1], + uint32_t hwcap2[restrict static 1]); - CPUINFO_INTERNAL void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( - uint32_t features, - uint32_t features2, - uint32_t midr, - uint32_t architecture_version, - uint32_t architecture_flags, - const struct cpuinfo_arm_chipset chipset[restrict static 1], - struct cpuinfo_arm_isa isa[restrict static 1]); +CPUINFO_INTERNAL void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( + uint32_t features, + uint32_t features2, + uint32_t midr, + uint32_t architecture_version, + uint32_t architecture_flags, + const struct cpuinfo_arm_chipset chipset[restrict static 1], + struct cpuinfo_arm_isa isa[restrict static 1]); #elif CPUINFO_ARCH_ARM64 - CPUINFO_INTERNAL void cpuinfo_arm_linux_hwcap_from_getauxval( - uint32_t hwcap[restrict static 1], - uint32_t hwcap2[restrict static 1]); +CPUINFO_INTERNAL void cpuinfo_arm_linux_hwcap_from_getauxval( + uint32_t hwcap[restrict static 1], + uint32_t hwcap2[restrict static 1]); - CPUINFO_INTERNAL void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( - uint32_t features, - uint32_t features2, - uint32_t midr, - const struct cpuinfo_arm_chipset chipset[restrict static 1], - struct cpuinfo_arm_isa isa[restrict static 1]); +CPUINFO_INTERNAL void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( + uint32_t features, + uint32_t features2, + uint32_t midr, + const struct cpuinfo_arm_chipset chipset[restrict static 1], + struct cpuinfo_arm_isa isa[restrict static 1]); #endif #if defined(__ANDROID__) - CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_android_decode_chipset( - const struct cpuinfo_android_properties properties[restrict static 1], - uint32_t cores, - uint32_t max_cpu_freq_max); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset( + const struct cpuinfo_android_properties properties[restrict static 1], + uint32_t cores, + uint32_t max_cpu_freq_max); #else - CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_linux_decode_chipset( - const char hardware[restrict static CPUINFO_HARDWARE_VALUE_MAX], - const char revision[restrict static CPUINFO_REVISION_VALUE_MAX], - uint32_t cores, - uint32_t max_cpu_freq_max); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset( + const char hardware[restrict static CPUINFO_HARDWARE_VALUE_MAX], + const char revision[restrict static CPUINFO_REVISION_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max); #endif -CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_hardware( - const char proc_cpuinfo_hardware[restrict static CPUINFO_HARDWARE_VALUE_MAX], - uint32_t cores, uint32_t max_cpu_freq_max, bool is_tegra); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_hardware( + const char proc_cpuinfo_hardware[restrict static CPUINFO_HARDWARE_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max, + bool is_tegra); #ifdef __ANDROID__ - CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_android_decode_chipset_from_ro_product_board( - const char ro_product_board[restrict static CPUINFO_BUILD_PROP_VALUE_MAX], - uint32_t cores, uint32_t max_cpu_freq_max); - CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_android_decode_chipset_from_ro_board_platform( - const char ro_board_platform[restrict static CPUINFO_BUILD_PROP_VALUE_MAX], - uint32_t cores, uint32_t max_cpu_freq_max); - CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_android_decode_chipset_from_ro_mediatek_platform( - const char ro_mediatek_platform[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]); - CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_android_decode_chipset_from_ro_arch( - const char ro_arch[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]); - CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_android_decode_chipset_from_ro_chipname( - const char ro_chipname[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]); - CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_android_decode_chipset_from_ro_hardware_chipname( - const char ro_hardware_chipname[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_product_board( + const char ro_product_board[restrict static CPUINFO_BUILD_PROP_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_board_platform( + const char ro_board_platform[restrict static CPUINFO_BUILD_PROP_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_mediatek_platform( + const char ro_mediatek_platform[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_arch( + const char ro_arch[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_chipname( + const char ro_chipname[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_hardware_chipname( + const char ro_hardware_chipname[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]); #else - CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_revision( - const char proc_cpuinfo_revision[restrict static CPUINFO_REVISION_VALUE_MAX]); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_revision( + const char proc_cpuinfo_revision[restrict static CPUINFO_REVISION_VALUE_MAX]); #endif CPUINFO_INTERNAL bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( diff --git a/3rdparty/cpuinfo/src/arm/linux/chipset.c b/3rdparty/cpuinfo/src/arm/linux/chipset.c index 0e9191fd9c..1f93351ddd 100644 --- a/3rdparty/cpuinfo/src/arm/linux/chipset.c +++ b/3rdparty/cpuinfo/src/arm/linux/chipset.c @@ -5,11 +5,10 @@ #include #ifdef __ANDROID__ - #include +#include #endif -#include #include - +#include static inline bool is_ascii_whitespace(char c) { switch (c) { @@ -25,29 +24,30 @@ static inline bool is_ascii_whitespace(char c) { static inline bool is_ascii_alphabetic(char c) { const char lower_c = c | '\x20'; - return (uint8_t) (lower_c - 'a') <= (uint8_t) ('z' - 'a'); + return (uint8_t)(lower_c - 'a') <= (uint8_t)('z' - 'a'); } static inline bool is_ascii_alphabetic_uppercase(char c) { - return (uint8_t) (c - 'A') <= (uint8_t) ('Z' - 'A'); + return (uint8_t)(c - 'A') <= (uint8_t)('Z' - 'A'); } static inline bool is_ascii_numeric(char c) { - return (uint8_t) (c - '0') < 10; + return (uint8_t)(c - '0') < 10; } static inline uint16_t load_u16le(const void* ptr) { - const uint8_t* byte_ptr = (const uint8_t*) ptr; - return ((uint16_t) byte_ptr[1] << 8) | (uint16_t) byte_ptr[0]; + const uint8_t* byte_ptr = (const uint8_t*)ptr; + return ((uint16_t)byte_ptr[1] << 8) | (uint16_t)byte_ptr[0]; } static inline uint32_t load_u24le(const void* ptr) { - return ((uint32_t) ((const uint8_t*) ptr)[2] << 16) | (uint32_t) load_u16le(ptr); + return ((uint32_t)((const uint8_t*)ptr)[2] << 16) | (uint32_t)load_u16le(ptr); } static inline uint32_t load_u32le(const void* ptr) { - const uint8_t* byte_ptr = (const uint8_t*) ptr; - return ((uint32_t) byte_ptr[3] << 24) | ((uint32_t) byte_ptr[2] << 16) | ((uint32_t) byte_ptr[1] << 8) | (uint32_t) byte_ptr[0]; + const uint8_t* byte_ptr = (const uint8_t*)ptr; + return ((uint32_t)byte_ptr[3] << 24) | ((uint32_t)byte_ptr[2] << 16) | ((uint32_t)byte_ptr[1] << 8) | + (uint32_t)byte_ptr[0]; } /* @@ -55,63 +55,63 @@ static inline uint32_t load_u32le(const void* ptr) { * This map is used to avoid storing vendor IDs in tables. */ static enum cpuinfo_arm_chipset_vendor chipset_series_vendor[cpuinfo_arm_chipset_series_max] = { - [cpuinfo_arm_chipset_series_unknown] = cpuinfo_arm_chipset_vendor_unknown, - [cpuinfo_arm_chipset_series_qualcomm_qsd] = cpuinfo_arm_chipset_vendor_qualcomm, - [cpuinfo_arm_chipset_series_qualcomm_msm] = cpuinfo_arm_chipset_vendor_qualcomm, - [cpuinfo_arm_chipset_series_qualcomm_apq] = cpuinfo_arm_chipset_vendor_qualcomm, - [cpuinfo_arm_chipset_series_qualcomm_snapdragon] = cpuinfo_arm_chipset_vendor_qualcomm, - [cpuinfo_arm_chipset_series_mediatek_mt] = cpuinfo_arm_chipset_vendor_mediatek, - [cpuinfo_arm_chipset_series_samsung_exynos] = cpuinfo_arm_chipset_vendor_samsung, - [cpuinfo_arm_chipset_series_hisilicon_k3v] = cpuinfo_arm_chipset_vendor_hisilicon, - [cpuinfo_arm_chipset_series_hisilicon_hi] = cpuinfo_arm_chipset_vendor_hisilicon, - [cpuinfo_arm_chipset_series_hisilicon_kirin] = cpuinfo_arm_chipset_vendor_hisilicon, - [cpuinfo_arm_chipset_series_actions_atm] = cpuinfo_arm_chipset_vendor_actions, - [cpuinfo_arm_chipset_series_allwinner_a] = cpuinfo_arm_chipset_vendor_allwinner, - [cpuinfo_arm_chipset_series_amlogic_aml] = cpuinfo_arm_chipset_vendor_amlogic, - [cpuinfo_arm_chipset_series_amlogic_s] = cpuinfo_arm_chipset_vendor_amlogic, - [cpuinfo_arm_chipset_series_broadcom_bcm] = cpuinfo_arm_chipset_vendor_broadcom, - [cpuinfo_arm_chipset_series_lg_nuclun] = cpuinfo_arm_chipset_vendor_lg, - [cpuinfo_arm_chipset_series_leadcore_lc] = cpuinfo_arm_chipset_vendor_leadcore, - [cpuinfo_arm_chipset_series_marvell_pxa] = cpuinfo_arm_chipset_vendor_marvell, - [cpuinfo_arm_chipset_series_mstar_6a] = cpuinfo_arm_chipset_vendor_mstar, - [cpuinfo_arm_chipset_series_novathor_u] = cpuinfo_arm_chipset_vendor_novathor, - [cpuinfo_arm_chipset_series_nvidia_tegra_t] = cpuinfo_arm_chipset_vendor_nvidia, - [cpuinfo_arm_chipset_series_nvidia_tegra_ap] = cpuinfo_arm_chipset_vendor_nvidia, - [cpuinfo_arm_chipset_series_nvidia_tegra_sl] = cpuinfo_arm_chipset_vendor_nvidia, - [cpuinfo_arm_chipset_series_pinecone_surge_s] = cpuinfo_arm_chipset_vendor_pinecone, - [cpuinfo_arm_chipset_series_renesas_mp] = cpuinfo_arm_chipset_vendor_renesas, - [cpuinfo_arm_chipset_series_rockchip_rk] = cpuinfo_arm_chipset_vendor_rockchip, - [cpuinfo_arm_chipset_series_spreadtrum_sc] = cpuinfo_arm_chipset_vendor_spreadtrum, - [cpuinfo_arm_chipset_series_telechips_tcc] = cpuinfo_arm_chipset_vendor_telechips, + [cpuinfo_arm_chipset_series_unknown] = cpuinfo_arm_chipset_vendor_unknown, + [cpuinfo_arm_chipset_series_qualcomm_qsd] = cpuinfo_arm_chipset_vendor_qualcomm, + [cpuinfo_arm_chipset_series_qualcomm_msm] = cpuinfo_arm_chipset_vendor_qualcomm, + [cpuinfo_arm_chipset_series_qualcomm_apq] = cpuinfo_arm_chipset_vendor_qualcomm, + [cpuinfo_arm_chipset_series_qualcomm_snapdragon] = cpuinfo_arm_chipset_vendor_qualcomm, + [cpuinfo_arm_chipset_series_mediatek_mt] = cpuinfo_arm_chipset_vendor_mediatek, + [cpuinfo_arm_chipset_series_samsung_exynos] = cpuinfo_arm_chipset_vendor_samsung, + [cpuinfo_arm_chipset_series_hisilicon_k3v] = cpuinfo_arm_chipset_vendor_hisilicon, + [cpuinfo_arm_chipset_series_hisilicon_hi] = cpuinfo_arm_chipset_vendor_hisilicon, + [cpuinfo_arm_chipset_series_hisilicon_kirin] = cpuinfo_arm_chipset_vendor_hisilicon, + [cpuinfo_arm_chipset_series_actions_atm] = cpuinfo_arm_chipset_vendor_actions, + [cpuinfo_arm_chipset_series_allwinner_a] = cpuinfo_arm_chipset_vendor_allwinner, + [cpuinfo_arm_chipset_series_amlogic_aml] = cpuinfo_arm_chipset_vendor_amlogic, + [cpuinfo_arm_chipset_series_amlogic_s] = cpuinfo_arm_chipset_vendor_amlogic, + [cpuinfo_arm_chipset_series_broadcom_bcm] = cpuinfo_arm_chipset_vendor_broadcom, + [cpuinfo_arm_chipset_series_lg_nuclun] = cpuinfo_arm_chipset_vendor_lg, + [cpuinfo_arm_chipset_series_leadcore_lc] = cpuinfo_arm_chipset_vendor_leadcore, + [cpuinfo_arm_chipset_series_marvell_pxa] = cpuinfo_arm_chipset_vendor_marvell, + [cpuinfo_arm_chipset_series_mstar_6a] = cpuinfo_arm_chipset_vendor_mstar, + [cpuinfo_arm_chipset_series_novathor_u] = cpuinfo_arm_chipset_vendor_novathor, + [cpuinfo_arm_chipset_series_nvidia_tegra_t] = cpuinfo_arm_chipset_vendor_nvidia, + [cpuinfo_arm_chipset_series_nvidia_tegra_ap] = cpuinfo_arm_chipset_vendor_nvidia, + [cpuinfo_arm_chipset_series_nvidia_tegra_sl] = cpuinfo_arm_chipset_vendor_nvidia, + [cpuinfo_arm_chipset_series_pinecone_surge_s] = cpuinfo_arm_chipset_vendor_pinecone, + [cpuinfo_arm_chipset_series_renesas_mp] = cpuinfo_arm_chipset_vendor_renesas, + [cpuinfo_arm_chipset_series_rockchip_rk] = cpuinfo_arm_chipset_vendor_rockchip, + [cpuinfo_arm_chipset_series_spreadtrum_sc] = cpuinfo_arm_chipset_vendor_spreadtrum, + [cpuinfo_arm_chipset_series_telechips_tcc] = cpuinfo_arm_chipset_vendor_telechips, [cpuinfo_arm_chipset_series_texas_instruments_omap] = cpuinfo_arm_chipset_vendor_texas_instruments, - [cpuinfo_arm_chipset_series_unisoc_t] = cpuinfo_arm_chipset_vendor_unisoc, - [cpuinfo_arm_chipset_series_wondermedia_wm] = cpuinfo_arm_chipset_vendor_wondermedia, + [cpuinfo_arm_chipset_series_unisoc_t] = cpuinfo_arm_chipset_vendor_unisoc, + [cpuinfo_arm_chipset_series_wondermedia_wm] = cpuinfo_arm_chipset_vendor_wondermedia, }; /** - * Tries to match /(MSM|APQ)\d{4}([A-Z\-]*)/ signature (case-insensitive) for Qualcomm MSM and APQ chipsets. - * If match successful, extracts model information into \p chipset argument. + * Tries to match /(MSM|APQ)\d{4}([A-Z\-]*)/ signature (case-insensitive) for + * Qualcomm MSM and APQ chipsets. If match successful, extracts model + * information into \p chipset argument. * - * @param start - start of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, ro.board.platform - * or ro.chipname) to match. - * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, ro.board.platform or - * ro.chipname) to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param start - start of the platform identifier (/proc/cpuinfo Hardware + * string, ro.product.board, ro.board.platform or ro.chipname) to match. + * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, + * ro.product.board, ro.board.platform or ro.chipname) to match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_msm_apq( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ +static bool match_msm_apq(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* Expect at least 7 symbols: 3 symbols "MSM" or "APQ" + 4 digits */ if (start + 7 > end) { return false; } /* Check that string starts with "MSM" or "APQ", case-insensitive. - * The first three characters are loaded as 24-bit little endian word, binary ORed with 0x20 to convert to lower - * case, and compared to "MSM" and "APQ" strings as integers. + * The first three characters are loaded as 24-bit little endian word, + * binary ORed with 0x20 to convert to lower case, and compared to "MSM" + * and "APQ" strings as integers. */ const uint32_t series_signature = UINT32_C(0x00202020) | load_u24le(start); enum cpuinfo_arm_chipset_series series; @@ -140,7 +140,7 @@ static bool match_msm_apq( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 0; i < 4; i++) { - const uint32_t digit = (uint32_t) (uint8_t) (*pos++) - '0'; + const uint32_t digit = (uint32_t)(uint8_t)(*pos++) - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -148,8 +148,9 @@ static bool match_msm_apq( model = model * 10 + digit; } - /* Suffix is optional, so if we got to this point, parsing is successful. Commit parsed chipset. */ - *chipset = (struct cpuinfo_arm_chipset) { + /* Suffix is optional, so if we got to this point, parsing is + * successful. Commit parsed chipset. */ + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_qualcomm, .series = series, .model = model, @@ -182,21 +183,20 @@ static bool match_msm_apq( * * @param start - start of the /proc/cpuinfo Hardware string to match. * @param end - end of the /proc/cpuinfo Hardware string to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_sdm( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ +static bool match_sdm(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* Expect exactly 6 symbols: 3 symbols "SDM" + 3 digits */ if (start + 6 != end) { return false; } /* Check that string starts with "SDM". - * The first three characters are loaded and compared as 24-bit little endian word. + * The first three characters are loaded and compared as 24-bit little + * endian word. */ const uint32_t expected_sdm = load_u24le(start); if (expected_sdm != UINT32_C(0x004D4453) /* "MDS" = reverse("SDM") */) { @@ -206,7 +206,7 @@ static bool match_sdm( /* Validate and parse 3-digit model number */ uint32_t model = 0; for (uint32_t i = 3; i < 6; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -215,7 +215,7 @@ static bool match_sdm( } /* Return parsed chipset. */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_qualcomm, .series = cpuinfo_arm_chipset_series_qualcomm_snapdragon, .model = model, @@ -229,21 +229,20 @@ static bool match_sdm( * * @param start - start of the /proc/cpuinfo Hardware string to match. * @param end - end of the /proc/cpuinfo Hardware string to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_sm( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ +static bool match_sm(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* Expect exactly 6 symbols: 2 symbols "SM" + 4 digits */ if (start + 6 != end) { return false; } /* Check that string starts with "SM". - * The first three characters are loaded and compared as 16-bit little endian word. + * The first three characters are loaded and compared as 16-bit little + * endian word. */ const uint32_t expected_sm = load_u16le(start); if (expected_sm != UINT16_C(0x4D53) /* "MS" = reverse("SM") */) { @@ -253,7 +252,7 @@ static bool match_sm( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 2; i < 6; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -262,7 +261,7 @@ static bool match_sm( } /* Return parsed chipset. */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_qualcomm, .series = cpuinfo_arm_chipset_series_qualcomm_snapdragon, .model = model, @@ -271,22 +270,25 @@ static bool match_sm( } /** - * Tries to match /Samsung Exynos\d{4}$/ signature (case-insensitive) for Samsung Exynos chipsets. - * If match successful, extracts model information into \p chipset argument. + * Tries to match /Samsung Exynos\d{4}$/ signature (case-insensitive) for + * Samsung Exynos chipsets. If match successful, extracts model information into + * \p chipset argument. * * @param start - start of the /proc/cpuinfo Hardware string to match. * @param end - end of the /proc/cpuinfo Hardware string to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ static bool match_samsung_exynos( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ + const char* start, + const char* end, + struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* * Expect at 18-19 symbols: - * - "Samsung" (7 symbols) + space + "Exynos" (6 symbols) + optional space 4-digit model number + * - "Samsung" (7 symbols) + space + "Exynos" (6 symbols) + optional + * space 4-digit model number */ const size_t length = end - start; switch (length) { @@ -299,8 +301,9 @@ static bool match_samsung_exynos( /* * Check that the string starts with "samsung exynos", case-insensitive. - * Blocks of 4 characters are loaded and compared as little-endian 32-bit word. - * Case-insensitive characters are binary ORed with 0x20 to convert them to lowercase. + * Blocks of 4 characters are loaded and compared as little-endian + * 32-bit word. Case-insensitive characters are binary ORed with 0x20 to + * convert them to lowercase. */ const uint32_t expected_sams = UINT32_C(0x20202000) | load_u32le(start); if (expected_sams != UINT32_C(0x736D6153) /* "smaS" = reverse("Sams") */) { @@ -325,7 +328,8 @@ static bool match_samsung_exynos( if (*pos == ' ') { pos++; - /* If optional space if present, we expect exactly 19 characters */ + /* If optional space if present, we expect exactly 19 characters + */ if (length != 19) { return false; } @@ -334,7 +338,7 @@ static bool match_samsung_exynos( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 0; i < 4; i++) { - const uint32_t digit = (uint32_t) (uint8_t) (*pos++) - '0'; + const uint32_t digit = (uint32_t)(uint8_t)(*pos++) - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -343,7 +347,7 @@ static bool match_samsung_exynos( } /* Return parsed chipset */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_samsung, .series = cpuinfo_arm_chipset_series_samsung_exynos, .model = model, @@ -355,37 +359,38 @@ static bool match_samsung_exynos( * Tries to match /exynos\d{4}$/ signature for Samsung Exynos chipsets. * If match successful, extracts model information into \p chipset argument. * - * @param start - start of the platform identifier (ro.board.platform or ro.chipname) to match. - * @param end - end of the platform identifier (ro.board.platform or ro.chipname) to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param start - start of the platform identifier (ro.board.platform or + * ro.chipname) to match. + * @param end - end of the platform identifier (ro.board.platform or + * ro.chipname) to match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_exynos( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect exactly 10 symbols: "exynos" (6 symbols) + 4-digit model number */ +static bool match_exynos(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect exactly 10 symbols: "exynos" (6 symbols) + 4-digit model + * number */ if (start + 10 != end) { return false; } /* Load first 4 bytes as little endian 32-bit word */ const uint32_t expected_exyn = load_u32le(start); - if (expected_exyn != UINT32_C(0x6E797865) /* "nyxe" = reverse("exyn") */ ) { + if (expected_exyn != UINT32_C(0x6E797865) /* "nyxe" = reverse("exyn") */) { return false; } /* Load next 2 bytes as little endian 16-bit word */ const uint16_t expected_os = load_u16le(start + 4); - if (expected_os != UINT16_C(0x736F) /* "so" = reverse("os") */ ) { + if (expected_os != UINT16_C(0x736F) /* "so" = reverse("os") */) { return false; } /* Check and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 6; i < 10; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -394,7 +399,7 @@ static bool match_exynos( } /* Return parsed chipset. */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_samsung, .series = cpuinfo_arm_chipset_series_samsung_exynos, .model = model, @@ -406,34 +411,35 @@ static bool match_exynos( * Tries to match /universal\d{4}$/ signature for Samsung Exynos chipsets. * If match successful, extracts model information into \p chipset argument. * - * @param start - start of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board or ro.chipname) - * to match. - * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board or ro.chipname) - * to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param start - start of the platform identifier (/proc/cpuinfo Hardware + * string, ro.product.board or ro.chipname) to match. + * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, + * ro.product.board or ro.chipname) to match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_universal( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect exactly 13 symbols: "universal" (9 symbols) + 4-digit model number */ +static bool match_universal(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect exactly 13 symbols: "universal" (9 symbols) + 4-digit model + * number + */ if (start + 13 != end) { return false; } /* * Check that the string starts with "universal". - * Blocks of 4 characters are loaded and compared as little-endian 32-bit word. - * Case-insensitive characters are binary ORed with 0x20 to convert them to lowercase. + * Blocks of 4 characters are loaded and compared as little-endian + * 32-bit word. Case-insensitive characters are binary ORed with 0x20 to + * convert them to lowercase. */ - const uint8_t expected_u = UINT8_C(0x20) | (uint8_t) start[0]; + const uint8_t expected_u = UINT8_C(0x20) | (uint8_t)start[0]; if (expected_u != UINT8_C(0x75) /* "u" */) { return false; } const uint32_t expected_nive = UINT32_C(0x20202020) | load_u32le(start + 1); - if (expected_nive != UINT32_C(0x6576696E) /* "evin" = reverse("nive") */ ) { + if (expected_nive != UINT32_C(0x6576696E) /* "evin" = reverse("nive") */) { return false; } const uint32_t expected_ersa = UINT32_C(0x20202020) | load_u32le(start + 5); @@ -444,7 +450,7 @@ static bool match_universal( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 9; i < 13; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -453,7 +459,7 @@ static bool match_universal( } /* Return parsed chipset. */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_samsung, .series = cpuinfo_arm_chipset_series_samsung_exynos, .model = model, @@ -462,29 +468,36 @@ static bool match_universal( } /** - * Compares, case insensitively, a string to known values "SMDK4210" and "SMDK4x12" for Samsung Exynos chipsets. - * If platform identifier matches one of the SMDK* values, extracts model information into \p chipset argument. - * For "SMDK4x12" match, decodes the chipset name using number of cores. + * Compares, case insensitively, a string to known values "SMDK4210" and + * "SMDK4x12" for Samsung Exynos chipsets. If platform identifier matches one of + * the SMDK* values, extracts model information into \p chipset argument. For + * "SMDK4x12" match, decodes the chipset name using number of cores. * - * @param start - start of the platform identifier (/proc/cpuinfo Hardware string or ro.product.board) to match. - * @param end - end of the platform identifier (/proc/cpuinfo Hardware string or ro.product.board) to match. + * @param start - start of the platform identifier (/proc/cpuinfo Hardware + * string or ro.product.board) to match. + * @param end - end of the platform identifier (/proc/cpuinfo Hardware string or + * ro.product.board) to match. * @param cores - number of cores in the chipset. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ static bool match_and_parse_smdk( - const char* start, const char* end, uint32_t cores, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect exactly 8 symbols: "SMDK" (4 symbols) + 4-digit model number */ + const char* start, + const char* end, + uint32_t cores, + struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect exactly 8 symbols: "SMDK" (4 symbols) + 4-digit model number + */ if (start + 8 != end) { return false; } /* * Check that string starts with "MT" (case-insensitive). - * The first four characters are loaded as a 32-bit little endian word and converted to lowercase. + * The first four characters are loaded as a 32-bit little endian word + * and converted to lowercase. */ const uint32_t expected_smdk = UINT32_C(0x20202020) | load_u32le(start); if (expected_smdk != UINT32_C(0x6B646D73) /* "kdms" = reverse("smdk") */) { @@ -493,7 +506,8 @@ static bool match_and_parse_smdk( /* * Check that string ends with "4210" or "4x12". - * The last four characters are loaded and compared as a 32-bit little endian word. + * The last four characters are loaded and compared as a 32-bit little + * endian word. */ uint32_t model = 0; const uint32_t expected_model = load_u32le(start + 4); @@ -510,7 +524,8 @@ static bool match_and_parse_smdk( model = 4412; break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core Exynos 4x12 chipset", cores); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 "-core Exynos 4x12 chipset", cores); } } @@ -518,7 +533,7 @@ static bool match_and_parse_smdk( return false; } - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_samsung, .series = cpuinfo_arm_chipset_series_samsung_exynos, .model = model, @@ -530,21 +545,26 @@ static bool match_and_parse_smdk( * Tries to match /MTK?\d{4}[A-Z/]*$/ signature for MediaTek MT chipsets. * If match successful, extracts model information into \p chipset argument. * - * @param start - start of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, ro.board.platform, - * ro.mediatek.platform, or ro.chipname) to match. - * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, ro.board.platform, - * ro.mediatek.platform, or ro.chipname) to match. - * @param match_end - indicates if the function should attempt to match through the end of the string and fail if there - * are unparsed characters in the end, or match only MTK signature, model number, and some of the - * suffix characters (the ones that pass validation). - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param start - start of the platform identifier (/proc/cpuinfo Hardware + * string, ro.product.board, ro.board.platform, ro.mediatek.platform, or + * ro.chipname) to match. + * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, + * ro.product.board, ro.board.platform, ro.mediatek.platform, or ro.chipname) to + * match. + * @param match_end - indicates if the function should attempt to match through + * the end of the string and fail if there are unparsed characters in the end, + * or match only MTK signature, model number, and some of the suffix characters + * (the ones that pass validation). + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ static bool match_mt( - const char* start, const char* end, bool match_end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ + const char* start, + const char* end, + bool match_end, + struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* Expect at least 6 symbols: "MT" (2 symbols) + 4-digit model number */ if (start + 6 > end) { return false; @@ -552,17 +572,17 @@ static bool match_mt( /* * Check that string starts with "MT" (case-insensitive). - * The first two characters are loaded as 16-bit little endian word and converted to lowercase. + * The first two characters are loaded as 16-bit little endian word and + * converted to lowercase. */ const uint16_t mt = UINT16_C(0x2020) | load_u16le(start); if (mt != UINT16_C(0x746D) /* "tm" */) { return false; } - /* Some images report "MTK" rather than "MT" */ const char* pos = start + 2; - if (((uint8_t) *pos | UINT8_C(0x20)) == (uint8_t) 'k') { + if (((uint8_t)*pos | UINT8_C(0x20)) == (uint8_t)'k') { pos++; /* Expect 4 more symbols after "MTK" (4-digit model number) */ @@ -574,7 +594,7 @@ static bool match_mt( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 0; i < 4; i++) { - const uint32_t digit = (uint32_t) (uint8_t) (*pos++) - '0'; + const uint32_t digit = (uint32_t)(uint8_t)(*pos++) - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -582,31 +602,36 @@ static bool match_mt( model = model * 10 + digit; } - /* Record parsed chipset. This implicitly zeroes-out suffix, which will be parsed later. */ - *chipset = (struct cpuinfo_arm_chipset) { + /* Record parsed chipset. This implicitly zeroes-out suffix, which will + * be parsed later. */ + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_mediatek, .series = cpuinfo_arm_chipset_series_mediatek_mt, .model = model, }; if (match_end) { - /* Check that the potential suffix does not exceed maximum length */ + /* Check that the potential suffix does not exceed maximum + * length */ const size_t suffix_length = end - pos; if (suffix_length > CPUINFO_ARM_CHIPSET_SUFFIX_MAX) { return false; } - /* Validate suffix characters and copy them to chipset structure */ + /* Validate suffix characters and copy them to chipset structure + */ for (size_t i = 0; i < suffix_length; i++) { const char c = (*pos++); if (is_ascii_alphabetic(c)) { - /* Matched a letter [A-Za-z], convert to uppercase */ + /* Matched a letter [A-Za-z], convert to + * uppercase */ chipset->suffix[i] = c & '\xDF'; } else if (c == '/') { /* Matched a slash '/' */ chipset->suffix[i] = c; } else { - /* Invalid suffix character (neither of [A-Za-z/]) */ + /* Invalid suffix character (neither of + * [A-Za-z/]) */ return false; } } @@ -619,18 +644,22 @@ static bool match_mt( const char c = pos[i]; if (is_ascii_alphabetic(c)) { - /* Matched a letter [A-Za-z], convert to uppercase */ + /* Matched a letter [A-Za-z], convert to + * uppercase */ chipset->suffix[i] = c & '\xDF'; } else if (c == '/') { /* Matched a slash '/' */ chipset->suffix[i] = c; } else { - /* Invalid suffix character (neither of [A-Za-z/]). This marks the end of the suffix. */ + /* Invalid suffix character (neither of + * [A-Za-z/]). This marks the end of the suffix. + */ break; } } } - /* All suffix characters successfully validated and copied to chipset data */ + /* All suffix characters successfully validated and copied to chipset + * data */ return true; } @@ -640,15 +669,14 @@ static bool match_mt( * * @param start - start of the /proc/cpuinfo Hardware string to match. * @param end - end of the /proc/cpuinfo Hardware string to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_kirin( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect 8-9 symbols: "Kirin" (5 symbols) + optional whitespace (1 symbol) + 3-digit model number */ +static bool match_kirin(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect 8-9 symbols: "Kirin" (5 symbols) + optional whitespace (1 + * symbol) + 3-digit model number */ const size_t length = end - start; switch (length) { case 8: @@ -659,7 +687,7 @@ static bool match_kirin( } /* Check that the string starts with "Kirin" or "kirin". */ - if (((uint8_t) start[0] | UINT8_C(0x20)) != (uint8_t) 'k') { + if (((uint8_t)start[0] | UINT8_C(0x20)) != (uint8_t)'k') { return false; } /* Symbols 1-5 are loaded and compared as little-endian 32-bit word. */ @@ -670,7 +698,8 @@ static bool match_kirin( /* Check for optional whitespace after "Kirin" */ if (is_ascii_whitespace(start[5])) { - /* When whitespace is present after "Kirin", expect 9 symbols total */ + /* When whitespace is present after "Kirin", expect 9 symbols + * total */ if (length != 9) { return false; } @@ -679,7 +708,7 @@ static bool match_kirin( /* Validate and parse 3-digit model number */ uint32_t model = 0; for (int32_t i = 0; i < 3; i++) { - const uint32_t digit = (uint32_t) (uint8_t) end[i - 3] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)end[i - 3] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -689,10 +718,11 @@ static bool match_kirin( /* * Thats it, return parsed chipset. - * Technically, Kirin 910T has a suffix, but it never appears in the form of "910T" string. - * Instead, Kirin 910T devices report "hi6620oem" string (handled outside of this function). + * Technically, Kirin 910T has a suffix, but it never appears in the + * form of "910T" string. Instead, Kirin 910T devices report "hi6620oem" + * string (handled outside of this function). */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_hisilicon, .series = cpuinfo_arm_chipset_series_hisilicon_kirin, .model = model, @@ -704,17 +734,18 @@ static bool match_kirin( * Tries to match /rk\d{4}[a-z]?$/ signature for Rockchip RK chipsets. * If match successful, extracts model information into \p chipset argument. * - * @param start - start of the platform identifier (/proc/cpuinfo Hardware string or ro.board.platform) to match. - * @param end - end of the platform identifier (/proc/cpuinfo Hardware string or ro.board.platform) to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param start - start of the platform identifier (/proc/cpuinfo Hardware + * string or ro.board.platform) to match. + * @param end - end of the platform identifier (/proc/cpuinfo Hardware string or + * ro.board.platform) to match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_rk( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect 6-7 symbols: "RK" (2 symbols) + 4-digit model number + optional 1-letter suffix */ +static bool match_rk(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect 6-7 symbols: "RK" (2 symbols) + 4-digit model number + + * optional 1-letter suffix */ const size_t length = end - start; switch (length) { case 6: @@ -726,7 +757,8 @@ static bool match_rk( /* * Check that string starts with "RK" (case-insensitive). - * The first two characters are loaded as 16-bit little endian word and converted to lowercase. + * The first two characters are loaded as 16-bit little endian word and + * converted to lowercase. */ const uint16_t expected_rk = UINT16_C(0x2020) | load_u16le(start); if (expected_rk != UINT16_C(0x6B72) /* "kr" = reverse("rk") */) { @@ -736,7 +768,7 @@ static bool match_rk( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 2; i < 6; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -759,33 +791,33 @@ static bool match_rk( } /* Return parsed chipset */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_rockchip, .series = cpuinfo_arm_chipset_series_rockchip_rk, .model = model, - .suffix = { - [0] = suffix, - }, + .suffix = + { + [0] = suffix, + }, }; return true; } /** - * Tries to match, case-insentitively, /s[cp]\d{4}[a-z]*|scx15$/ signature for Spreadtrum SC chipsets. - * If match successful, extracts model information into \p chipset argument. + * Tries to match, case-insentitively, /s[cp]\d{4}[a-z]*|scx15$/ signature for + * Spreadtrum SC chipsets. If match successful, extracts model information into + * \p chipset argument. * - * @param start - start of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, - * ro.board.platform, or ro.chipname) to match. - * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, - * ro.board.platform, or ro.chipname) to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param start - start of the platform identifier (/proc/cpuinfo Hardware + * string, ro.product.board, ro.board.platform, or ro.chipname) to match. + * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, + * ro.product.board, ro.board.platform, or ro.chipname) to match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_sc( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ +static bool match_sc(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* Expect at least 5 symbols: "scx15" */ if (start + 5 > end) { return false; @@ -793,7 +825,8 @@ static bool match_sc( /* * Check that string starts with "S[CP]" (case-insensitive). - * The first two characters are loaded as 16-bit little endian word and converted to lowercase. + * The first two characters are loaded as 16-bit little endian word and + * converted to lowercase. */ const uint16_t expected_sc_or_sp = UINT16_C(0x2020) | load_u16le(start); switch (expected_sc_or_sp) { @@ -813,11 +846,11 @@ static bool match_sc( /* Check that string ends with "15" */ const uint16_t expected_15 = load_u16le(start + 3); - if (expected_15 != UINT16_C(0x3531) /* "51" = reverse("15") */ ) { + if (expected_15 != UINT16_C(0x3531) /* "51" = reverse("15") */) { return false; } - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_spreadtrum, .series = cpuinfo_arm_chipset_series_spreadtrum_sc, .model = 7715, @@ -825,7 +858,8 @@ static bool match_sc( return true; } - /* Expect at least 6 symbols: "S[CP]" (2 symbols) + 4-digit model number */ + /* Expect at least 6 symbols: "S[CP]" (2 symbols) + 4-digit model number + */ if (start + 6 > end) { return false; } @@ -833,7 +867,7 @@ static bool match_sc( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 2; i < 6; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -842,13 +876,14 @@ static bool match_sc( } /* Write parsed chipset */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_spreadtrum, .series = cpuinfo_arm_chipset_series_spreadtrum_sc, .model = model, }; - /* Validate and copy suffix letters. If suffix is too long, truncate at CPUINFO_ARM_CHIPSET_SUFFIX_MAX letters. */ + /* Validate and copy suffix letters. If suffix is too long, truncate at + * CPUINFO_ARM_CHIPSET_SUFFIX_MAX letters. */ const char* suffix = start + 6; for (size_t i = 0; i < CPUINFO_ARM_CHIPSET_SUFFIX_MAX; i++) { if (suffix + i == end) { @@ -867,22 +902,22 @@ static bool match_sc( } /** - * Tries to match, case-sentitively, /Unisoc T\d{3,4}/ signature for Unisoc T chipset. - * If match successful, extracts model information into \p chipset argument. + * Tries to match, case-sentitively, /Unisoc T\d{3,4}/ signature for Unisoc T + * chipset. If match successful, extracts model information into \p chipset + * argument. * - * @param start - start of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, - * ro.board.platform, or ro.chipname) to match. - * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, - * ro.board.platform, or ro.chipname) to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param start - start of the platform identifier (/proc/cpuinfo Hardware + * string, ro.product.board, ro.board.platform, or ro.chipname) to match. + * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, + * ro.product.board, ro.board.platform, or ro.chipname) to match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_t( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect 11-12 symbols: "Unisoc T" (8 symbols) + 3-4-digit model number */ +static bool match_t(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect 11-12 symbols: "Unisoc T" (8 symbols) + 3-4-digit model number + */ const size_t length = end - start; switch (length) { case 11: @@ -892,7 +927,8 @@ static bool match_t( return false; } - /* Check that string starts with "Unisoc T". The first four characters are loaded as 32-bit little endian word */ + /* Check that string starts with "Unisoc T". The first four characters + * are loaded as 32-bit little endian word */ const uint32_t expected_unis = load_u32le(start); if (expected_unis != UINT32_C(0x73696E55) /* "sinU" = reverse("Unis") */) { return false; @@ -907,7 +943,7 @@ static bool match_t( /* Validate and parse 3-4 digit model number */ uint32_t model = 0; for (uint32_t i = 8; i < length; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -915,7 +951,7 @@ static bool match_t( model = model * 10 + digit; } - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_unisoc, .series = cpuinfo_arm_chipset_series_unisoc_t, .model = model, @@ -927,17 +963,18 @@ static bool match_t( * Tries to match /lc\d{4}[a-z]?$/ signature for Leadcore LC chipsets. * If match successful, extracts model information into \p chipset argument. * - * @param start - start of the platform identifier (ro.product.board or ro.board.platform) to match. - * @param end - end of the platform identifier (ro.product.board or ro.board.platform) to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param start - start of the platform identifier (ro.product.board or + * ro.board.platform) to match. + * @param end - end of the platform identifier (ro.product.board or + * ro.board.platform) to match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_lc( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect 6-7 symbols: "lc" (2 symbols) + 4-digit model number + optional 1-letter suffix */ +static bool match_lc(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect 6-7 symbols: "lc" (2 symbols) + 4-digit model number + + * optional 1-letter suffix */ const size_t length = end - start; switch (length) { case 6: @@ -947,7 +984,8 @@ static bool match_lc( return false; } - /* Check that string starts with "lc". The first two characters are loaded as 16-bit little endian word */ + /* Check that string starts with "lc". The first two characters are + * loaded as 16-bit little endian word */ const uint16_t expected_lc = load_u16le(start); if (expected_lc != UINT16_C(0x636C) /* "cl" = reverse("lc") */) { return false; @@ -956,7 +994,7 @@ static bool match_lc( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 2; i < 6; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -978,13 +1016,14 @@ static bool match_lc( } /* Return parsed chipset */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_leadcore, .series = cpuinfo_arm_chipset_series_leadcore_lc, .model = model, - .suffix = { - [0] = suffix, - }, + .suffix = + { + [0] = suffix, + }, }; return true; } @@ -993,18 +1032,16 @@ static bool match_lc( * Tries to match /PXA(\d{3,4}|1L88)$/ signature for Marvell PXA chipsets. * If match successful, extracts model information into \p chipset argument. * - * @param start - start of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board or ro.chipname) - * to match. - * @param end - end of the platform identifier (/proc/cpuinfo Hardaware string, ro.product.board or ro.chipname) to - * match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param start - start of the platform identifier (/proc/cpuinfo Hardware + * string, ro.product.board or ro.chipname) to match. + * @param end - end of the platform identifier (/proc/cpuinfo Hardaware string, + * ro.product.board or ro.chipname) to match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_pxa( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ +static bool match_pxa(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* Expect 6-7 symbols: "PXA" (3 symbols) + 3-4 digit model number */ const size_t length = end - start; switch (length) { @@ -1015,7 +1052,8 @@ static bool match_pxa( return false; } - /* Check that the string starts with "PXA". Symbols 1-3 are loaded and compared as little-endian 16-bit word. */ + /* Check that the string starts with "PXA". Symbols 1-3 are loaded and + * compared as little-endian 16-bit word. */ if (start[0] != 'P') { return false; } @@ -1026,10 +1064,10 @@ static bool match_pxa( uint32_t model = 0; - /* Check for a very common typo: "PXA1L88" for "PXA1088" */ if (length == 7) { - /* Load 4 model "number" symbols as a little endian 32-bit word and compare to "1L88" */ + /* Load 4 model "number" symbols as a little endian 32-bit word + * and compare to "1L88" */ const uint32_t expected_1L88 = load_u32le(start + 3); if (expected_1L88 == UINT32_C(0x38384C31) /* "88L1" = reverse("1L88") */) { model = 1088; @@ -1039,7 +1077,7 @@ static bool match_pxa( /* Check and parse 3-4 digit model number */ for (uint32_t i = 3; i < length; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -1049,7 +1087,7 @@ static bool match_pxa( /* Return parsed chipset. */ write_chipset: - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_marvell, .series = cpuinfo_arm_chipset_series_marvell_pxa, .model = model, @@ -1063,21 +1101,20 @@ write_chipset: * * @param start - start of the /proc/cpuinfo Hardware string to match. * @param end - end of the /proc/cpuinfo Hardware string to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_bcm( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ +static bool match_bcm(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* Expect exactly 7 symbols: "BCM" (3 symbols) + 4-digit model number */ if (start + 7 != end) { return false; } /* Check that the string starts with "BCM". - * The first three characters are loaded and compared as a 24-bit little endian word. + * The first three characters are loaded and compared as a 24-bit little + * endian word. */ const uint32_t expected_bcm = load_u24le(start); if (expected_bcm != UINT32_C(0x004D4342) /* "MCB" = reverse("BCM") */) { @@ -1087,7 +1124,7 @@ static bool match_bcm( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 3; i < 7; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -1096,7 +1133,7 @@ static bool match_bcm( } /* Return parsed chipset. */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_broadcom, .series = cpuinfo_arm_chipset_series_broadcom_bcm, .model = model, @@ -1110,20 +1147,20 @@ static bool match_bcm( * * @param start - start of the /proc/cpuinfo Hardware string to match. * @param end - end of the /proc/cpuinfo Hardware string to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_omap( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect exactly 8 symbols: "OMAP" (4 symbols) + 4-digit model number */ +static bool match_omap(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect exactly 8 symbols: "OMAP" (4 symbols) + 4-digit model number + */ if (start + 8 != end) { return false; } - /* Check that the string starts with "OMAP". Symbols 0-4 are loaded and compared as little-endian 32-bit word. */ + /* Check that the string starts with "OMAP". Symbols 0-4 are loaded and + * compared as little-endian 32-bit word. */ const uint32_t expected_omap = load_u32le(start); if (expected_omap != UINT32_C(0x50414D4F) /* "PAMO" = reverse("OMAP") */) { return false; @@ -1132,7 +1169,7 @@ static bool match_omap( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 4; i < 8; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -1141,7 +1178,7 @@ static bool match_omap( } /* Return parsed chipset. */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_texas_instruments, .series = cpuinfo_arm_chipset_series_texas_instruments_omap, .model = model, @@ -1151,22 +1188,30 @@ static bool match_omap( /** * Compares platform identifier string to known values for Broadcom chipsets. - * If the string matches one of the known values, the function decodes Broadcom chipset from frequency and number of - * cores into \p chipset argument. + * If the string matches one of the known values, the function decodes Broadcom + * chipset from frequency and number of cores into \p chipset argument. * - * @param start - start of the platform identifier (ro.product.board or ro.board.platform) to match. - * @param end - end of the platform identifier (ro.product.board or ro.board.platform) to match. + * @param start - start of the platform identifier (ro.product.board or + * ro.board.platform) to match. + * @param end - end of the platform identifier (ro.product.board or + * ro.board.platform) to match. * @param cores - number of cores in the chipset. - * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. - * @param[out] chipset - location where chipset information will be stored upon a successful match and decoding. + * @param max_cpu_freq_max - maximum of + * /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match and decoding. * - * @returns true if signature matched (even if exact model can't be decoded), false otherwise. + * @returns true if signature matched (even if exact model can't be decoded), + * false otherwise. */ static bool match_and_parse_broadcom( - const char* start, const char* end, uint32_t cores, uint32_t max_cpu_freq_max, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect 4-6 symbols: "java" (4 symbols), "rhea" (4 symbols), "capri" (5 symbols), or "hawaii" (6 symbols) */ + const char* start, + const char* end, + uint32_t cores, + uint32_t max_cpu_freq_max, + struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect 4-6 symbols: "java" (4 symbols), "rhea" (4 symbols), "capri" + * (5 symbols), or "hawaii" (6 symbols) */ const size_t length = end - start; switch (length) { case 4: @@ -1178,12 +1223,14 @@ static bool match_and_parse_broadcom( } /* - * Compare the platform identifier to known values for Broadcom chipsets: + * Compare the platform identifier to known values for Broadcom + * chipsets: * - "rhea" * - "java" * - "capri" * - "hawaii" - * Upon a successful match, decode chipset name from frequency and number of cores. + * Upon a successful match, decode chipset name from frequency and + * number of cores. */ uint32_t model = 0; char suffix = 0; @@ -1219,7 +1266,7 @@ static bool match_and_parse_broadcom( if (length == 6) { /* Check that string equals "hawaii" */ const uint16_t expected_ii = load_u16le(start + 4); - if (expected_ii == UINT16_C(0x6969) /* "ii" */ ) { + if (expected_ii == UINT16_C(0x6969) /* "ii" */) { /* * Detected "hawaii" platform: * - 1 core -> BCM21663 @@ -1258,13 +1305,14 @@ static bool match_and_parse_broadcom( if (model != 0) { /* Chipset was successfully decoded */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_broadcom, .series = cpuinfo_arm_chipset_series_broadcom_bcm, .model = model, - .suffix = { - [0] = suffix, - }, + .suffix = + { + [0] = suffix, + }, }; } return model != 0; @@ -1339,22 +1387,27 @@ static const struct sunxi_map_entry sunxi_map_entries[] = { }; /** - * Tries to match /proc/cpuinfo Hardware string to Allwinner /sun\d+i/ signature. - * If the string matches signature, the function decodes Allwinner chipset from the number in the signature and the - * number of cores, and stores it in \p chipset argument. + * Tries to match /proc/cpuinfo Hardware string to Allwinner /sun\d+i/ + * signature. If the string matches signature, the function decodes Allwinner + * chipset from the number in the signature and the number of cores, and stores + * it in \p chipset argument. * * @param start - start of the /proc/cpuinfo Hardware string to match. * @param end - end of the /proc/cpuinfo Hardware string to match. * @param cores - number of cores in the chipset. - * @param[out] chipset - location where chipset information will be stored upon a successful match and decoding. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match and decoding. * - * @returns true if signature matched (even if exact model can't be decoded), false otherwise. + * @returns true if signature matched (even if exact model can't be decoded), + * false otherwise. */ static bool match_and_parse_sunxi( - const char* start, const char* end, uint32_t cores, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect at least 5 symbols: "sun" (3 symbols) + platform id (1-2 digits) + "i" (1 symbol) */ + const char* start, + const char* end, + uint32_t cores, + struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect at least 5 symbols: "sun" (3 symbols) + platform id (1-2 + * digits) + "i" (1 symbol) */ if (start + 5 > end) { return false; } @@ -1368,10 +1421,11 @@ static bool match_and_parse_sunxi( return false; } - /* Check and parse the first (required) digit of the sunXi platform id */ + /* Check and parse the first (required) digit of the sunXi platform id + */ uint32_t sunxi_platform = 0; { - const uint32_t digit = (uint32_t) (uint8_t) start[3] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[3] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -1382,11 +1436,12 @@ static bool match_and_parse_sunxi( /* Parse optional second digit of the sunXi platform id */ const char* pos = start + 4; { - const uint32_t digit = (uint32_t) (uint8_t) (*pos) - '0'; + const uint32_t digit = (uint32_t)(uint8_t)(*pos) - '0'; if (digit < 10) { sunxi_platform = sunxi_platform * 10 + digit; if (++pos == end) { - /* Expected one more character, final 'i' letter */ + /* Expected one more character, final 'i' letter + */ return false; } } @@ -1397,7 +1452,8 @@ static bool match_and_parse_sunxi( return false; } - /* Compare sunXi platform id and number of cores to tabulated values to decode chipset name */ + /* Compare sunXi platform id and number of cores to tabulated values to + * decode chipset name */ uint32_t model = 0; char suffix = 0; for (size_t i = 0; i < CPUINFO_COUNT_OF(sunxi_map_entries); i++) { @@ -1409,37 +1465,44 @@ static bool match_and_parse_sunxi( } if (model == 0) { - cpuinfo_log_info("unrecognized %"PRIu32"-core Allwinner sun%"PRIu32" platform", cores, sunxi_platform); + cpuinfo_log_info( + "unrecognized %" PRIu32 "-core Allwinner sun%" PRIu32 " platform", cores, sunxi_platform); } /* Create chipset name from decoded data */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_allwinner, .series = cpuinfo_arm_chipset_series_allwinner_a, .model = model, - .suffix = { - [0] = suffix, - }, + .suffix = + { + [0] = suffix, + }, }; return true; } /** * Compares /proc/cpuinfo Hardware string to "WMT" signature. - * If the string matches signature, the function decodes WonderMedia chipset from frequency and number of cores into - * \p chipset argument. + * If the string matches signature, the function decodes WonderMedia chipset + * from frequency and number of cores into \p chipset argument. * * @param start - start of the /proc/cpuinfo Hardware string to match. * @param end - end of the /proc/cpuinfo Hardware string to match. * @param cores - number of cores in the chipset. - * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. - * @param[out] chipset - location where chipset information will be stored upon a successful match and decoding. + * @param max_cpu_freq_max - maximum of + * /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match and decoding. * - * @returns true if signature matched (even if exact model can't be decoded), false otherwise. + * @returns true if signature matched (even if exact model can't be decoded), + * false otherwise. */ static bool match_and_parse_wmt( - const char* start, const char* end, uint32_t cores, uint32_t max_cpu_freq_max, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ + const char* start, + const char* end, + uint32_t cores, + uint32_t max_cpu_freq_max, + struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* Expected 3 symbols: "WMT" */ if (start + 3 != end) { return false; @@ -1478,10 +1541,12 @@ static bool match_and_parse_wmt( } if (model == 0) { - cpuinfo_log_info("unrecognized WonderMedia platform with %"PRIu32" cores at %"PRIu32" KHz", - cores, max_cpu_freq_max); + cpuinfo_log_info( + "unrecognized WonderMedia platform with %" PRIu32 " cores at %" PRIu32 " KHz", + cores, + max_cpu_freq_max); } - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_wondermedia, .series = cpuinfo_arm_chipset_series_wondermedia_wm, .model = model, @@ -1633,26 +1698,30 @@ static const struct huawei_map_entry huawei_platform_map[] = { }; /** - * Tries to match ro.product.board string to Huawei /([A-Z]{3})(\-[A-Z]?L\d{2})$/ signature where \1 is one of the - * known values for Huawei devices, which do not report chipset name elsewhere. - * If the string matches signature, the function decodes chipset (always HiSilicon Kirin for matched devices) from - * the Huawei platform ID in the signature and stores it in \p chipset argument. + * Tries to match ro.product.board string to Huawei + * /([A-Z]{3})(\-[A-Z]?L\d{2})$/ signature where \1 is one of the known values + * for Huawei devices, which do not report chipset name elsewhere. If the string + * matches signature, the function decodes chipset (always HiSilicon Kirin for + * matched devices) from the Huawei platform ID in the signature and stores it + * in \p chipset argument. * * @param start - start of the ro.product.board string to match. * @param end - end of the ro.product.board string to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match and decoding. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match and decoding. * * @returns true if signature matched, false otherwise. */ static bool match_and_parse_huawei( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ + const char* start, + const char* end, + struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* * Expect length of either 3, 7 or 8, exactly: * - 3-letter platform identifier (see huawei_platform_map) * - 3-letter platform identifier + '-' + 'L' + two digits - * - 3-letter platform identifier + '-' + capital letter + 'L' + two digits + * - 3-letter platform identifier + '-' + capital letter + 'L' + two + * digits */ const size_t length = end - start; switch (length) { @@ -1665,8 +1734,9 @@ static bool match_and_parse_huawei( } /* - * Try to find the first three-letter substring in among the tabulated entries for Huawei devices. - * The first three letters are loaded and compared as a little-endian 24-bit word. + * Try to find the first three-letter substring in among the tabulated + * entries for Huawei devices. The first three letters are loaded and + * compared as a little-endian 24-bit word. */ uint32_t model = 0; const uint32_t target_platform_id = load_u24le(start); @@ -1686,7 +1756,8 @@ static bool match_and_parse_huawei( /* * Check that: * - The symbol after platform id is a dash - * - The symbol after it is an uppercase letter. For 7-symbol strings, the symbol is just 'L'. + * - The symbol after it is an uppercase letter. For 7-symbol + * strings, the symbol is just 'L'. */ if (start[3] != '-' || !is_ascii_alphabetic_uppercase(start[4])) { return false; @@ -1699,7 +1770,7 @@ static bool match_and_parse_huawei( } /* All checks succeeded, commit chipset name */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_hisilicon, .series = cpuinfo_arm_chipset_series_hisilicon_kirin, .model = model, @@ -1713,15 +1784,14 @@ static bool match_and_parse_huawei( * * @param start - start of the /proc/cpuinfo Hardware string to match. * @param end - end of the /proc/cpuinfo Hardware string to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_tcc( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect exactly 7 symbols: "tcc" (3 symbols) + 3-digit model number + fixed "x" suffix */ +static bool match_tcc(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect exactly 7 symbols: "tcc" (3 symbols) + 3-digit model number + + * fixed "x" suffix */ if (start + 7 != end) { return false; } @@ -1733,14 +1803,14 @@ static bool match_tcc( /* Load the next 2 bytes as little endian 16-bit word */ const uint16_t expected_cc = load_u16le(start + 1); - if (expected_cc != UINT16_C(0x6363) /* "cc" */ ) { + if (expected_cc != UINT16_C(0x6363) /* "cc" */) { return false; } /* Check and parse 3-digit model number */ uint32_t model = 0; for (uint32_t i = 3; i < 6; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -1754,25 +1824,25 @@ static bool match_tcc( } /* Commit parsed chipset. */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_telechips, .series = cpuinfo_arm_chipset_series_telechips_tcc, .model = model, - .suffix = { - [0] = 'X' - }, + .suffix = {[0] = 'X'}, }; return true; } /* - * Compares ro.board.platform string to Nvidia Tegra signatures ("tegra" and "tegra3") - * This check has effect on how /proc/cpuinfo Hardware string is interpreted. + * Compares ro.board.platform string to Nvidia Tegra signatures ("tegra" and + * "tegra3") This check has effect on how /proc/cpuinfo Hardware string is + * interpreted. * * @param start - start of the ro.board.platform string to check. * @param end - end of the ro.board.platform string to check. * - * @returns true if the string matches an Nvidia Tegra signature, and false otherwise + * @returns true if the string matches an Nvidia Tegra signature, and false + * otherwise */ static bool is_tegra(const char* start, const char* end) { /* Expect 5 ("tegra") or 6 ("tegra3") symbols */ @@ -1794,7 +1864,8 @@ static bool is_tegra(const char* start, const char* end) { return false; } - /* Check if the string is either "tegra" (length = 5) or "tegra3" (length != 5) and last character is '3' */ + /* Check if the string is either "tegra" (length = 5) or "tegra3" + * (length != 5) and last character is '3' */ return (length == 5 || start[5] == '3'); } @@ -1813,13 +1884,11 @@ static const struct special_map_entry special_hardware_map_entries[] = { .series = cpuinfo_arm_chipset_series_hisilicon_k3v, .model = 2, }, - { - /* "hi6620oem" -> HiSilicon Kirin 910T */ - .platform = "hi6620oem", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 910, - .suffix = 'T' - }, + {/* "hi6620oem" -> HiSilicon Kirin 910T */ + .platform = "hi6620oem", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 910, + .suffix = 'T'}, #endif /* CPUINFO_ARCH_ARM */ { /* "hi6250" -> HiSilicon Kirin 650 */ @@ -1906,7 +1975,8 @@ static const struct special_map_entry special_hardware_map_entries[] = { .model = 4470, }, { - /* "Tuna" (Samsung Galaxy Nexus) -> Texas Instruments OMAP4460 */ + /* "Tuna" (Samsung Galaxy Nexus) -> Texas Instruments OMAP4460 + */ .platform = "Tuna", .series = cpuinfo_arm_chipset_series_texas_instruments_omap, .model = 4460, @@ -1954,7 +2024,8 @@ static const struct special_map_entry tegra_hardware_map_entries[] = { .model = 20, }, { - /* "n1" (Samsung Galaxy R / Samsung Captivate Glide) -> Tegra AP20H */ + /* "n1" (Samsung Galaxy R / Samsung Captivate Glide) -> Tegra + AP20H */ .platform = "n1", .series = cpuinfo_arm_chipset_series_nvidia_tegra_ap, .model = 20, @@ -2134,7 +2205,8 @@ static const struct special_map_entry tegra_hardware_map_entries[] = { .model = 20, }, { - /* "tostab12AL" (Toshiba AT300SE "Excite 10 SE") -> Tegra T30L */ + /* "tostab12AL" (Toshiba AT300SE "Excite 10 SE") -> Tegra T30L + */ .platform = "tostab12AL", .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, .model = 30, @@ -2160,7 +2232,8 @@ static const struct special_map_entry tegra_hardware_map_entries[] = { .model = 30, }, { - /* "tostab12BA" (Toshiba AT10-LE-A "Excite Pro") -> Tegra T114 */ + /* "tostab12BA" (Toshiba AT10-LE-A "Excite Pro") -> Tegra T114 + */ .platform = "tostab12BA", .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, .model = 114, @@ -2260,45 +2333,50 @@ static const struct special_map_entry tegra_hardware_map_entries[] = { /* * Decodes chipset name from /proc/cpuinfo Hardware string. - * For some chipsets, the function relies frequency and on number of cores for chipset detection. + * For some chipsets, the function relies frequency and on number of cores for + * chipset detection. * * @param[in] platform - /proc/cpuinfo Hardware string. * @param cores - number of cores in the chipset. - * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. + * @param max_cpu_freq_max - maximum of + * /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. * - * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` vendor - * and series identifiers. + * @returns Decoded chipset name. If chipset could not be decoded, the resulting + * structure would use `unknown` vendor and series identifiers. */ struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_hardware( const char hardware[restrict static CPUINFO_HARDWARE_VALUE_MAX], - uint32_t cores, uint32_t max_cpu_freq_max, bool is_tegra) -{ + uint32_t cores, + uint32_t max_cpu_freq_max, + bool is_tegra) { struct cpuinfo_arm_chipset chipset; const size_t hardware_length = strnlen(hardware, CPUINFO_HARDWARE_VALUE_MAX); const char* hardware_end = hardware + hardware_length; if (is_tegra) { /* - * Nvidia Tegra-specific path: compare /proc/cpuinfo Hardware string to - * tabulated Hardware values for popular chipsets/devices with Tegra chipsets. - * This path is only used when ro.board.platform indicates a Tegra chipset - * (albeit does not indicate which exactly Tegra chipset). + * Nvidia Tegra-specific path: compare /proc/cpuinfo Hardware + * string to tabulated Hardware values for popular + * chipsets/devices with Tegra chipsets. This path is only used + * when ro.board.platform indicates a Tegra chipset (albeit does + * not indicate which exactly Tegra chipset). */ for (size_t i = 0; i < CPUINFO_COUNT_OF(tegra_hardware_map_entries); i++) { if (strncmp(tegra_hardware_map_entries[i].platform, hardware, hardware_length) == 0 && - tegra_hardware_map_entries[i].platform[hardware_length] == 0) - { + tegra_hardware_map_entries[i].platform[hardware_length] == 0) { cpuinfo_log_debug( "found /proc/cpuinfo Hardware string \"%.*s\" in Nvidia Tegra chipset table", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); /* Create chipset name from entry */ - return (struct cpuinfo_arm_chipset) { + return (struct cpuinfo_arm_chipset){ .vendor = chipset_series_vendor[tegra_hardware_map_entries[i].series], - .series = (enum cpuinfo_arm_chipset_series) tegra_hardware_map_entries[i].series, + .series = (enum cpuinfo_arm_chipset_series)tegra_hardware_map_entries[i].series, .model = tegra_hardware_map_entries[i].model, - .suffix = { - [0] = tegra_hardware_map_entries[i].suffix, - }, + .suffix = + { + [0] = tegra_hardware_map_entries[i].suffix, + }, }; } } @@ -2316,51 +2394,63 @@ struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_ha break; default: if (word_start && is_ascii_alphabetic(c)) { - /* Check Qualcomm MSM/APQ signature */ + /* Check Qualcomm MSM/APQ + * signature */ if (match_msm_apq(pos, hardware_end, &chipset)) { cpuinfo_log_debug( "matched Qualcomm MSM/APQ signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } - /* Check SDMxxx (Qualcomm Snapdragon) signature */ + /* Check SDMxxx (Qualcomm + * Snapdragon) signature */ if (match_sdm(pos, hardware_end, &chipset)) { cpuinfo_log_debug( "matched Qualcomm SDM signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } - /* Check SMxxxx (Qualcomm Snapdragon) signature */ + /* Check SMxxxx (Qualcomm + * Snapdragon) signature */ if (match_sm(pos, hardware_end, &chipset)) { cpuinfo_log_debug( "matched Qualcomm SM signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } - /* Check MediaTek MT signature */ + /* Check MediaTek MT signature + */ if (match_mt(pos, hardware_end, true, &chipset)) { cpuinfo_log_debug( "matched MediaTek MT signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } - /* Check HiSilicon Kirin signature */ + /* Check HiSilicon Kirin + * signature */ if (match_kirin(pos, hardware_end, &chipset)) { cpuinfo_log_debug( "matched HiSilicon Kirin signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } - /* Check Rockchip RK signature */ + /* Check Rockchip RK signature + */ if (match_rk(pos, hardware_end, &chipset)) { cpuinfo_log_debug( "matched Rockchip RK signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } } @@ -2373,7 +2463,8 @@ struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_ha if (match_samsung_exynos(hardware, hardware_end, &chipset)) { cpuinfo_log_debug( "matched Samsung Exynos signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } @@ -2381,25 +2472,28 @@ struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_ha if (match_universal(hardware, hardware_end, &chipset)) { cpuinfo_log_debug( "matched UNIVERSAL (Samsung Exynos) signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } - #if CPUINFO_ARCH_ARM - /* Match /SMDK(4410|4x12)$/ */ - if (match_and_parse_smdk(hardware, hardware_end, cores, &chipset)) { - cpuinfo_log_debug( - "matched SMDK (Samsung Exynos) signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); - return chipset; - } - #endif +#if CPUINFO_ARCH_ARM + /* Match /SMDK(4410|4x12)$/ */ + if (match_and_parse_smdk(hardware, hardware_end, cores, &chipset)) { + cpuinfo_log_debug( + "matched SMDK (Samsung Exynos) signature in /proc/cpuinfo Hardware string \"%.*s\"", + (int)hardware_length, + hardware); + return chipset; + } +#endif /* Check Spreadtrum SC signature */ if (match_sc(hardware, hardware_end, &chipset)) { cpuinfo_log_debug( "matched Spreadtrum SC signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } @@ -2408,26 +2502,30 @@ struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_ha if (match_t(hardware, hardware_end, &chipset)) { cpuinfo_log_debug( "matched Unisoc T signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } - #if CPUINFO_ARCH_ARM - /* Check Marvell PXA signature */ - if (match_pxa(hardware, hardware_end, &chipset)) { - cpuinfo_log_debug( - "matched Marvell PXA signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); - return chipset; - } - #endif +#if CPUINFO_ARCH_ARM + /* Check Marvell PXA signature */ + if (match_pxa(hardware, hardware_end, &chipset)) { + cpuinfo_log_debug( + "matched Marvell PXA signature in /proc/cpuinfo Hardware string \"%.*s\"", + (int)hardware_length, + hardware); + return chipset; + } +#endif - /* Match /sun\d+i/ signature and map to Allwinner chipset name */ + /* Match /sun\d+i/ signature and map to Allwinner chipset name + */ if (match_and_parse_sunxi(hardware, hardware_end, cores, &chipset)) { cpuinfo_log_debug( "matched sunxi (Allwinner Ax) signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } @@ -2435,781 +2533,828 @@ struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_ha if (match_bcm(hardware, hardware_end, &chipset)) { cpuinfo_log_debug( "matched Broadcom BCM signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } - #if CPUINFO_ARCH_ARM - /* Check Texas Instruments OMAP signature */ - if (match_omap(hardware, hardware_end, &chipset)) { - cpuinfo_log_debug( - "matched Texas Instruments OMAP signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); - return chipset; - } +#if CPUINFO_ARCH_ARM + /* Check Texas Instruments OMAP signature */ + if (match_omap(hardware, hardware_end, &chipset)) { + cpuinfo_log_debug( + "matched Texas Instruments OMAP signature in /proc/cpuinfo Hardware string \"%.*s\"", + (int)hardware_length, + hardware); + return chipset; + } - /* Check WonderMedia WMT signature and decode chipset from frequency and number of cores */ - if (match_and_parse_wmt(hardware, hardware_end, cores, max_cpu_freq_max, &chipset)) { - cpuinfo_log_debug( - "matched WonderMedia WMT signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); - return chipset; - } + /* Check WonderMedia WMT signature and decode chipset from + * frequency and number of cores */ + if (match_and_parse_wmt(hardware, hardware_end, cores, max_cpu_freq_max, &chipset)) { + cpuinfo_log_debug( + "matched WonderMedia WMT signature in /proc/cpuinfo Hardware string \"%.*s\"", + (int)hardware_length, + hardware); + return chipset; + } - #endif +#endif /* Check Telechips TCC signature */ if (match_tcc(hardware, hardware_end, &chipset)) { cpuinfo_log_debug( "matched Telechips TCC signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } - /* Compare to tabulated Hardware values for popular chipsets/devices which can't be otherwise detected */ + /* Compare to tabulated Hardware values for popular + * chipsets/devices which can't be otherwise detected */ for (size_t i = 0; i < CPUINFO_COUNT_OF(special_hardware_map_entries); i++) { if (strncmp(special_hardware_map_entries[i].platform, hardware, hardware_length) == 0 && - special_hardware_map_entries[i].platform[hardware_length] == 0) - { + special_hardware_map_entries[i].platform[hardware_length] == 0) { cpuinfo_log_debug( "found /proc/cpuinfo Hardware string \"%.*s\" in special chipset table", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); /* Create chipset name from entry */ - return (struct cpuinfo_arm_chipset) { + return (struct cpuinfo_arm_chipset){ .vendor = chipset_series_vendor[special_hardware_map_entries[i].series], - .series = (enum cpuinfo_arm_chipset_series) special_hardware_map_entries[i].series, + .series = + (enum cpuinfo_arm_chipset_series)special_hardware_map_entries[i].series, .model = special_hardware_map_entries[i].model, - .suffix = { - [0] = special_hardware_map_entries[i].suffix, - }, + .suffix = + { + [0] = special_hardware_map_entries[i].suffix, + }, }; } } } - return (struct cpuinfo_arm_chipset) { + return (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_unknown, .series = cpuinfo_arm_chipset_series_unknown, }; } #ifdef __ANDROID__ - static const struct special_map_entry special_board_map_entries[] = { - { - /* "hi6250" -> HiSilicon Kirin 650 */ - .platform = "hi6250", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 650, - }, - { - /* "hi6210sft" -> HiSilicon Kirin 620 */ - .platform = "hi6210sft", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 620, - }, +static const struct special_map_entry special_board_map_entries[] = { + { + /* "hi6250" -> HiSilicon Kirin 650 */ + .platform = "hi6250", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 650, + }, + { + /* "hi6210sft" -> HiSilicon Kirin 620 */ + .platform = "hi6210sft", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 620, + }, #if CPUINFO_ARCH_ARM - { - /* "hi3630" -> HiSilicon Kirin 920 */ - .platform = "hi3630", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 920, - }, + { + /* "hi3630" -> HiSilicon Kirin 920 */ + .platform = "hi3630", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 920, + }, #endif /* CPUINFO_ARCH_ARM */ - { - /* "hi3635" -> HiSilicon Kirin 930 */ - .platform = "hi3635", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 930, - }, - { - /* "hi3650" -> HiSilicon Kirin 950 */ - .platform = "hi3650", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 950, - }, - { - /* "hi3660" -> HiSilicon Kirin 960 */ - .platform = "hi3660", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 960, - }, + { + /* "hi3635" -> HiSilicon Kirin 930 */ + .platform = "hi3635", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 930, + }, + { + /* "hi3650" -> HiSilicon Kirin 950 */ + .platform = "hi3650", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 950, + }, + { + /* "hi3660" -> HiSilicon Kirin 960 */ + .platform = "hi3660", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 960, + }, #if CPUINFO_ARCH_ARM - { - /* "mp523x" -> Renesas MP5232 */ - .platform = "mp523x", - .series = cpuinfo_arm_chipset_series_renesas_mp, - .model = 5232, - }, + { + /* "mp523x" -> Renesas MP5232 */ + .platform = "mp523x", + .series = cpuinfo_arm_chipset_series_renesas_mp, + .model = 5232, + }, #endif /* CPUINFO_ARCH_ARM */ - { - /* "BEETHOVEN" (Huawei MadiaPad M3) -> HiSilicon Kirin 950 */ - .platform = "BEETHOVEN", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 950, - }, + { + /* "BEETHOVEN" (Huawei MadiaPad M3) -> HiSilicon Kirin 950 */ + .platform = "BEETHOVEN", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 950, + }, #if CPUINFO_ARCH_ARM - { - /* "hws7701u" (Huawei MediaPad 7 Youth) -> Rockchip RK3168 */ - .platform = "hws7701u", - .series = cpuinfo_arm_chipset_series_rockchip_rk, - .model = 3168, - }, - { - /* "g2mv" (LG G2 mini LTE) -> Nvidia Tegra SL460N */ - .platform = "g2mv", - .series = cpuinfo_arm_chipset_series_nvidia_tegra_sl, - .model = 460, - .suffix = 'N', - }, - { - /* "K00F" (Asus MeMO Pad 10) -> Rockchip RK3188 */ - .platform = "K00F", - .series = cpuinfo_arm_chipset_series_rockchip_rk, - .model = 3188, - }, - { - /* "T7H" (HP Slate 7) -> Rockchip RK3066 */ - .platform = "T7H", - .series = cpuinfo_arm_chipset_series_rockchip_rk, - .model = 3066, - }, - { - /* "tuna" (Samsung Galaxy Nexus) -> Texas Instruments OMAP4460 */ - .platform = "tuna", - .series = cpuinfo_arm_chipset_series_texas_instruments_omap, - .model = 4460, - }, - { - /* "grouper" (Asus Nexus 7 2012) -> Nvidia Tegra T30L */ - .platform = "grouper", - .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, - .model = 30, - .suffix = 'L', - }, + { + /* "hws7701u" (Huawei MediaPad 7 Youth) -> Rockchip RK3168 */ + .platform = "hws7701u", + .series = cpuinfo_arm_chipset_series_rockchip_rk, + .model = 3168, + }, + { + /* "g2mv" (LG G2 mini LTE) -> Nvidia Tegra SL460N */ + .platform = "g2mv", + .series = cpuinfo_arm_chipset_series_nvidia_tegra_sl, + .model = 460, + .suffix = 'N', + }, + { + /* "K00F" (Asus MeMO Pad 10) -> Rockchip RK3188 */ + .platform = "K00F", + .series = cpuinfo_arm_chipset_series_rockchip_rk, + .model = 3188, + }, + { + /* "T7H" (HP Slate 7) -> Rockchip RK3066 */ + .platform = "T7H", + .series = cpuinfo_arm_chipset_series_rockchip_rk, + .model = 3066, + }, + { + /* "tuna" (Samsung Galaxy Nexus) -> Texas Instruments OMAP4460 + */ + .platform = "tuna", + .series = cpuinfo_arm_chipset_series_texas_instruments_omap, + .model = 4460, + }, + { + /* "grouper" (Asus Nexus 7 2012) -> Nvidia Tegra T30L */ + .platform = "grouper", + .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, + .model = 30, + .suffix = 'L', + }, #endif /* CPUINFO_ARCH_ARM */ - { - /* "flounder" (HTC Nexus 9) -> Nvidia Tegra T132 */ - .platform = "flounder", - .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, - .model = 132, - }, - { - /* "dragon" (Google Pixel C) -> Nvidia Tegra T210 */ - .platform = "dragon", - .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, - .model = 210, - }, - { - /* "sailfish" (Google Pixel) -> Qualcomm MSM8996PRO */ - .platform = "sailfish", - .series = cpuinfo_arm_chipset_series_qualcomm_msm, - .model = 8996, - .suffix = 'P', - }, - { - /* "marlin" (Google Pixel XL) -> Qualcomm MSM8996PRO */ - .platform = "marlin", - .series = cpuinfo_arm_chipset_series_qualcomm_msm, - .model = 8996, - .suffix = 'P', - }, - }; + { + /* "flounder" (HTC Nexus 9) -> Nvidia Tegra T132 */ + .platform = "flounder", + .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, + .model = 132, + }, + { + /* "dragon" (Google Pixel C) -> Nvidia Tegra T210 */ + .platform = "dragon", + .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, + .model = 210, + }, + { + /* "sailfish" (Google Pixel) -> Qualcomm MSM8996PRO */ + .platform = "sailfish", + .series = cpuinfo_arm_chipset_series_qualcomm_msm, + .model = 8996, + .suffix = 'P', + }, + { + /* "marlin" (Google Pixel XL) -> Qualcomm MSM8996PRO */ + .platform = "marlin", + .series = cpuinfo_arm_chipset_series_qualcomm_msm, + .model = 8996, + .suffix = 'P', + }, +}; + +/* + * Decodes chipset name from ro.product.board Android system property. + * For some chipsets, the function relies frequency and on number of cores for + * chipset detection. + * + * @param[in] platform - ro.product.board value. + * @param cores - number of cores in the chipset. + * @param max_cpu_freq_max - maximum of + * /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. + * + * @returns Decoded chipset name. If chipset could not be decoded, the resulting + * structure would use `unknown` vendor and series identifiers. + */ +struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_product_board( + const char ro_product_board[restrict static CPUINFO_BUILD_PROP_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max) { + struct cpuinfo_arm_chipset chipset; + const char* board = ro_product_board; + const size_t board_length = strnlen(ro_product_board, CPUINFO_BUILD_PROP_VALUE_MAX); + const char* board_end = ro_product_board + board_length; + + /* Check Qualcomm MSM/APQ signature */ + if (match_msm_apq(board, board_end, &chipset)) { + cpuinfo_log_debug( + "matched Qualcomm MSM/APQ signature in ro.product.board string \"%.*s\"", + (int)board_length, + board); + return chipset; + } + + /* Check universaXXXX (Samsung Exynos) signature */ + if (match_universal(board, board_end, &chipset)) { + cpuinfo_log_debug( + "matched UNIVERSAL (Samsung Exynos) signature in ro.product.board string \"%.*s\"", + (int)board_length, + board); + return chipset; + } + +#if CPUINFO_ARCH_ARM + /* Check SMDK (Samsung Exynos) signature */ + if (match_and_parse_smdk(board, board_end, cores, &chipset)) { + cpuinfo_log_debug( + "matched SMDK (Samsung Exynos) signature in ro.product.board string \"%.*s\"", + (int)board_length, + board); + return chipset; + } +#endif + + /* Check MediaTek MT signature */ + if (match_mt(board, board_end, true, &chipset)) { + cpuinfo_log_debug( + "matched MediaTek MT signature in ro.product.board string \"%.*s\"", (int)board_length, board); + return chipset; + } + + /* Check Spreadtrum SC signature */ + if (match_sc(board, board_end, &chipset)) { + cpuinfo_log_debug( + "matched Spreadtrum SC signature in ro.product.board string \"%.*s\"", + (int)board_length, + board); + return chipset; + } + +#if CPUINFO_ARCH_ARM + /* Check Marvell PXA signature */ + if (match_pxa(board, board_end, &chipset)) { + cpuinfo_log_debug( + "matched Marvell PXA signature in ro.product.board string \"%.*s\"", (int)board_length, board); + return chipset; + } + + /* Check Leadcore LCxxxx signature */ + if (match_lc(board, board_end, &chipset)) { + cpuinfo_log_debug( + "matched Leadcore LC signature in ro.product.board string \"%.*s\"", (int)board_length, board); + return chipset; + } /* - * Decodes chipset name from ro.product.board Android system property. - * For some chipsets, the function relies frequency and on number of cores for chipset detection. - * - * @param[in] platform - ro.product.board value. - * @param cores - number of cores in the chipset. - * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. - * - * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` vendor - * and series identifiers. + * Compare to tabulated ro.product.board values for Broadcom chipsets + * and decode chipset from frequency and number of cores. */ - struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_product_board( - const char ro_product_board[restrict static CPUINFO_BUILD_PROP_VALUE_MAX], - uint32_t cores, uint32_t max_cpu_freq_max) - { - struct cpuinfo_arm_chipset chipset; - const char* board = ro_product_board; - const size_t board_length = strnlen(ro_product_board, CPUINFO_BUILD_PROP_VALUE_MAX); - const char* board_end = ro_product_board + board_length; + if (match_and_parse_broadcom(board, board_end, cores, max_cpu_freq_max, &chipset)) { + cpuinfo_log_debug( + "found ro.product.board string \"%.*s\" in Broadcom chipset table", (int)board_length, board); + return chipset; + } +#endif - /* Check Qualcomm MSM/APQ signature */ - if (match_msm_apq(board, board_end, &chipset)) { + /* Compare to tabulated ro.product.board values for Huawei devices which + * don't report chipset elsewhere */ + if (match_and_parse_huawei(board, board_end, &chipset)) { + cpuinfo_log_debug( + "found ro.product.board string \"%.*s\" in Huawei chipset table", (int)board_length, board); + return chipset; + } + + /* Compare to tabulated ro.product.board values for popular + * chipsets/devices which can't be otherwise detected */ + for (size_t i = 0; i < CPUINFO_COUNT_OF(special_board_map_entries); i++) { + if (strncmp(special_board_map_entries[i].platform, board, board_length) == 0 && + special_board_map_entries[i].platform[board_length] == 0) { cpuinfo_log_debug( - "matched Qualcomm MSM/APQ signature in ro.product.board string \"%.*s\"", (int) board_length, board); - return chipset; - } - - /* Check universaXXXX (Samsung Exynos) signature */ - if (match_universal(board, board_end, &chipset)) { - cpuinfo_log_debug( - "matched UNIVERSAL (Samsung Exynos) signature in ro.product.board string \"%.*s\"", - (int) board_length, board); - return chipset; - } - - #if CPUINFO_ARCH_ARM - /* Check SMDK (Samsung Exynos) signature */ - if (match_and_parse_smdk(board, board_end, cores, &chipset)) { - cpuinfo_log_debug( - "matched SMDK (Samsung Exynos) signature in ro.product.board string \"%.*s\"", - (int) board_length, board); - return chipset; - } - #endif - - /* Check MediaTek MT signature */ - if (match_mt(board, board_end, true, &chipset)) { - cpuinfo_log_debug( - "matched MediaTek MT signature in ro.product.board string \"%.*s\"", - (int) board_length, board); - return chipset; - } - - /* Check Spreadtrum SC signature */ - if (match_sc(board, board_end, &chipset)) { - cpuinfo_log_debug( - "matched Spreadtrum SC signature in ro.product.board string \"%.*s\"", - (int) board_length, board); - return chipset; - } - - #if CPUINFO_ARCH_ARM - /* Check Marvell PXA signature */ - if (match_pxa(board, board_end, &chipset)) { - cpuinfo_log_debug( - "matched Marvell PXA signature in ro.product.board string \"%.*s\"", - (int) board_length, board); - return chipset; - } - - /* Check Leadcore LCxxxx signature */ - if (match_lc(board, board_end, &chipset)) { - cpuinfo_log_debug( - "matched Leadcore LC signature in ro.product.board string \"%.*s\"", - (int) board_length, board); - return chipset; - } - - /* - * Compare to tabulated ro.product.board values for Broadcom chipsets and decode chipset from frequency and - * number of cores. - */ - if (match_and_parse_broadcom(board, board_end, cores, max_cpu_freq_max, &chipset)) { - cpuinfo_log_debug( - "found ro.product.board string \"%.*s\" in Broadcom chipset table", - (int) board_length, board); - return chipset; - } - #endif - - /* Compare to tabulated ro.product.board values for Huawei devices which don't report chipset elsewhere */ - if (match_and_parse_huawei(board, board_end, &chipset)) { - cpuinfo_log_debug( - "found ro.product.board string \"%.*s\" in Huawei chipset table", - (int) board_length, board); - return chipset; - } - - /* Compare to tabulated ro.product.board values for popular chipsets/devices which can't be otherwise detected */ - for (size_t i = 0; i < CPUINFO_COUNT_OF(special_board_map_entries); i++) { - if (strncmp(special_board_map_entries[i].platform, board, board_length) == 0 && - special_board_map_entries[i].platform[board_length] == 0) - { - cpuinfo_log_debug( - "found ro.product.board string \"%.*s\" in special chipset table", - (int) board_length, board); - /* Create chipset name from entry */ - return (struct cpuinfo_arm_chipset) { - .vendor = chipset_series_vendor[special_board_map_entries[i].series], - .series = (enum cpuinfo_arm_chipset_series) special_board_map_entries[i].series, - .model = special_board_map_entries[i].model, - .suffix = { + "found ro.product.board string \"%.*s\" in special chipset table", + (int)board_length, + board); + /* Create chipset name from entry */ + return (struct cpuinfo_arm_chipset){ + .vendor = chipset_series_vendor[special_board_map_entries[i].series], + .series = (enum cpuinfo_arm_chipset_series)special_board_map_entries[i].series, + .model = special_board_map_entries[i].model, + .suffix = + { [0] = special_board_map_entries[i].suffix, - /* The suffix of MSM8996PRO is truncated at the first letter, reconstruct it here. */ + /* The suffix of MSM8996PRO is + truncated at the first + letter, reconstruct it here. + */ [1] = special_board_map_entries[i].suffix == 'P' ? 'R' : 0, [2] = special_board_map_entries[i].suffix == 'P' ? 'O' : 0, }, - }; - } + }; } - - return (struct cpuinfo_arm_chipset) { - .vendor = cpuinfo_arm_chipset_vendor_unknown, - .series = cpuinfo_arm_chipset_series_unknown, - }; } - struct amlogic_map_entry { - char ro_board_platform[6]; - uint16_t model; - uint8_t series; - char suffix[3]; + return (struct cpuinfo_arm_chipset){ + .vendor = cpuinfo_arm_chipset_vendor_unknown, + .series = cpuinfo_arm_chipset_series_unknown, }; +} - static const struct amlogic_map_entry amlogic_map_entries[] = { -#if CPUINFO_ARCH_ARM - { - /* "meson3" -> Amlogic AML8726-M */ - .ro_board_platform = "meson3", - .series = cpuinfo_arm_chipset_series_amlogic_aml, - .model = 8726, - .suffix = "-M", - }, - { - /* "meson6" -> Amlogic AML8726-MX */ - .ro_board_platform = "meson6", - .series = cpuinfo_arm_chipset_series_amlogic_aml, - .model = 8726, - .suffix = "-MX", - }, - { - /* "meson8" -> Amlogic S805 */ - .ro_board_platform = "meson8", - .series = cpuinfo_arm_chipset_series_amlogic_s, - .model = 805, - }, -#endif /* CPUINFO_ARCH_ARM */ - { - /* "gxbaby" -> Amlogic S905 */ - .ro_board_platform = "gxbaby", - .series = cpuinfo_arm_chipset_series_amlogic_s, - .model = 905, - }, - { - /* "gxl" -> Amlogic S905X */ - .ro_board_platform = "gxl", - .series = cpuinfo_arm_chipset_series_amlogic_s, - .model = 905, - .suffix = "X", - }, - { - /* "gxm" -> Amlogic S912 */ - .ro_board_platform = "gxm", - .series = cpuinfo_arm_chipset_series_amlogic_s, - .model = 912, - }, - }; +struct amlogic_map_entry { + char ro_board_platform[6]; + uint16_t model; + uint8_t series; + char suffix[3]; +}; - static const struct special_map_entry special_platform_map_entries[] = { +static const struct amlogic_map_entry amlogic_map_entries[] = { #if CPUINFO_ARCH_ARM - { - /* "hi6620oem" -> HiSilicon Kirin 910T */ - .platform = "hi6620oem", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 910, - .suffix = 'T', - }, + { + /* "meson3" -> Amlogic AML8726-M */ + .ro_board_platform = "meson3", + .series = cpuinfo_arm_chipset_series_amlogic_aml, + .model = 8726, + .suffix = "-M", + }, + { + /* "meson6" -> Amlogic AML8726-MX */ + .ro_board_platform = "meson6", + .series = cpuinfo_arm_chipset_series_amlogic_aml, + .model = 8726, + .suffix = "-MX", + }, + { + /* "meson8" -> Amlogic S805 */ + .ro_board_platform = "meson8", + .series = cpuinfo_arm_chipset_series_amlogic_s, + .model = 805, + }, #endif /* CPUINFO_ARCH_ARM */ - { - /* "hi6250" -> HiSilicon Kirin 650 */ - .platform = "hi6250", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 650, - }, - { - /* "hi6210sft" -> HiSilicon Kirin 620 */ - .platform = "hi6210sft", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 620, - }, + { + /* "gxbaby" -> Amlogic S905 */ + .ro_board_platform = "gxbaby", + .series = cpuinfo_arm_chipset_series_amlogic_s, + .model = 905, + }, + { + /* "gxl" -> Amlogic S905X */ + .ro_board_platform = "gxl", + .series = cpuinfo_arm_chipset_series_amlogic_s, + .model = 905, + .suffix = "X", + }, + { + /* "gxm" -> Amlogic S912 */ + .ro_board_platform = "gxm", + .series = cpuinfo_arm_chipset_series_amlogic_s, + .model = 912, + }, +}; + +static const struct special_map_entry special_platform_map_entries[] = { #if CPUINFO_ARCH_ARM - { - /* "hi3630" -> HiSilicon Kirin 920 */ - .platform = "hi3630", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 920, - }, + { + /* "hi6620oem" -> HiSilicon Kirin 910T */ + .platform = "hi6620oem", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 910, + .suffix = 'T', + }, #endif /* CPUINFO_ARCH_ARM */ - { - /* "hi3635" -> HiSilicon Kirin 930 */ - .platform = "hi3635", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 930, - }, - { - /* "hi3650" -> HiSilicon Kirin 950 */ - .platform = "hi3650", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 950, - }, - { - /* "hi3660" -> HiSilicon Kirin 960 */ - .platform = "hi3660", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 960, - }, + { + /* "hi6250" -> HiSilicon Kirin 650 */ + .platform = "hi6250", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 650, + }, + { + /* "hi6210sft" -> HiSilicon Kirin 620 */ + .platform = "hi6210sft", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 620, + }, #if CPUINFO_ARCH_ARM - { - /* "k3v2oem1" -> HiSilicon K3V2 */ - .platform = "k3v2oem1", - .series = cpuinfo_arm_chipset_series_hisilicon_k3v, - .model = 2, - }, - { - /* "k3v200" -> HiSilicon K3V2 */ - .platform = "k3v200", - .series = cpuinfo_arm_chipset_series_hisilicon_k3v, - .model = 2, - }, - { - /* "montblanc" -> NovaThor U8500 */ - .platform = "montblanc", - .series = cpuinfo_arm_chipset_series_novathor_u, - .model = 8500, - }, + { + /* "hi3630" -> HiSilicon Kirin 920 */ + .platform = "hi3630", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 920, + }, #endif /* CPUINFO_ARCH_ARM */ - { - /* "song" -> Pinecone Surge S1 */ - .platform = "song", - .series = cpuinfo_arm_chipset_series_pinecone_surge_s, - .model = 1, - }, + { + /* "hi3635" -> HiSilicon Kirin 930 */ + .platform = "hi3635", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 930, + }, + { + /* "hi3650" -> HiSilicon Kirin 950 */ + .platform = "hi3650", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 950, + }, + { + /* "hi3660" -> HiSilicon Kirin 960 */ + .platform = "hi3660", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 960, + }, #if CPUINFO_ARCH_ARM - { - /* "rk322x" -> RockChip RK3229 */ - .platform = "rk322x", - .series = cpuinfo_arm_chipset_series_rockchip_rk, - .model = 3229, - }, + { + /* "k3v2oem1" -> HiSilicon K3V2 */ + .platform = "k3v2oem1", + .series = cpuinfo_arm_chipset_series_hisilicon_k3v, + .model = 2, + }, + { + /* "k3v200" -> HiSilicon K3V2 */ + .platform = "k3v200", + .series = cpuinfo_arm_chipset_series_hisilicon_k3v, + .model = 2, + }, + { + /* "montblanc" -> NovaThor U8500 */ + .platform = "montblanc", + .series = cpuinfo_arm_chipset_series_novathor_u, + .model = 8500, + }, #endif /* CPUINFO_ARCH_ARM */ - { - /* "tegra132" -> Nvidia Tegra T132 */ - .platform = "tegra132", - .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, - .model = 132, - }, - { - /* "tegra210_dragon" -> Nvidia Tegra T210 */ - .platform = "tegra210_dragon", - .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, - .model = 210, - }, + { + /* "song" -> Pinecone Surge S1 */ + .platform = "song", + .series = cpuinfo_arm_chipset_series_pinecone_surge_s, + .model = 1, + }, #if CPUINFO_ARCH_ARM - { - /* "tegra4" -> Nvidia Tegra T114 */ - .platform = "tegra4", - .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, - .model = 114, - }, - { - /* "s5pc110" -> Samsung Exynos 3110 */ - .platform = "s5pc110", - .series = cpuinfo_arm_chipset_series_samsung_exynos, - .model = 3110, - }, + { + /* "rk322x" -> RockChip RK3229 */ + .platform = "rk322x", + .series = cpuinfo_arm_chipset_series_rockchip_rk, + .model = 3229, + }, #endif /* CPUINFO_ARCH_ARM */ - }; + { + /* "tegra132" -> Nvidia Tegra T132 */ + .platform = "tegra132", + .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, + .model = 132, + }, + { + /* "tegra210_dragon" -> Nvidia Tegra T210 */ + .platform = "tegra210_dragon", + .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, + .model = 210, + }, +#if CPUINFO_ARCH_ARM + { + /* "tegra4" -> Nvidia Tegra T114 */ + .platform = "tegra4", + .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, + .model = 114, + }, + { + /* "s5pc110" -> Samsung Exynos 3110 */ + .platform = "s5pc110", + .series = cpuinfo_arm_chipset_series_samsung_exynos, + .model = 3110, + }, +#endif /* CPUINFO_ARCH_ARM */ +}; + +/* + * Decodes chipset name from ro.board.platform Android system property. + * For some chipsets, the function relies frequency and on number of cores for + * chipset detection. + * + * @param[in] platform - ro.board.platform value. + * @param cores - number of cores in the chipset. + * @param max_cpu_freq_max - maximum of + * /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. + * + * @returns Decoded chipset name. If chipset could not be decoded, the resulting + * structure would use `unknown` vendor and series identifiers. + */ +struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_board_platform( + const char platform[restrict static CPUINFO_BUILD_PROP_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max) { + struct cpuinfo_arm_chipset chipset; + const size_t platform_length = strnlen(platform, CPUINFO_BUILD_PROP_VALUE_MAX); + const char* platform_end = platform + platform_length; + + /* Check Qualcomm MSM/APQ signature */ + if (match_msm_apq(platform, platform_end, &chipset)) { + cpuinfo_log_debug( + "matched Qualcomm MSM/APQ signature in ro.board.platform string \"%.*s\"", + (int)platform_length, + platform); + return chipset; + } + + /* Check exynosXXXX (Samsung Exynos) signature */ + if (match_exynos(platform, platform_end, &chipset)) { + cpuinfo_log_debug( + "matched exynosXXXX (Samsung Exynos) signature in ro.board.platform string \"%.*s\"", + (int)platform_length, + platform); + return chipset; + } + + /* Check MediaTek MT signature */ + if (match_mt(platform, platform_end, true, &chipset)) { + cpuinfo_log_debug( + "matched MediaTek MT signature in ro.board.platform string \"%.*s\"", + (int)platform_length, + platform); + return chipset; + } + + /* Check HiSilicon Kirin signature */ + if (match_kirin(platform, platform_end, &chipset)) { + cpuinfo_log_debug( + "matched HiSilicon Kirin signature in ro.board.platform string \"%.*s\"", + (int)platform_length, + platform); + return chipset; + } + + /* Check Spreadtrum SC signature */ + if (match_sc(platform, platform_end, &chipset)) { + cpuinfo_log_debug( + "matched Spreadtrum SC signature in ro.board.platform string \"%.*s\"", + (int)platform_length, + platform); + return chipset; + } + + /* Check Rockchip RK signature */ + if (match_rk(platform, platform_end, &chipset)) { + cpuinfo_log_debug( + "matched Rockchip RK signature in ro.board.platform string \"%.*s\"", + (int)platform_length, + platform); + return chipset; + } + +#if CPUINFO_ARCH_ARM + /* Check Leadcore LCxxxx signature */ + if (match_lc(platform, platform_end, &chipset)) { + cpuinfo_log_debug( + "matched Leadcore LC signature in ro.board.platform string \"%.*s\"", + (int)platform_length, + platform); + return chipset; + } +#endif + + /* Compare to tabulated ro.board.platform values for Huawei devices + * which don't report chipset elsewhere */ + if (match_and_parse_huawei(platform, platform_end, &chipset)) { + cpuinfo_log_debug( + "found ro.board.platform string \"%.*s\" in Huawei chipset table", + (int)platform_length, + platform); + return chipset; + } + +#if CPUINFO_ARCH_ARM + /* + * Compare to known ro.board.platform values for Broadcom devices and + * detect chipset from frequency and number of cores + */ + if (match_and_parse_broadcom(platform, platform_end, cores, max_cpu_freq_max, &chipset)) { + cpuinfo_log_debug( + "found ro.board.platform string \"%.*s\" in Broadcom chipset table", + (int)platform_length, + platform); + return chipset; + } /* - * Decodes chipset name from ro.board.platform Android system property. - * For some chipsets, the function relies frequency and on number of cores for chipset detection. - * - * @param[in] platform - ro.board.platform value. - * @param cores - number of cores in the chipset. - * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. - * - * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` vendor - * and series identifiers. + * Compare to ro.board.platform value ("omap4") for OMAP4xxx chipsets. + * Upon successful match, detect OMAP4430 from frequency and number of + * cores. */ - struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_board_platform( - const char platform[restrict static CPUINFO_BUILD_PROP_VALUE_MAX], - uint32_t cores, uint32_t max_cpu_freq_max) - { - struct cpuinfo_arm_chipset chipset; - const size_t platform_length = strnlen(platform, CPUINFO_BUILD_PROP_VALUE_MAX); - const char* platform_end = platform + platform_length; + if (platform_length == 5 && cores == 2 && max_cpu_freq_max == 1008000 && memcmp(platform, "omap4", 5) == 0) { + cpuinfo_log_debug( + "matched Texas Instruments OMAP4 signature in ro.board.platform string \"%.*s\"", + (int)platform_length, + platform); - /* Check Qualcomm MSM/APQ signature */ - if (match_msm_apq(platform, platform_end, &chipset)) { - cpuinfo_log_debug( - "matched Qualcomm MSM/APQ signature in ro.board.platform string \"%.*s\"", - (int) platform_length, platform); - return chipset; - } + return (struct cpuinfo_arm_chipset){ + .vendor = cpuinfo_arm_chipset_vendor_texas_instruments, + .series = cpuinfo_arm_chipset_series_texas_instruments_omap, + .model = 4430, + }; + } +#endif - /* Check exynosXXXX (Samsung Exynos) signature */ - if (match_exynos(platform, platform_end, &chipset)) { - cpuinfo_log_debug( - "matched exynosXXXX (Samsung Exynos) signature in ro.board.platform string \"%.*s\"", - (int) platform_length, platform); - return chipset; - } - - /* Check MediaTek MT signature */ - if (match_mt(platform, platform_end, true, &chipset)) { - cpuinfo_log_debug( - "matched MediaTek MT signature in ro.board.platform string \"%.*s\"", (int) platform_length, platform); - return chipset; - } - - /* Check HiSilicon Kirin signature */ - if (match_kirin(platform, platform_end, &chipset)) { - cpuinfo_log_debug( - "matched HiSilicon Kirin signature in ro.board.platform string \"%.*s\"", (int) platform_length, platform); - return chipset; - } - - /* Check Spreadtrum SC signature */ - if (match_sc(platform, platform_end, &chipset)) { - cpuinfo_log_debug( - "matched Spreadtrum SC signature in ro.board.platform string \"%.*s\"", (int) platform_length, platform); - return chipset; - } - - /* Check Rockchip RK signature */ - if (match_rk(platform, platform_end, &chipset)) { - cpuinfo_log_debug( - "matched Rockchip RK signature in ro.board.platform string \"%.*s\"", (int) platform_length, platform); - return chipset; - } - - #if CPUINFO_ARCH_ARM - /* Check Leadcore LCxxxx signature */ - if (match_lc(platform, platform_end, &chipset)) { + /* + * Compare to tabulated ro.board.platform values for Amlogic + * chipsets/devices which can't be otherwise detected. The tabulated + * Amlogic ro.board.platform values have not more than 6 characters. + */ + if (platform_length <= 6) { + for (size_t i = 0; i < CPUINFO_COUNT_OF(amlogic_map_entries); i++) { + if (strncmp(amlogic_map_entries[i].ro_board_platform, platform, 6) == 0) { cpuinfo_log_debug( - "matched Leadcore LC signature in ro.board.platform string \"%.*s\"", (int) platform_length, platform); - return chipset; - } - #endif - - /* Compare to tabulated ro.board.platform values for Huawei devices which don't report chipset elsewhere */ - if (match_and_parse_huawei(platform, platform_end, &chipset)) { - cpuinfo_log_debug( - "found ro.board.platform string \"%.*s\" in Huawei chipset table", - (int) platform_length, platform); - return chipset; - } - - #if CPUINFO_ARCH_ARM - /* - * Compare to known ro.board.platform values for Broadcom devices and - * detect chipset from frequency and number of cores - */ - if (match_and_parse_broadcom(platform, platform_end, cores, max_cpu_freq_max, &chipset)) { - cpuinfo_log_debug( - "found ro.board.platform string \"%.*s\" in Broadcom chipset table", - (int) platform_length, platform); - return chipset; - } - - /* - * Compare to ro.board.platform value ("omap4") for OMAP4xxx chipsets. - * Upon successful match, detect OMAP4430 from frequency and number of cores. - */ - if (platform_length == 5 && cores == 2 && max_cpu_freq_max == 1008000 && memcmp(platform, "omap4", 5) == 0) { - cpuinfo_log_debug( - "matched Texas Instruments OMAP4 signature in ro.board.platform string \"%.*s\"", - (int) platform_length, platform); - - return (struct cpuinfo_arm_chipset) { - .vendor = cpuinfo_arm_chipset_vendor_texas_instruments, - .series = cpuinfo_arm_chipset_series_texas_instruments_omap, - .model = 4430, - }; - } - #endif - - /* - * Compare to tabulated ro.board.platform values for Amlogic chipsets/devices which can't be otherwise detected. - * The tabulated Amlogic ro.board.platform values have not more than 6 characters. - */ - if (platform_length <= 6) { - for (size_t i = 0; i < CPUINFO_COUNT_OF(amlogic_map_entries); i++) { - if (strncmp(amlogic_map_entries[i].ro_board_platform, platform, 6) == 0) { - cpuinfo_log_debug( - "found ro.board.platform string \"%.*s\" in Amlogic chipset table", - (int) platform_length, platform); - /* Create chipset name from entry */ - return (struct cpuinfo_arm_chipset) { - .vendor = cpuinfo_arm_chipset_vendor_amlogic, - .series = (enum cpuinfo_arm_chipset_series) amlogic_map_entries[i].series, - .model = amlogic_map_entries[i].model, - .suffix = { + "found ro.board.platform string \"%.*s\" in Amlogic chipset table", + (int)platform_length, + platform); + /* Create chipset name from entry */ + return (struct cpuinfo_arm_chipset){ + .vendor = cpuinfo_arm_chipset_vendor_amlogic, + .series = (enum cpuinfo_arm_chipset_series)amlogic_map_entries[i].series, + .model = amlogic_map_entries[i].model, + .suffix = + { [0] = amlogic_map_entries[i].suffix[0], [1] = amlogic_map_entries[i].suffix[1], [2] = amlogic_map_entries[i].suffix[2], }, - }; - } + }; } } + } - /* Compare to tabulated ro.board.platform values for popular chipsets/devices which can't be otherwise detected */ - for (size_t i = 0; i < CPUINFO_COUNT_OF(special_platform_map_entries); i++) { - if (strncmp(special_platform_map_entries[i].platform, platform, platform_length) == 0 && - special_platform_map_entries[i].platform[platform_length] == 0) - { - /* Create chipset name from entry */ - cpuinfo_log_debug( - "found ro.board.platform string \"%.*s\" in special chipset table", (int) platform_length, platform); - return (struct cpuinfo_arm_chipset) { - .vendor = chipset_series_vendor[special_platform_map_entries[i].series], - .series = (enum cpuinfo_arm_chipset_series) special_platform_map_entries[i].series, - .model = special_platform_map_entries[i].model, - .suffix = { + /* Compare to tabulated ro.board.platform values for popular + * chipsets/devices which can't be otherwise detected */ + for (size_t i = 0; i < CPUINFO_COUNT_OF(special_platform_map_entries); i++) { + if (strncmp(special_platform_map_entries[i].platform, platform, platform_length) == 0 && + special_platform_map_entries[i].platform[platform_length] == 0) { + /* Create chipset name from entry */ + cpuinfo_log_debug( + "found ro.board.platform string \"%.*s\" in special chipset table", + (int)platform_length, + platform); + return (struct cpuinfo_arm_chipset){ + .vendor = chipset_series_vendor[special_platform_map_entries[i].series], + .series = (enum cpuinfo_arm_chipset_series)special_platform_map_entries[i].series, + .model = special_platform_map_entries[i].model, + .suffix = + { [0] = special_platform_map_entries[i].suffix, }, - }; - } + }; } - - /* None of the ro.board.platform signatures matched, indicate unknown chipset */ - return (struct cpuinfo_arm_chipset) { - .vendor = cpuinfo_arm_chipset_vendor_unknown, - .series = cpuinfo_arm_chipset_series_unknown, - }; } - /* - * Decodes chipset name from ro.mediatek.platform Android system property. - * - * @param[in] platform - ro.mediatek.platform value. - * - * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` - * vendor and series identifiers. + /* None of the ro.board.platform signatures matched, indicate unknown + * chipset */ - struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_mediatek_platform( - const char platform[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]) - { - struct cpuinfo_arm_chipset chipset; - const char* platform_end = platform + strnlen(platform, CPUINFO_BUILD_PROP_VALUE_MAX); + return (struct cpuinfo_arm_chipset){ + .vendor = cpuinfo_arm_chipset_vendor_unknown, + .series = cpuinfo_arm_chipset_series_unknown, + }; +} - /* Check MediaTek MT signature */ - if (match_mt(platform, platform_end, false, &chipset)) { - return chipset; - } +/* + * Decodes chipset name from ro.mediatek.platform Android system property. + * + * @param[in] platform - ro.mediatek.platform value. + * + * @returns Decoded chipset name. If chipset could not be decoded, the resulting + * structure would use `unknown` vendor and series identifiers. + */ +struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_mediatek_platform( + const char platform[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]) { + struct cpuinfo_arm_chipset chipset; + const char* platform_end = platform + strnlen(platform, CPUINFO_BUILD_PROP_VALUE_MAX); - return (struct cpuinfo_arm_chipset) { - .vendor = cpuinfo_arm_chipset_vendor_unknown, - .series = cpuinfo_arm_chipset_series_unknown, - }; + /* Check MediaTek MT signature */ + if (match_mt(platform, platform_end, false, &chipset)) { + return chipset; } + return (struct cpuinfo_arm_chipset){ + .vendor = cpuinfo_arm_chipset_vendor_unknown, + .series = cpuinfo_arm_chipset_series_unknown, + }; +} - /* - * Decodes chipset name from ro.arch Android system property. - * - * The ro.arch property is matched only against Samsung Exynos signature. Systems with other chipset rarely - * configure ro.arch Android system property, and can be decoded through other properties, but some Exynos - * chipsets are identified only in ro.arch. - * - * @param[in] arch - ro.arch value. - * - * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` - * vendor and series identifiers. - */ - struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_arch( - const char arch[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]) - { - struct cpuinfo_arm_chipset chipset; - const char* arch_end = arch + strnlen(arch, CPUINFO_BUILD_PROP_VALUE_MAX); +/* + * Decodes chipset name from ro.arch Android system property. + * + * The ro.arch property is matched only against Samsung Exynos signature. + * Systems with other chipset rarely configure ro.arch Android system property, + * and can be decoded through other properties, but some Exynos chipsets are + * identified only in ro.arch. + * + * @param[in] arch - ro.arch value. + * + * @returns Decoded chipset name. If chipset could not be decoded, the resulting + * structure would use `unknown` vendor and series identifiers. + */ +struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_arch( + const char arch[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]) { + struct cpuinfo_arm_chipset chipset; + const char* arch_end = arch + strnlen(arch, CPUINFO_BUILD_PROP_VALUE_MAX); - /* Check Samsung exynosXXXX signature */ - if (match_exynos(arch, arch_end, &chipset)) { - return chipset; - } - - return (struct cpuinfo_arm_chipset) { - .vendor = cpuinfo_arm_chipset_vendor_unknown, - .series = cpuinfo_arm_chipset_series_unknown, - }; + /* Check Samsung exynosXXXX signature */ + if (match_exynos(arch, arch_end, &chipset)) { + return chipset; } - /* - * Decodes chipset name from ro.chipname or ro.hardware.chipname Android system property. - * - * @param[in] chipname - ro.chipname or ro.hardware.chipname value. - * - * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` vendor - * and series identifiers. - */ + return (struct cpuinfo_arm_chipset){ + .vendor = cpuinfo_arm_chipset_vendor_unknown, + .series = cpuinfo_arm_chipset_series_unknown, + }; +} - struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_chipname( - const char chipname[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]) - { - struct cpuinfo_arm_chipset chipset; - const size_t chipname_length = strnlen(chipname, CPUINFO_BUILD_PROP_VALUE_MAX); - const char* chipname_end = chipname + chipname_length; +/* + * Decodes chipset name from ro.chipname or ro.hardware.chipname Android system + * property. + * + * @param[in] chipname - ro.chipname or ro.hardware.chipname value. + * + * @returns Decoded chipset name. If chipset could not be decoded, the resulting + * structure would use `unknown` vendor and series identifiers. + */ - /* Check Qualcomm MSM/APQ signatures */ - if (match_msm_apq(chipname, chipname_end, &chipset)) { - cpuinfo_log_debug( - "matched Qualcomm MSM/APQ signature in ro.chipname string \"%.*s\"", - (int) chipname_length, chipname); - return chipset; - } +struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_chipname( + const char chipname[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]) { + struct cpuinfo_arm_chipset chipset; + const size_t chipname_length = strnlen(chipname, CPUINFO_BUILD_PROP_VALUE_MAX); + const char* chipname_end = chipname + chipname_length; - /* Check SMxxxx (Qualcomm Snapdragon) signature */ - if (match_sm(chipname, chipname_end, &chipset)) { - cpuinfo_log_debug( - "matched Qualcomm SM signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) chipname_length, chipname); - return chipset; - } + /* Check Qualcomm MSM/APQ signatures */ + if (match_msm_apq(chipname, chipname_end, &chipset)) { + cpuinfo_log_debug( + "matched Qualcomm MSM/APQ signature in ro.chipname string \"%.*s\"", + (int)chipname_length, + chipname); + return chipset; + } - /* Check exynosXXXX (Samsung Exynos) signature */ - if (match_exynos(chipname, chipname_end, &chipset)) { - cpuinfo_log_debug( - "matched exynosXXXX (Samsung Exynos) signature in ro.chipname string \"%.*s\"", - (int) chipname_length, chipname); - return chipset; - } + /* Check SMxxxx (Qualcomm Snapdragon) signature */ + if (match_sm(chipname, chipname_end, &chipset)) { + cpuinfo_log_debug( + "matched Qualcomm SM signature in /proc/cpuinfo Hardware string \"%.*s\"", + (int)chipname_length, + chipname); + return chipset; + } - /* Check universalXXXX (Samsung Exynos) signature */ - if (match_universal(chipname, chipname_end, &chipset)) { - cpuinfo_log_debug( - "matched UNIVERSAL (Samsung Exynos) signature in ro.chipname Hardware string \"%.*s\"", - (int) chipname_length, chipname); - return chipset; - } + /* Check exynosXXXX (Samsung Exynos) signature */ + if (match_exynos(chipname, chipname_end, &chipset)) { + cpuinfo_log_debug( + "matched exynosXXXX (Samsung Exynos) signature in ro.chipname string \"%.*s\"", + (int)chipname_length, + chipname); + return chipset; + } - /* Check MediaTek MT signature */ - if (match_mt(chipname, chipname_end, true, &chipset)) { - cpuinfo_log_debug( - "matched MediaTek MT signature in ro.chipname string \"%.*s\"", - (int) chipname_length, chipname); - return chipset; - } + /* Check universalXXXX (Samsung Exynos) signature */ + if (match_universal(chipname, chipname_end, &chipset)) { + cpuinfo_log_debug( + "matched UNIVERSAL (Samsung Exynos) signature in ro.chipname Hardware string \"%.*s\"", + (int)chipname_length, + chipname); + return chipset; + } - /* Check Spreadtrum SC signature */ - if (match_sc(chipname, chipname_end, &chipset)) { - cpuinfo_log_debug( - "matched Spreadtrum SC signature in ro.chipname string \"%.*s\"", - (int) chipname_length, chipname); - return chipset; - } + /* Check MediaTek MT signature */ + if (match_mt(chipname, chipname_end, true, &chipset)) { + cpuinfo_log_debug( + "matched MediaTek MT signature in ro.chipname string \"%.*s\"", (int)chipname_length, chipname); + return chipset; + } - #if CPUINFO_ARCH_ARM - /* Check Marvell PXA signature */ - if (match_pxa(chipname, chipname_end, &chipset)) { - cpuinfo_log_debug( - "matched Marvell PXA signature in ro.chipname string \"%.*s\"", - (int) chipname_length, chipname); - return chipset; - } + /* Check Spreadtrum SC signature */ + if (match_sc(chipname, chipname_end, &chipset)) { + cpuinfo_log_debug( + "matched Spreadtrum SC signature in ro.chipname string \"%.*s\"", + (int)chipname_length, + chipname); + return chipset; + } - /* Compare to ro.chipname value ("mp523x") for Renesas MP5232 which can't be otherwise detected */ - if (chipname_length == 6 && memcmp(chipname, "mp523x", 6) == 0) { - cpuinfo_log_debug( - "matched Renesas MP5232 signature in ro.chipname string \"%.*s\"", - (int) chipname_length, chipname); +#if CPUINFO_ARCH_ARM + /* Check Marvell PXA signature */ + if (match_pxa(chipname, chipname_end, &chipset)) { + cpuinfo_log_debug( + "matched Marvell PXA signature in ro.chipname string \"%.*s\"", (int)chipname_length, chipname); + return chipset; + } - return (struct cpuinfo_arm_chipset) { - .vendor = cpuinfo_arm_chipset_vendor_renesas, - .series = cpuinfo_arm_chipset_series_renesas_mp, - .model = 5232, - }; - } - #endif + /* Compare to ro.chipname value ("mp523x") for Renesas MP5232 which + * can't be otherwise detected */ + if (chipname_length == 6 && memcmp(chipname, "mp523x", 6) == 0) { + cpuinfo_log_debug( + "matched Renesas MP5232 signature in ro.chipname string \"%.*s\"", + (int)chipname_length, + chipname); - return (struct cpuinfo_arm_chipset) { - .vendor = cpuinfo_arm_chipset_vendor_unknown, - .series = cpuinfo_arm_chipset_series_unknown, + return (struct cpuinfo_arm_chipset){ + .vendor = cpuinfo_arm_chipset_vendor_renesas, + .series = cpuinfo_arm_chipset_series_renesas_mp, + .model = 5232, }; } +#endif + + return (struct cpuinfo_arm_chipset){ + .vendor = cpuinfo_arm_chipset_vendor_unknown, + .series = cpuinfo_arm_chipset_series_unknown, + }; +} #endif /* __ANDROID__ */ /* @@ -3217,96 +3362,136 @@ struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_ha * * @param[in,out] chipset - chipset name to fix. * @param cores - number of cores in the chipset. - * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. + * @param max_cpu_freq_max - maximum of + * /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. */ void cpuinfo_arm_fixup_chipset( - struct cpuinfo_arm_chipset chipset[restrict static 1], uint32_t cores, uint32_t max_cpu_freq_max) -{ + struct cpuinfo_arm_chipset chipset[restrict static 1], + uint32_t cores, + uint32_t max_cpu_freq_max) { switch (chipset->series) { case cpuinfo_arm_chipset_series_qualcomm_msm: /* Check if there is suffix */ if (chipset->suffix[0] == 0) { - /* No suffix, but the model may be misreported */ + /* No suffix, but the model may be misreported + */ switch (chipset->model) { case 8216: - /* MSM8216 was renamed to MSM8916 */ + /* MSM8216 was renamed to + * MSM8916 */ cpuinfo_log_info("reinterpreted MSM8216 chipset as MSM8916"); chipset->model = 8916; break; case 8916: - /* Common bug: MSM8939 (Octa-core) reported as MSM8916 (Quad-core) */ + /* Common bug: MSM8939 + * (Octa-core) reported as + * MSM8916 (Quad-core) + */ switch (cores) { case 4: break; case 8: - cpuinfo_log_info("reinterpreted MSM8916 chipset with 8 cores as MSM8939"); + cpuinfo_log_info( + "reinterpreted MSM8916 chipset with 8 cores as MSM8939"); chipset->model = 8939; break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core MSM%"PRIu32" chipset", - cores, chipset->model); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 + "-core MSM%" PRIu32 " chipset", + cores, + chipset->model); chipset->model = 0; } break; case 8937: - /* Common bug: MSM8917 (Quad-core) reported as MSM8937 (Octa-core) */ + /* Common bug: MSM8917 + * (Quad-core) reported as + * MSM8937 (Octa-core) + */ switch (cores) { case 4: - cpuinfo_log_info("reinterpreted MSM8937 chipset with 4 cores as MSM8917"); + cpuinfo_log_info( + "reinterpreted MSM8937 chipset with 4 cores as MSM8917"); chipset->model = 8917; break; case 8: break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core MSM%"PRIu32" chipset", - cores, chipset->model); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 + "-core MSM%" PRIu32 " chipset", + cores, + chipset->model); chipset->model = 0; } break; case 8960: - /* Common bug: APQ8064 (Quad-core) reported as MSM8960 (Dual-core) */ + /* Common bug: APQ8064 + * (Quad-core) reported as + * MSM8960 (Dual-core) + */ switch (cores) { case 2: break; case 4: - cpuinfo_log_info("reinterpreted MSM8960 chipset with 4 cores as APQ8064"); - chipset->series = cpuinfo_arm_chipset_series_qualcomm_apq; + cpuinfo_log_info( + "reinterpreted MSM8960 chipset with 4 cores as APQ8064"); + chipset->series = + cpuinfo_arm_chipset_series_qualcomm_apq; chipset->model = 8064; break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core MSM%"PRIu32" chipset", - cores, chipset->model); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 + "-core MSM%" PRIu32 " chipset", + cores, + chipset->model); chipset->model = 0; } break; case 8996: - /* Common bug: MSM8994 (Octa-core) reported as MSM8996 (Quad-core) */ + /* Common bug: MSM8994 + * (Octa-core) reported as + * MSM8996 (Quad-core) + */ switch (cores) { case 4: break; case 8: - cpuinfo_log_info("reinterpreted MSM8996 chipset with 8 cores as MSM8994"); + cpuinfo_log_info( + "reinterpreted MSM8996 chipset with 8 cores as MSM8994"); chipset->model = 8994; break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core MSM%"PRIu32" chipset", - cores, chipset->model); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 + "-core MSM%" PRIu32 " chipset", + cores, + chipset->model); chipset->model = 0; } break; #if CPUINFO_ARCH_ARM case 8610: - /* Common bug: MSM8612 (Quad-core) reported as MSM8610 (Dual-core) */ + /* Common bug: MSM8612 + * (Quad-core) reported as + * MSM8610 (Dual-core) + */ switch (cores) { case 2: break; case 4: - cpuinfo_log_info("reinterpreted MSM8610 chipset with 4 cores as MSM8612"); + cpuinfo_log_info( + "reinterpreted MSM8610 chipset with 4 cores as MSM8612"); chipset->model = 8612; break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core MSM%"PRIu32" chipset", - cores, chipset->model); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 + "-core MSM%" PRIu32 " chipset", + cores, + chipset->model); chipset->model = 0; } break; @@ -3317,8 +3502,10 @@ void cpuinfo_arm_fixup_chipset( const uint32_t suffix_word = load_u32le(chipset->suffix); if (suffix_word == UINT32_C(0x004D534D) /* "\0MSM" = reverse("MSM\0") */) { /* - * Common bug: model name repeated twice, e.g. "MSM8916MSM8916" - * In this case, model matching code parses the second "MSM" as a suffix + * Common bug: model name repeated + * twice, e.g. "MSM8916MSM8916" In this + * case, model matching code parses the + * second "MSM" as a suffix */ chipset->suffix[0] = 0; chipset->suffix[1] = 0; @@ -3326,33 +3513,39 @@ void cpuinfo_arm_fixup_chipset( } else { switch (chipset->model) { case 8976: - /* MSM8976SG -> MSM8976PRO */ - if (suffix_word == UINT32_C(0x00004753) /* "\0\0GS" = reverse("SG\0\0") */ ) { + /* MSM8976SG -> + * MSM8976PRO */ + if (suffix_word == + UINT32_C(0x00004753) /* "\0\0GS" = reverse("SG\0\0") */) { chipset->suffix[0] = 'P'; chipset->suffix[1] = 'R'; chipset->suffix[2] = 'O'; } break; case 8996: - /* MSM8996PRO -> MSM8996PRO-AB or MSM8996PRO-AC */ - if (suffix_word == UINT32_C(0x004F5250) /* "\0ORP" = reverse("PRO\0") */ ) { + /* MSM8996PRO -> + * MSM8996PRO-AB or + * MSM8996PRO-AC */ + if (suffix_word == + UINT32_C(0x004F5250) /* "\0ORP" = reverse("PRO\0") */) { chipset->suffix[3] = '-'; chipset->suffix[4] = 'A'; - chipset->suffix[5] = 'B' + (char) (max_cpu_freq_max >= 2188800); + chipset->suffix[5] = + 'B' + (char)(max_cpu_freq_max >= 2188800); } break; } } } break; - case cpuinfo_arm_chipset_series_qualcomm_apq: - { + case cpuinfo_arm_chipset_series_qualcomm_apq: { /* Suffix may need correction */ const uint32_t expected_apq = load_u32le(chipset->suffix); if (expected_apq == UINT32_C(0x00515041) /* "\0QPA" = reverse("APQ\0") */) { /* - * Common bug: model name repeated twice, e.g. "APQ8016APQ8016" - * In this case, model matching code parses the second "APQ" as a suffix + * Common bug: model name repeated twice, e.g. + * "APQ8016APQ8016" In this case, model matching + * code parses the second "APQ" as a suffix */ chipset->suffix[0] = 0; chipset->suffix[1] = 0; @@ -3364,35 +3557,48 @@ void cpuinfo_arm_fixup_chipset( switch (chipset->model) { #if CPUINFO_ARCH_ARM case 4410: - /* Exynos 4410 was renamed to Exynos 4412 */ + /* Exynos 4410 was renamed to Exynos + * 4412 */ chipset->model = 4412; break; case 5420: - /* Common bug: Exynos 5260 (Hexa-core) reported as Exynos 5420 (Quad-core) */ + /* Common bug: Exynos 5260 (Hexa-core) + * reported as Exynos 5420 (Quad-core) + */ switch (cores) { case 4: break; case 6: - cpuinfo_log_info("reinterpreted Exynos 5420 chipset with 6 cores as Exynos 5260"); + cpuinfo_log_info( + "reinterpreted Exynos 5420 chipset with 6 cores as Exynos 5260"); chipset->model = 5260; break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core Exynos 5420 chipset", cores); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 + "-core Exynos 5420 chipset", + cores); chipset->model = 0; } break; #endif /* CPUINFO_ARCH_ARM */ case 7580: - /* Common bug: Exynos 7578 (Quad-core) reported as Exynos 7580 (Octa-core) */ + /* Common bug: Exynos 7578 (Quad-core) + * reported as Exynos 7580 (Octa-core) + */ switch (cores) { case 4: - cpuinfo_log_info("reinterpreted Exynos 7580 chipset with 4 cores as Exynos 7578"); + cpuinfo_log_info( + "reinterpreted Exynos 7580 chipset with 4 cores as Exynos 7578"); chipset->model = 7578; break; case 8: break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core Exynos 7580 chipset", cores); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 + "-core Exynos 7580 chipset", + cores); chipset->model = 0; } break; @@ -3400,7 +3606,8 @@ void cpuinfo_arm_fixup_chipset( break; case cpuinfo_arm_chipset_series_mediatek_mt: if (chipset->model == 6752) { - /* Common bug: MT6732 (Quad-core) reported as MT6752 (Octa-core) */ + /* Common bug: MT6732 (Quad-core) reported as + * MT6752 (Octa-core) */ switch (cores) { case 4: cpuinfo_log_info("reinterpreted MT6752 chipset with 4 cores as MT6732"); @@ -3409,16 +3616,23 @@ void cpuinfo_arm_fixup_chipset( case 8: break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core MT6752 chipset", cores); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 "-core MT6752 chipset", + cores); chipset->model = 0; } } if (chipset->suffix[0] == 'T') { - /* Normalization: "TURBO" and "TRUBO" (apparently a typo) -> "T" */ + /* Normalization: "TURBO" and "TRUBO" + * (apparently a typo) -> "T" */ const uint32_t suffix_word = load_u32le(chipset->suffix + 1); switch (suffix_word) { - case UINT32_C(0x4F425255): /* "OBRU" = reverse("URBO") */ - case UINT32_C(0x4F425552): /* "OBUR" = reverse("RUBO") */ + case UINT32_C(0x4F425255): /* "OBRU" = + reverse("URBO") + */ + case UINT32_C(0x4F425552): /* "OBUR" = + reverse("RUBO") + */ if (chipset->suffix[5] == 0) { chipset->suffix[1] = 0; chipset->suffix[2] = 0; @@ -3431,7 +3645,8 @@ void cpuinfo_arm_fixup_chipset( break; case cpuinfo_arm_chipset_series_rockchip_rk: if (chipset->model == 3288) { - /* Common bug: Rockchip RK3399 (Hexa-core) always reported as RK3288 (Quad-core) */ + /* Common bug: Rockchip RK3399 (Hexa-core) + * always reported as RK3288 (Quad-core) */ switch (cores) { case 4: break; @@ -3440,7 +3655,9 @@ void cpuinfo_arm_fixup_chipset( chipset->model = 3399; break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core RK3288 chipset", cores); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 "-core RK3288 chipset", + cores); chipset->model = 0; } } @@ -3452,71 +3669,71 @@ void cpuinfo_arm_fixup_chipset( /* Map from ARM chipset vendor ID to its string representation */ static const char* chipset_vendor_string[cpuinfo_arm_chipset_vendor_max] = { - [cpuinfo_arm_chipset_vendor_unknown] = "Unknown", - [cpuinfo_arm_chipset_vendor_qualcomm] = "Qualcomm", - [cpuinfo_arm_chipset_vendor_mediatek] = "MediaTek", - [cpuinfo_arm_chipset_vendor_samsung] = "Samsung", - [cpuinfo_arm_chipset_vendor_hisilicon] = "HiSilicon", - [cpuinfo_arm_chipset_vendor_actions] = "Actions", - [cpuinfo_arm_chipset_vendor_allwinner] = "Allwinner", - [cpuinfo_arm_chipset_vendor_amlogic] = "Amlogic", - [cpuinfo_arm_chipset_vendor_broadcom] = "Broadcom", - [cpuinfo_arm_chipset_vendor_lg] = "LG", - [cpuinfo_arm_chipset_vendor_leadcore] = "Leadcore", - [cpuinfo_arm_chipset_vendor_marvell] = "Marvell", - [cpuinfo_arm_chipset_vendor_mstar] = "MStar", - [cpuinfo_arm_chipset_vendor_novathor] = "NovaThor", - [cpuinfo_arm_chipset_vendor_nvidia] = "Nvidia", - [cpuinfo_arm_chipset_vendor_pinecone] = "Pinecone", - [cpuinfo_arm_chipset_vendor_renesas] = "Renesas", - [cpuinfo_arm_chipset_vendor_rockchip] = "Rockchip", - [cpuinfo_arm_chipset_vendor_spreadtrum] = "Spreadtrum", - [cpuinfo_arm_chipset_vendor_telechips] = "Telechips", + [cpuinfo_arm_chipset_vendor_unknown] = "Unknown", + [cpuinfo_arm_chipset_vendor_qualcomm] = "Qualcomm", + [cpuinfo_arm_chipset_vendor_mediatek] = "MediaTek", + [cpuinfo_arm_chipset_vendor_samsung] = "Samsung", + [cpuinfo_arm_chipset_vendor_hisilicon] = "HiSilicon", + [cpuinfo_arm_chipset_vendor_actions] = "Actions", + [cpuinfo_arm_chipset_vendor_allwinner] = "Allwinner", + [cpuinfo_arm_chipset_vendor_amlogic] = "Amlogic", + [cpuinfo_arm_chipset_vendor_broadcom] = "Broadcom", + [cpuinfo_arm_chipset_vendor_lg] = "LG", + [cpuinfo_arm_chipset_vendor_leadcore] = "Leadcore", + [cpuinfo_arm_chipset_vendor_marvell] = "Marvell", + [cpuinfo_arm_chipset_vendor_mstar] = "MStar", + [cpuinfo_arm_chipset_vendor_novathor] = "NovaThor", + [cpuinfo_arm_chipset_vendor_nvidia] = "Nvidia", + [cpuinfo_arm_chipset_vendor_pinecone] = "Pinecone", + [cpuinfo_arm_chipset_vendor_renesas] = "Renesas", + [cpuinfo_arm_chipset_vendor_rockchip] = "Rockchip", + [cpuinfo_arm_chipset_vendor_spreadtrum] = "Spreadtrum", + [cpuinfo_arm_chipset_vendor_telechips] = "Telechips", [cpuinfo_arm_chipset_vendor_texas_instruments] = "Texas Instruments", - [cpuinfo_arm_chipset_vendor_unisoc] = "Unisoc", - [cpuinfo_arm_chipset_vendor_wondermedia] = "WonderMedia", + [cpuinfo_arm_chipset_vendor_unisoc] = "Unisoc", + [cpuinfo_arm_chipset_vendor_wondermedia] = "WonderMedia", }; /* Map from ARM chipset series ID to its string representation */ static const char* chipset_series_string[cpuinfo_arm_chipset_series_max] = { - [cpuinfo_arm_chipset_series_unknown] = NULL, - [cpuinfo_arm_chipset_series_qualcomm_qsd] = "QSD", - [cpuinfo_arm_chipset_series_qualcomm_msm] = "MSM", - [cpuinfo_arm_chipset_series_qualcomm_apq] = "APQ", - [cpuinfo_arm_chipset_series_qualcomm_snapdragon] = "Snapdragon ", - [cpuinfo_arm_chipset_series_mediatek_mt] = "MT", - [cpuinfo_arm_chipset_series_samsung_exynos] = "Exynos ", - [cpuinfo_arm_chipset_series_hisilicon_k3v] = "K3V", - [cpuinfo_arm_chipset_series_hisilicon_hi] = "Hi", - [cpuinfo_arm_chipset_series_hisilicon_kirin] = "Kirin ", - [cpuinfo_arm_chipset_series_actions_atm] = "ATM", - [cpuinfo_arm_chipset_series_allwinner_a] = "A", - [cpuinfo_arm_chipset_series_amlogic_aml] = "AML", - [cpuinfo_arm_chipset_series_amlogic_s] = "S", - [cpuinfo_arm_chipset_series_broadcom_bcm] = "BCM", - [cpuinfo_arm_chipset_series_lg_nuclun] = "Nuclun ", - [cpuinfo_arm_chipset_series_leadcore_lc] = "LC", - [cpuinfo_arm_chipset_series_marvell_pxa] = "PXA", - [cpuinfo_arm_chipset_series_mstar_6a] = "6A", - [cpuinfo_arm_chipset_series_novathor_u] = "U", - [cpuinfo_arm_chipset_series_nvidia_tegra_t] = "Tegra T", - [cpuinfo_arm_chipset_series_nvidia_tegra_ap] = "Tegra AP", - [cpuinfo_arm_chipset_series_nvidia_tegra_sl] = "Tegra SL", - [cpuinfo_arm_chipset_series_pinecone_surge_s] = "Surge S", - [cpuinfo_arm_chipset_series_renesas_mp] = "MP", - [cpuinfo_arm_chipset_series_rockchip_rk] = "RK", - [cpuinfo_arm_chipset_series_spreadtrum_sc] = "SC", - [cpuinfo_arm_chipset_series_telechips_tcc] = "TCC", + [cpuinfo_arm_chipset_series_unknown] = NULL, + [cpuinfo_arm_chipset_series_qualcomm_qsd] = "QSD", + [cpuinfo_arm_chipset_series_qualcomm_msm] = "MSM", + [cpuinfo_arm_chipset_series_qualcomm_apq] = "APQ", + [cpuinfo_arm_chipset_series_qualcomm_snapdragon] = "Snapdragon ", + [cpuinfo_arm_chipset_series_mediatek_mt] = "MT", + [cpuinfo_arm_chipset_series_samsung_exynos] = "Exynos ", + [cpuinfo_arm_chipset_series_hisilicon_k3v] = "K3V", + [cpuinfo_arm_chipset_series_hisilicon_hi] = "Hi", + [cpuinfo_arm_chipset_series_hisilicon_kirin] = "Kirin ", + [cpuinfo_arm_chipset_series_actions_atm] = "ATM", + [cpuinfo_arm_chipset_series_allwinner_a] = "A", + [cpuinfo_arm_chipset_series_amlogic_aml] = "AML", + [cpuinfo_arm_chipset_series_amlogic_s] = "S", + [cpuinfo_arm_chipset_series_broadcom_bcm] = "BCM", + [cpuinfo_arm_chipset_series_lg_nuclun] = "Nuclun ", + [cpuinfo_arm_chipset_series_leadcore_lc] = "LC", + [cpuinfo_arm_chipset_series_marvell_pxa] = "PXA", + [cpuinfo_arm_chipset_series_mstar_6a] = "6A", + [cpuinfo_arm_chipset_series_novathor_u] = "U", + [cpuinfo_arm_chipset_series_nvidia_tegra_t] = "Tegra T", + [cpuinfo_arm_chipset_series_nvidia_tegra_ap] = "Tegra AP", + [cpuinfo_arm_chipset_series_nvidia_tegra_sl] = "Tegra SL", + [cpuinfo_arm_chipset_series_pinecone_surge_s] = "Surge S", + [cpuinfo_arm_chipset_series_renesas_mp] = "MP", + [cpuinfo_arm_chipset_series_rockchip_rk] = "RK", + [cpuinfo_arm_chipset_series_spreadtrum_sc] = "SC", + [cpuinfo_arm_chipset_series_telechips_tcc] = "TCC", [cpuinfo_arm_chipset_series_texas_instruments_omap] = "OMAP", - [cpuinfo_arm_chipset_series_unisoc_t] = "T", - [cpuinfo_arm_chipset_series_wondermedia_wm] = "WM", + [cpuinfo_arm_chipset_series_unisoc_t] = "T", + [cpuinfo_arm_chipset_series_wondermedia_wm] = "WM", }; -/* Convert chipset name represented by cpuinfo_arm_chipset structure to a string representation */ +/* Convert chipset name represented by cpuinfo_arm_chipset structure to a string + * representation */ void cpuinfo_arm_chipset_to_string( const struct cpuinfo_arm_chipset chipset[restrict static 1], - char name[restrict static CPUINFO_ARM_CHIPSET_NAME_MAX]) -{ + char name[restrict static CPUINFO_ARM_CHIPSET_NAME_MAX]) { enum cpuinfo_arm_chipset_vendor vendor = chipset->vendor; if (vendor >= cpuinfo_arm_chipset_vendor_max) { vendor = cpuinfo_arm_chipset_vendor_unknown; @@ -3532,387 +3749,411 @@ void cpuinfo_arm_chipset_to_string( if (series == cpuinfo_arm_chipset_series_unknown) { strncpy(name, vendor_string, CPUINFO_ARM_CHIPSET_NAME_MAX); } else { - snprintf(name, CPUINFO_ARM_CHIPSET_NAME_MAX, - "%s %s", vendor_string, series_string); + snprintf(name, CPUINFO_ARM_CHIPSET_NAME_MAX, "%s %s", vendor_string, series_string); } } else { const size_t suffix_length = strnlen(chipset->suffix, CPUINFO_ARM_CHIPSET_SUFFIX_MAX); - snprintf(name, CPUINFO_ARM_CHIPSET_NAME_MAX, - "%s %s%"PRIu32"%.*s", vendor_string, series_string, model, (int) suffix_length, chipset->suffix); + snprintf( + name, + CPUINFO_ARM_CHIPSET_NAME_MAX, + "%s %s%" PRIu32 "%.*s", + vendor_string, + series_string, + model, + (int)suffix_length, + chipset->suffix); } } #if defined(__ANDROID__) - static inline struct cpuinfo_arm_chipset disambiguate_qualcomm_chipset( - const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_hardware_chipname_chipset[restrict static 1]) - { - if (ro_hardware_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_hardware_chipname_chipset; - } - if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_chipname_chipset; - } - if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *proc_cpuinfo_hardware_chipset; - } - if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_product_board_chipset; - } - return *ro_board_platform_chipset; +static inline struct cpuinfo_arm_chipset disambiguate_qualcomm_chipset( + const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_hardware_chipname_chipset[restrict static 1]) { + if (ro_hardware_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_hardware_chipname_chipset; } - - static inline struct cpuinfo_arm_chipset disambiguate_mediatek_chipset( - const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_mediatek_platform_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1]) - { - if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_chipname_chipset; - } - if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *proc_cpuinfo_hardware_chipset; - } - if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_product_board_chipset; - } - if (ro_board_platform_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_board_platform_chipset; - } - return *ro_mediatek_platform_chipset; + if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_chipname_chipset; } - - static inline struct cpuinfo_arm_chipset disambiguate_hisilicon_chipset( - const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1]) - { - if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *proc_cpuinfo_hardware_chipset; - } - if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_product_board_chipset; - } - return *ro_board_platform_chipset; - } - - static inline struct cpuinfo_arm_chipset disambiguate_amlogic_chipset( - const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1]) - { - if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *proc_cpuinfo_hardware_chipset; - } - return *ro_board_platform_chipset; - } - - static inline struct cpuinfo_arm_chipset disambiguate_marvell_chipset( - const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1]) - { - if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_chipname_chipset; - } - if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_product_board_chipset; - } + if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { return *proc_cpuinfo_hardware_chipset; } + if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_product_board_chipset; + } + return *ro_board_platform_chipset; +} - static inline struct cpuinfo_arm_chipset disambiguate_rockchip_chipset( - const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1]) - { - if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_product_board_chipset; - } - if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *proc_cpuinfo_hardware_chipset; - } +static inline struct cpuinfo_arm_chipset disambiguate_mediatek_chipset( + const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_mediatek_platform_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1]) { + if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_chipname_chipset; + } + if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *proc_cpuinfo_hardware_chipset; + } + if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_product_board_chipset; + } + if (ro_board_platform_chipset->series != cpuinfo_arm_chipset_series_unknown) { return *ro_board_platform_chipset; } + return *ro_mediatek_platform_chipset; +} - static inline struct cpuinfo_arm_chipset disambiguate_spreadtrum_chipset( - const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1]) - { - if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_chipname_chipset; +static inline struct cpuinfo_arm_chipset disambiguate_hisilicon_chipset( + const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1]) { + if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *proc_cpuinfo_hardware_chipset; + } + if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_product_board_chipset; + } + return *ro_board_platform_chipset; +} + +static inline struct cpuinfo_arm_chipset disambiguate_amlogic_chipset( + const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1]) { + if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *proc_cpuinfo_hardware_chipset; + } + return *ro_board_platform_chipset; +} + +static inline struct cpuinfo_arm_chipset disambiguate_marvell_chipset( + const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1]) { + if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_chipname_chipset; + } + if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_product_board_chipset; + } + return *proc_cpuinfo_hardware_chipset; +} + +static inline struct cpuinfo_arm_chipset disambiguate_rockchip_chipset( + const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1]) { + if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_product_board_chipset; + } + if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *proc_cpuinfo_hardware_chipset; + } + return *ro_board_platform_chipset; +} + +static inline struct cpuinfo_arm_chipset disambiguate_spreadtrum_chipset( + const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1]) { + if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_chipname_chipset; + } + if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_product_board_chipset; + } + if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *proc_cpuinfo_hardware_chipset; + } + return *ro_board_platform_chipset; +} + +/* + * Decodes chipset name from Android system properties: + * - /proc/cpuinfo Hardware string + * - ro.product.board + * - ro.board.platform + * - ro.mediatek.platform + * - ro.chipname + * For some chipsets, the function relies frequency and on number of cores for + * chipset detection. + * + * @param[in] properties - structure with the Android system properties + * described above. + * @param cores - number of cores in the chipset. + * @param max_cpu_freq_max - maximum of + * /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. + * + * @returns Decoded chipset name. If chipset could not be decoded, the resulting + * structure would use `unknown` vendor and series identifiers. + */ +struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset( + const struct cpuinfo_android_properties properties[restrict static 1], + uint32_t cores, + uint32_t max_cpu_freq_max) { + struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_unknown, + .series = cpuinfo_arm_chipset_series_unknown, + }; + + const bool tegra_platform = is_tegra( + properties->ro_board_platform, + properties->ro_board_platform + strnlen(properties->ro_board_platform, CPUINFO_BUILD_PROP_VALUE_MAX)); + + struct cpuinfo_arm_chipset chipsets[cpuinfo_android_chipset_property_max] = { + [cpuinfo_android_chipset_property_proc_cpuinfo_hardware] = + cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_hardware( + properties->proc_cpuinfo_hardware, cores, max_cpu_freq_max, tegra_platform), + [cpuinfo_android_chipset_property_ro_product_board] = + cpuinfo_arm_android_decode_chipset_from_ro_product_board( + properties->ro_product_board, cores, max_cpu_freq_max), + [cpuinfo_android_chipset_property_ro_board_platform] = + cpuinfo_arm_android_decode_chipset_from_ro_board_platform( + properties->ro_board_platform, cores, max_cpu_freq_max), + [cpuinfo_android_chipset_property_ro_mediatek_platform] = + cpuinfo_arm_android_decode_chipset_from_ro_mediatek_platform(properties->ro_mediatek_platform), + [cpuinfo_android_chipset_property_ro_arch] = + cpuinfo_arm_android_decode_chipset_from_ro_arch(properties->ro_arch), + [cpuinfo_android_chipset_property_ro_chipname] = + cpuinfo_arm_android_decode_chipset_from_ro_chipname(properties->ro_chipname), + [cpuinfo_android_chipset_property_ro_hardware_chipname] = + cpuinfo_arm_android_decode_chipset_from_ro_chipname(properties->ro_hardware_chipname), + }; + enum cpuinfo_arm_chipset_vendor vendor = cpuinfo_arm_chipset_vendor_unknown; + for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { + const enum cpuinfo_arm_chipset_vendor decoded_vendor = chipsets[i].vendor; + if (decoded_vendor != cpuinfo_arm_chipset_vendor_unknown) { + if (vendor == cpuinfo_arm_chipset_vendor_unknown) { + vendor = decoded_vendor; + } else if (vendor != decoded_vendor) { + /* Parsing different system properties produces + * different chipset vendors. This situation is + * rare. */ + cpuinfo_log_error( + "chipset detection failed: different chipset vendors reported in different system properties"); + goto finish; + } } - if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_product_board_chipset; - } - if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *proc_cpuinfo_hardware_chipset; - } - return *ro_board_platform_chipset; + } + if (vendor == cpuinfo_arm_chipset_vendor_unknown) { + cpuinfo_log_warning("chipset detection failed: none of the system properties matched known signatures"); + goto finish; + } + + /* Fix common bugs in reported chipsets */ + for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { + cpuinfo_arm_fixup_chipset(&chipsets[i], cores, max_cpu_freq_max); } /* - * Decodes chipset name from Android system properties: - * - /proc/cpuinfo Hardware string - * - ro.product.board - * - ro.board.platform - * - ro.mediatek.platform - * - ro.chipname - * For some chipsets, the function relies frequency and on number of cores for chipset detection. - * - * @param[in] properties - structure with the Android system properties described above. - * @param cores - number of cores in the chipset. - * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. - * - * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` vendor - * and series identifiers. + * Propagate suffixes: consider all pairs of chipsets, if both chipsets + * in the pair are from the same series, and one's suffix is a prefix of + * another's chipset suffix, use the longest suffix. */ - struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset( - const struct cpuinfo_android_properties properties[restrict static 1], - uint32_t cores, - uint32_t max_cpu_freq_max) - { - struct cpuinfo_arm_chipset chipset = { - .vendor = cpuinfo_arm_chipset_vendor_unknown, - .series = cpuinfo_arm_chipset_series_unknown, - }; - - const bool tegra_platform = is_tegra( - properties->ro_board_platform, - properties->ro_board_platform + strnlen(properties->ro_board_platform, CPUINFO_BUILD_PROP_VALUE_MAX)); - - struct cpuinfo_arm_chipset chipsets[cpuinfo_android_chipset_property_max] = { - [cpuinfo_android_chipset_property_proc_cpuinfo_hardware] = - cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_hardware( - properties->proc_cpuinfo_hardware, cores, max_cpu_freq_max, tegra_platform), - [cpuinfo_android_chipset_property_ro_product_board] = - cpuinfo_arm_android_decode_chipset_from_ro_product_board( - properties->ro_product_board, cores, max_cpu_freq_max), - [cpuinfo_android_chipset_property_ro_board_platform] = - cpuinfo_arm_android_decode_chipset_from_ro_board_platform( - properties->ro_board_platform, cores, max_cpu_freq_max), - [cpuinfo_android_chipset_property_ro_mediatek_platform] = - cpuinfo_arm_android_decode_chipset_from_ro_mediatek_platform(properties->ro_mediatek_platform), - [cpuinfo_android_chipset_property_ro_arch] = - cpuinfo_arm_android_decode_chipset_from_ro_arch(properties->ro_arch), - [cpuinfo_android_chipset_property_ro_chipname] = - cpuinfo_arm_android_decode_chipset_from_ro_chipname(properties->ro_chipname), - [cpuinfo_android_chipset_property_ro_hardware_chipname] = - cpuinfo_arm_android_decode_chipset_from_ro_chipname(properties->ro_hardware_chipname), - }; - enum cpuinfo_arm_chipset_vendor vendor = cpuinfo_arm_chipset_vendor_unknown; - for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { - const enum cpuinfo_arm_chipset_vendor decoded_vendor = chipsets[i].vendor; - if (decoded_vendor != cpuinfo_arm_chipset_vendor_unknown) { - if (vendor == cpuinfo_arm_chipset_vendor_unknown) { - vendor = decoded_vendor; - } else if (vendor != decoded_vendor) { - /* Parsing different system properties produces different chipset vendors. This situation is rare. */ - cpuinfo_log_error( - "chipset detection failed: different chipset vendors reported in different system properties"); - goto finish; - } - } - } - if (vendor == cpuinfo_arm_chipset_vendor_unknown) { - cpuinfo_log_warning( - "chipset detection failed: none of the system properties matched known signatures"); - goto finish; - } - - /* Fix common bugs in reported chipsets */ - for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { - cpuinfo_arm_fixup_chipset(&chipsets[i], cores, max_cpu_freq_max); - } - - /* - * Propagate suffixes: consider all pairs of chipsets, if both chipsets in the pair are from the same series, - * and one's suffix is a prefix of another's chipset suffix, use the longest suffix. - */ - for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { - const size_t chipset_i_suffix_length = strnlen(chipsets[i].suffix, CPUINFO_ARM_CHIPSET_SUFFIX_MAX); - for (size_t j = 0; j < i; j++) { - if (chipsets[i].series == chipsets[j].series) { - const size_t chipset_j_suffix_length = strnlen(chipsets[j].suffix, CPUINFO_ARM_CHIPSET_SUFFIX_MAX); - if (chipset_i_suffix_length != chipset_j_suffix_length) { - const size_t common_prefix_length = (chipset_i_suffix_length < chipset_j_suffix_length) ? - chipset_i_suffix_length : chipset_j_suffix_length; - if (common_prefix_length == 0 || - memcmp(chipsets[i].suffix, chipsets[j].suffix, common_prefix_length) == 0) - { - if (chipset_i_suffix_length > chipset_j_suffix_length) { - memcpy(chipsets[j].suffix, chipsets[i].suffix, chipset_i_suffix_length); - } else { - memcpy(chipsets[i].suffix, chipsets[j].suffix, chipset_j_suffix_length); - } + for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { + const size_t chipset_i_suffix_length = strnlen(chipsets[i].suffix, CPUINFO_ARM_CHIPSET_SUFFIX_MAX); + for (size_t j = 0; j < i; j++) { + if (chipsets[i].series == chipsets[j].series) { + const size_t chipset_j_suffix_length = + strnlen(chipsets[j].suffix, CPUINFO_ARM_CHIPSET_SUFFIX_MAX); + if (chipset_i_suffix_length != chipset_j_suffix_length) { + const size_t common_prefix_length = + (chipset_i_suffix_length < chipset_j_suffix_length) + ? chipset_i_suffix_length + : chipset_j_suffix_length; + if (common_prefix_length == 0 || + memcmp(chipsets[i].suffix, chipsets[j].suffix, common_prefix_length) == 0) { + if (chipset_i_suffix_length > chipset_j_suffix_length) { + memcpy(chipsets[j].suffix, + chipsets[i].suffix, + chipset_i_suffix_length); + } else { + memcpy(chipsets[i].suffix, + chipsets[j].suffix, + chipset_j_suffix_length); } } } } } + } - for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { - if (chipsets[i].series != cpuinfo_arm_chipset_series_unknown) { - if (chipset.series == cpuinfo_arm_chipset_series_unknown) { - chipset = chipsets[i]; - } else if (chipsets[i].series != chipset.series || chipsets[i].model != chipset.model || - strncmp(chipsets[i].suffix, chipset.suffix, CPUINFO_ARM_CHIPSET_SUFFIX_MAX) != 0) - { - cpuinfo_log_info( - "different chipsets reported in different system properties; " - "vendor-specific disambiguation heuristic would be used"); - switch (vendor) { - case cpuinfo_arm_chipset_vendor_qualcomm: - return disambiguate_qualcomm_chipset( - &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], - &chipsets[cpuinfo_android_chipset_property_ro_product_board], - &chipsets[cpuinfo_android_chipset_property_ro_board_platform], - &chipsets[cpuinfo_android_chipset_property_ro_chipname], - &chipsets[cpuinfo_android_chipset_property_ro_hardware_chipname]); - case cpuinfo_arm_chipset_vendor_mediatek: - return disambiguate_mediatek_chipset( - &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], - &chipsets[cpuinfo_android_chipset_property_ro_product_board], - &chipsets[cpuinfo_android_chipset_property_ro_board_platform], - &chipsets[cpuinfo_android_chipset_property_ro_mediatek_platform], - &chipsets[cpuinfo_android_chipset_property_ro_chipname]); - case cpuinfo_arm_chipset_vendor_hisilicon: - return disambiguate_hisilicon_chipset( - &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], - &chipsets[cpuinfo_android_chipset_property_ro_product_board], - &chipsets[cpuinfo_android_chipset_property_ro_board_platform]); - case cpuinfo_arm_chipset_vendor_amlogic: - return disambiguate_amlogic_chipset( - &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], - &chipsets[cpuinfo_android_chipset_property_ro_board_platform]); - case cpuinfo_arm_chipset_vendor_marvell: - return disambiguate_marvell_chipset( - &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], - &chipsets[cpuinfo_android_chipset_property_ro_product_board], - &chipsets[cpuinfo_android_chipset_property_ro_chipname]); - case cpuinfo_arm_chipset_vendor_rockchip: - return disambiguate_rockchip_chipset( - &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], - &chipsets[cpuinfo_android_chipset_property_ro_product_board], - &chipsets[cpuinfo_android_chipset_property_ro_board_platform]); - case cpuinfo_arm_chipset_vendor_spreadtrum: - return disambiguate_spreadtrum_chipset( - &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], - &chipsets[cpuinfo_android_chipset_property_ro_product_board], - &chipsets[cpuinfo_android_chipset_property_ro_board_platform], - &chipsets[cpuinfo_android_chipset_property_ro_chipname]); - default: - cpuinfo_log_error( - "chipset detection failed: " - "could not disambiguate different chipsets reported in different system properties"); - /* chipset variable contains valid, but inconsistent chipset information, overwrite it */ - chipset = (struct cpuinfo_arm_chipset) { - .vendor = cpuinfo_arm_chipset_vendor_unknown, - .series = cpuinfo_arm_chipset_series_unknown, - }; - goto finish; - } + for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { + if (chipsets[i].series != cpuinfo_arm_chipset_series_unknown) { + if (chipset.series == cpuinfo_arm_chipset_series_unknown) { + chipset = chipsets[i]; + } else if ( + chipsets[i].series != chipset.series || chipsets[i].model != chipset.model || + strncmp(chipsets[i].suffix, chipset.suffix, CPUINFO_ARM_CHIPSET_SUFFIX_MAX) != 0) { + cpuinfo_log_info( + "different chipsets reported in different system properties; " + "vendor-specific disambiguation heuristic would be used"); + switch (vendor) { + case cpuinfo_arm_chipset_vendor_qualcomm: + return disambiguate_qualcomm_chipset( + &chipsets + [cpuinfo_android_chipset_property_proc_cpuinfo_hardware], + &chipsets[cpuinfo_android_chipset_property_ro_product_board], + &chipsets[cpuinfo_android_chipset_property_ro_board_platform], + &chipsets[cpuinfo_android_chipset_property_ro_chipname], + &chipsets + [cpuinfo_android_chipset_property_ro_hardware_chipname]); + case cpuinfo_arm_chipset_vendor_mediatek: + return disambiguate_mediatek_chipset( + &chipsets + [cpuinfo_android_chipset_property_proc_cpuinfo_hardware], + &chipsets[cpuinfo_android_chipset_property_ro_product_board], + &chipsets[cpuinfo_android_chipset_property_ro_board_platform], + &chipsets + [cpuinfo_android_chipset_property_ro_mediatek_platform], + &chipsets[cpuinfo_android_chipset_property_ro_chipname]); + case cpuinfo_arm_chipset_vendor_hisilicon: + return disambiguate_hisilicon_chipset( + &chipsets + [cpuinfo_android_chipset_property_proc_cpuinfo_hardware], + &chipsets[cpuinfo_android_chipset_property_ro_product_board], + &chipsets[cpuinfo_android_chipset_property_ro_board_platform]); + case cpuinfo_arm_chipset_vendor_amlogic: + return disambiguate_amlogic_chipset( + &chipsets + [cpuinfo_android_chipset_property_proc_cpuinfo_hardware], + &chipsets[cpuinfo_android_chipset_property_ro_board_platform]); + case cpuinfo_arm_chipset_vendor_marvell: + return disambiguate_marvell_chipset( + &chipsets + [cpuinfo_android_chipset_property_proc_cpuinfo_hardware], + &chipsets[cpuinfo_android_chipset_property_ro_product_board], + &chipsets[cpuinfo_android_chipset_property_ro_chipname]); + case cpuinfo_arm_chipset_vendor_rockchip: + return disambiguate_rockchip_chipset( + &chipsets + [cpuinfo_android_chipset_property_proc_cpuinfo_hardware], + &chipsets[cpuinfo_android_chipset_property_ro_product_board], + &chipsets[cpuinfo_android_chipset_property_ro_board_platform]); + case cpuinfo_arm_chipset_vendor_spreadtrum: + return disambiguate_spreadtrum_chipset( + &chipsets + [cpuinfo_android_chipset_property_proc_cpuinfo_hardware], + &chipsets[cpuinfo_android_chipset_property_ro_product_board], + &chipsets[cpuinfo_android_chipset_property_ro_board_platform], + &chipsets[cpuinfo_android_chipset_property_ro_chipname]); + default: + cpuinfo_log_error( + "chipset detection failed: " + "could not disambiguate different chipsets reported in different system properties"); + /* chipset variable contains + * valid, but inconsistent + * chipset information, + * overwrite it */ + chipset = (struct cpuinfo_arm_chipset){ + .vendor = cpuinfo_arm_chipset_vendor_unknown, + .series = cpuinfo_arm_chipset_series_unknown, + }; + goto finish; } } } - - finish: - return chipset; } + +finish: + return chipset; +} #else /* !defined(__ANDROID__) */ - /* - * Fix commonly misreported Broadcom BCM models on Raspberry Pi boards. - * - * @param[in,out] chipset - chipset name to fix. - * @param[in] revision - /proc/cpuinfo Revision string. - */ - void cpuinfo_arm_fixup_raspberry_pi_chipset( - struct cpuinfo_arm_chipset chipset[restrict static 1], - const char revision[restrict static CPUINFO_REVISION_VALUE_MAX]) - { - const size_t revision_length = strnlen(revision, CPUINFO_REVISION_VALUE_MAX); +/* + * Fix commonly misreported Broadcom BCM models on Raspberry Pi boards. + * + * @param[in,out] chipset - chipset name to fix. + * @param[in] revision - /proc/cpuinfo Revision string. + */ +void cpuinfo_arm_fixup_raspberry_pi_chipset( + struct cpuinfo_arm_chipset chipset[restrict static 1], + const char revision[restrict static CPUINFO_REVISION_VALUE_MAX]) { + const size_t revision_length = strnlen(revision, CPUINFO_REVISION_VALUE_MAX); - /* Parse revision codes according to https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md */ - #if CPUINFO_ARCH_ARM - if (revision_length == 4) { - /* - * Old-style revision codes. - * All Raspberry Pi models with old-style revision code use Broadcom BCM2835. - */ +/* Parse revision codes according to + * https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md + */ +#if CPUINFO_ARCH_ARM + if (revision_length == 4) { + /* + * Old-style revision codes. + * All Raspberry Pi models with old-style revision code use + * Broadcom BCM2835. + */ - /* BCM2835 often misreported as BCM2708 */ - if (chipset->model == 2708) { - chipset->model = 2835; - } - return; - } - #endif - if ((size_t) (revision_length - 5) <= (size_t) (8 - 5) /* 5 <= length(revision) <= 8 */) { - /* New-style revision codes */ + /* BCM2835 often misreported as BCM2708 */ + if (chipset->model == 2708) { + chipset->model = 2835; + } + return; + } +#endif + if ((size_t)(revision_length - 5) <= (size_t)(8 - 5) /* 5 <= length(revision) <= 8 */) { + /* New-style revision codes */ - uint32_t model = 0; - switch (revision[revision_length - 4]) { - case '0': - /* BCM2835 */ - model = 2835; - break; - case '1': - /* BCM2836 */ - model = 2836; - break; - case '2': - /* BCM2837 */ - model = 2837; - break; - case '3': - /* BCM2711 */ - model = 2711; - break; - } + uint32_t model = 0; + switch (revision[revision_length - 4]) { + case '0': + /* BCM2835 */ + model = 2835; + break; + case '1': + /* BCM2836 */ + model = 2836; + break; + case '2': + /* BCM2837 */ + model = 2837; + break; + case '3': + /* BCM2711 */ + model = 2711; + break; + } - if (model != 0) { - chipset->model = model; - chipset->suffix[0] = 0; - } + if (model != 0) { + chipset->model = model; + chipset->suffix[0] = 0; } } +} - /* - * Decodes chipset name from /proc/cpuinfo Hardware string. - * For some chipsets, the function relies frequency and on number of cores for chipset detection. - * - * @param[in] hardware - /proc/cpuinfo Hardware string. - * @param cores - number of cores in the chipset. - * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. - * - * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` vendor - * and series identifiers. - */ - struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset( - const char hardware[restrict static CPUINFO_HARDWARE_VALUE_MAX], - const char revision[restrict static CPUINFO_REVISION_VALUE_MAX], - uint32_t cores, - uint32_t max_cpu_freq_max) - { - struct cpuinfo_arm_chipset chipset = - cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_hardware( - hardware, cores, max_cpu_freq_max, false); - if (chipset.vendor == cpuinfo_arm_chipset_vendor_unknown) { - cpuinfo_log_warning( - "chipset detection failed: /proc/cpuinfo Hardware string did not match known signatures"); - } else if (chipset.vendor == cpuinfo_arm_chipset_vendor_broadcom) { - /* Raspberry Pi kernel reports bogus chipset models; detect chipset from RPi revision */ - cpuinfo_arm_fixup_raspberry_pi_chipset(&chipset, revision); - } else { - cpuinfo_arm_fixup_chipset(&chipset, cores, max_cpu_freq_max); - } - return chipset; +/* + * Decodes chipset name from /proc/cpuinfo Hardware string. + * For some chipsets, the function relies frequency and on number of cores for + * chipset detection. + * + * @param[in] hardware - /proc/cpuinfo Hardware string. + * @param cores - number of cores in the chipset. + * @param max_cpu_freq_max - maximum of + * /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. + * + * @returns Decoded chipset name. If chipset could not be decoded, the resulting + * structure would use `unknown` vendor and series identifiers. + */ +struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset( + const char hardware[restrict static CPUINFO_HARDWARE_VALUE_MAX], + const char revision[restrict static CPUINFO_REVISION_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max) { + struct cpuinfo_arm_chipset chipset = + cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_hardware(hardware, cores, max_cpu_freq_max, false); + if (chipset.vendor == cpuinfo_arm_chipset_vendor_unknown) { + cpuinfo_log_warning( + "chipset detection failed: /proc/cpuinfo Hardware string did not match known signatures"); + } else if (chipset.vendor == cpuinfo_arm_chipset_vendor_broadcom) { + /* Raspberry Pi kernel reports bogus chipset models; detect + * chipset from RPi revision */ + cpuinfo_arm_fixup_raspberry_pi_chipset(&chipset, revision); + } else { + cpuinfo_arm_fixup_chipset(&chipset, cores, max_cpu_freq_max); } + return chipset; +} #endif diff --git a/3rdparty/cpuinfo/src/arm/linux/clusters.c b/3rdparty/cpuinfo/src/arm/linux/clusters.c index 430773d1d1..8dd452a7f1 100644 --- a/3rdparty/cpuinfo/src/arm/linux/clusters.c +++ b/3rdparty/cpuinfo/src/arm/linux/clusters.c @@ -1,63 +1,74 @@ -#include #include +#include #include #include -#include #include +#include #if defined(__ANDROID__) - #include +#include #endif #include #include -#include #include #include +#include static inline bool bitmask_all(uint32_t bitfield, uint32_t mask) { return (bitfield & mask) == mask; } /* - * Assigns logical processors to clusters of cores using heuristic based on the typical configuration of clusters for - * 5, 6, 8, and 10 cores: + * Assigns logical processors to clusters of cores using heuristic based on the + * typical configuration of clusters for 5, 6, 8, and 10 cores: * - 5 cores (ARM32 Android only): 2 clusters of 4+1 cores * - 6 cores: 2 clusters of 4+2 cores * - 8 cores: 2 clusters of 4+4 cores * - 10 cores: 3 clusters of 4+4+2 cores * - * The function must be called after parsing OS-provided information on core clusters. - * Its purpose is to detect clusters of cores when OS-provided information is lacking or incomplete, i.e. - * - Linux kernel is not configured to report information in sysfs topology leaf. - * - Linux kernel reports topology information only for online cores, and only cores on one cluster are online, e.g.: - * - Exynos 8890 has 8 cores in 4+4 clusters, but only the first cluster of 4 cores is reported, and cluster - * configuration of logical processors 4-7 is not reported (all remaining processors 4-7 form cluster 1) - * - MT6797 has 10 cores in 4+4+2, but only the first cluster of 4 cores is reported, and cluster configuration - * of logical processors 4-9 is not reported (processors 4-7 form cluster 1, and processors 8-9 form cluster 2). + * The function must be called after parsing OS-provided information on core + * clusters. Its purpose is to detect clusters of cores when OS-provided + * information is lacking or incomplete, i.e. + * - Linux kernel is not configured to report information in sysfs topology + * leaf. + * - Linux kernel reports topology information only for online cores, and only + * cores on one cluster are online, e.g.: + * - Exynos 8890 has 8 cores in 4+4 clusters, but only the first cluster of 4 + * cores is reported, and cluster configuration of logical processors 4-7 is not + * reported (all remaining processors 4-7 form cluster 1) + * - MT6797 has 10 cores in 4+4+2, but only the first cluster of 4 cores is + * reported, and cluster configuration of logical processors 4-9 is not reported + * (processors 4-7 form cluster 1, and processors 8-9 form cluster 2). * - * Heuristic assignment of processors to the above pre-defined clusters fails if such assignment would contradict - * information provided by the operating system: - * - Any of the OS-reported processor clusters is different than the corresponding heuristic cluster. - * - Processors in a heuristic cluster have no OS-provided cluster siblings information, but have known and different - * minimum/maximum frequency. - * - Processors in a heuristic cluster have no OS-provided cluster siblings information, but have known and different - * MIDR components. + * Heuristic assignment of processors to the above pre-defined clusters fails if + * such assignment would contradict information provided by the operating + * system: + * - Any of the OS-reported processor clusters is different than the + * corresponding heuristic cluster. + * - Processors in a heuristic cluster have no OS-provided cluster siblings + * information, but have known and different minimum/maximum frequency. + * - Processors in a heuristic cluster have no OS-provided cluster siblings + * information, but have known and different MIDR components. * - * If the heuristic assignment of processors to clusters of cores fails, all processors' clusters are unchanged. + * If the heuristic assignment of processors to clusters of cores fails, all + * processors' clusters are unchanged. * - * @param usable_processors - number of processors in the @p processors array with CPUINFO_LINUX_FLAG_VALID flags. + * @param usable_processors - number of processors in the @p processors array + * with CPUINFO_LINUX_FLAG_VALID flags. * @param max_processors - number of elements in the @p processors array. - * @param[in,out] processors - processor descriptors with pre-parsed POSSIBLE and PRESENT flags, minimum/maximum - * frequency, MIDR information, and core cluster (package siblings list) information. + * @param[in,out] processors - processor descriptors with pre-parsed POSSIBLE + * and PRESENT flags, minimum/maximum frequency, MIDR information, and core + * cluster (package siblings list) information. * - * @retval true if the heuristic successfully assigned all processors into clusters of cores. - * @retval false if known details about processors contradict the heuristic configuration of core clusters. + * @retval true if the heuristic successfully assigned all processors into + * clusters of cores. + * @retval false if known details about processors contradict the heuristic + * configuration of core clusters. */ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( uint32_t usable_processors, uint32_t max_processors, - struct cpuinfo_arm_linux_processor processors[restrict static max_processors]) -{ + struct cpuinfo_arm_linux_processor processors[restrict static max_processors]) { uint32_t cluster_processors[3]; switch (usable_processors) { case 10: @@ -76,8 +87,9 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( #if defined(__ANDROID__) && CPUINFO_ARCH_ARM case 5: /* - * The only processor with 5 cores is Leadcore L1860C (ARMv7, mobile), - * but this configuration is not too unreasonable for a virtualized ARM server. + * The only processor with 5 cores is Leadcore L1860C + * (ARMv7, mobile), but this configuration is not too + * unreasonable for a virtualized ARM server. */ cluster_processors[0] = 4; cluster_processors[1] = 1; @@ -89,7 +101,8 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( /* * Assignment of processors to core clusters is done in two passes: - * 1. Verify that the clusters proposed by heuristic are compatible with known details about processors. + * 1. Verify that the clusters proposed by heuristic are compatible with + * known details about processors. * 2. If verification passed, update core clusters for the processors. */ @@ -100,16 +113,22 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( for (uint32_t i = 0; i < max_processors; i++) { if (bitmask_all(processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { if (expected_cluster_processors == 0) { - /* Expect this processor to start a new cluster */ + /* Expect this processor to start a new cluster + */ expected_cluster_exists = !!(processors[i].flags & CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER); if (expected_cluster_exists) { if (processors[i].package_leader_id != i) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "processor %"PRIu32" is expected to start a new cluster #%"PRIu32" with %"PRIu32" cores, " - "but system siblings lists reported it as a sibling of processor %"PRIu32, - i, cluster, cluster_processors[cluster], processors[i].package_leader_id); + "processor %" PRIu32 + " is expected to start a new cluster #%" PRIu32 " with %" PRIu32 + " cores, " + "but system siblings lists reported it as a sibling of processor %" PRIu32, + i, + cluster, + cluster_processors[cluster], + processors[i].package_leader_id); return false; } } else { @@ -119,48 +138,73 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( cluster_start = i; expected_cluster_processors = cluster_processors[cluster++]; } else { - /* Expect this processor to belong to the same cluster as processor */ + /* Expect this processor to belong to the same + * cluster as processor */ if (expected_cluster_exists) { /* - * The cluster suggested by the heuristic was already parsed from system siblings lists. - * For all processors we expect in the cluster, check that: - * - They have pre-assigned cluster from siblings lists (CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER flag). - * - They were assigned to the same cluster based on siblings lists - * (package_leader_id points to the first processor in the cluster). + * The cluster suggested by the + * heuristic was already parsed from + * system siblings lists. For all + * processors we expect in the cluster, + * check that: + * - They have pre-assigned cluster from + * siblings lists + * (CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER + * flag). + * - They were assigned to the same + * cluster based on siblings lists + * (package_leader_id points to the + * first processor in the cluster). */ if ((processors[i].flags & CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER) == 0) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "processor %"PRIu32" is expected to belong to the cluster of processor %"PRIu32", " - "but system siblings lists did not report it as a sibling of processor %"PRIu32, - i, cluster_start, cluster_start); + "processor %" PRIu32 + " is expected to belong to the cluster of processor %" PRIu32 + ", " + "but system siblings lists did not report it as a sibling of processor %" PRIu32, + i, + cluster_start, + cluster_start); return false; } if (processors[i].package_leader_id != cluster_start) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "processor %"PRIu32" is expected to belong to the cluster of processor %"PRIu32", " - "but system siblings lists reported it to belong to the cluster of processor %"PRIu32, - i, cluster_start, cluster_start); + "processor %" PRIu32 + " is expected to belong to the cluster of processor %" PRIu32 + ", " + "but system siblings lists reported it to belong to the cluster of processor %" PRIu32, + i, + cluster_start, + cluster_start); return false; } } else { /* - * The cluster suggest by the heuristic was not parsed from system siblings lists. - * For all processors we expect in the cluster, check that: - * - They have no pre-assigned cluster from siblings lists. - * - If their min/max CPU frequency is known, it is the same. - * - If any part of their MIDR (Implementer, Variant, Part, Revision) is known, it is the same. + * The cluster suggest by the heuristic + * was not parsed from system siblings + * lists. For all processors we expect + * in the cluster, check that: + * - They have no pre-assigned cluster + * from siblings lists. + * - If their min/max CPU frequency is + * known, it is the same. + * - If any part of their MIDR + * (Implementer, Variant, Part, + * Revision) is known, it is the same. */ if (processors[i].flags & CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "processor %"PRIu32" is expected to be unassigned to any cluster, " - "but system siblings lists reported it to belong to the cluster of processor %"PRIu32, - i, processors[i].package_leader_id); + "processor %" PRIu32 + " is expected to be unassigned to any cluster, " + "but system siblings lists reported it to belong to the cluster of processor %" PRIu32, + i, + processors[i].package_leader_id); return false; } @@ -169,8 +213,13 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( if (cluster_min_frequency != processors[i].min_frequency) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "minimum frequency of processor %"PRIu32" (%"PRIu32" KHz) is different than of its expected cluster (%"PRIu32" KHz)", - i, processors[i].min_frequency, cluster_min_frequency); + "minimum frequency of processor %" PRIu32 + " (%" PRIu32 + " KHz) is different than of its expected cluster (%" PRIu32 + " KHz)", + i, + processors[i].min_frequency, + cluster_min_frequency); return false; } } else { @@ -184,8 +233,13 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( if (cluster_max_frequency != processors[i].max_frequency) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "maximum frequency of processor %"PRIu32" (%"PRIu32" KHz) is different than of its expected cluster (%"PRIu32" KHz)", - i, processors[i].max_frequency, cluster_max_frequency); + "maximum frequency of processor %" PRIu32 + " (%" PRIu32 + " KHz) is different than of its expected cluster (%" PRIu32 + " KHz)", + i, + processors[i].max_frequency, + cluster_max_frequency); return false; } } else { @@ -196,41 +250,61 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( if (processors[i].flags & CPUINFO_ARM_LINUX_VALID_IMPLEMENTER) { if (cluster_flags & CPUINFO_ARM_LINUX_VALID_IMPLEMENTER) { - if ((cluster_midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK)) { + if ((cluster_midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) != + (processors[i].midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK)) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "CPU Implementer of processor %"PRIu32" (0x%02"PRIx32") is different than of its expected cluster (0x%02"PRIx32")", - i, midr_get_implementer(processors[i].midr), midr_get_implementer(cluster_midr)); + "CPU Implementer of processor %" PRIu32 + " (0x%02" PRIx32 + ") is different than of its expected cluster (0x%02" PRIx32 + ")", + i, + midr_get_implementer(processors[i].midr), + midr_get_implementer(cluster_midr)); return false; } } else { - cluster_midr = midr_copy_implementer(cluster_midr, processors[i].midr); + cluster_midr = + midr_copy_implementer(cluster_midr, processors[i].midr); cluster_flags |= CPUINFO_ARM_LINUX_VALID_IMPLEMENTER; } } if (processors[i].flags & CPUINFO_ARM_LINUX_VALID_VARIANT) { if (cluster_flags & CPUINFO_ARM_LINUX_VALID_VARIANT) { - if ((cluster_midr & CPUINFO_ARM_MIDR_VARIANT_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_VARIANT_MASK)) { + if ((cluster_midr & CPUINFO_ARM_MIDR_VARIANT_MASK) != + (processors[i].midr & CPUINFO_ARM_MIDR_VARIANT_MASK)) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "CPU Variant of processor %"PRIu32" (0x%"PRIx32") is different than of its expected cluster (0x%"PRIx32")", - i, midr_get_variant(processors[i].midr), midr_get_variant(cluster_midr)); + "CPU Variant of processor %" PRIu32 + " (0x%" PRIx32 + ") is different than of its expected cluster (0x%" PRIx32 + ")", + i, + midr_get_variant(processors[i].midr), + midr_get_variant(cluster_midr)); return false; } } else { - cluster_midr = midr_copy_variant(cluster_midr, processors[i].midr); + cluster_midr = + midr_copy_variant(cluster_midr, processors[i].midr); cluster_flags |= CPUINFO_ARM_LINUX_VALID_VARIANT; } } if (processors[i].flags & CPUINFO_ARM_LINUX_VALID_PART) { if (cluster_flags & CPUINFO_ARM_LINUX_VALID_PART) { - if ((cluster_midr & CPUINFO_ARM_MIDR_PART_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_PART_MASK)) { + if ((cluster_midr & CPUINFO_ARM_MIDR_PART_MASK) != + (processors[i].midr & CPUINFO_ARM_MIDR_PART_MASK)) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "CPU Part of processor %"PRIu32" (0x%03"PRIx32") is different than of its expected cluster (0x%03"PRIx32")", - i, midr_get_part(processors[i].midr), midr_get_part(cluster_midr)); + "CPU Part of processor %" PRIu32 + " (0x%03" PRIx32 + ") is different than of its expected cluster (0x%03" PRIx32 + ")", + i, + midr_get_part(processors[i].midr), + midr_get_part(cluster_midr)); return false; } } else { @@ -241,15 +315,22 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( if (processors[i].flags & CPUINFO_ARM_LINUX_VALID_REVISION) { if (cluster_flags & CPUINFO_ARM_LINUX_VALID_REVISION) { - if ((cluster_midr & CPUINFO_ARM_MIDR_REVISION_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_REVISION_MASK)) { + if ((cluster_midr & CPUINFO_ARM_MIDR_REVISION_MASK) != + (processors[i].midr & CPUINFO_ARM_MIDR_REVISION_MASK)) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "CPU Revision of processor %"PRIu32" (0x%"PRIx32") is different than of its expected cluster (0x%"PRIx32")", - i, midr_get_revision(cluster_midr), midr_get_revision(processors[i].midr)); + "CPU Revision of processor %" PRIu32 + " (0x%" PRIx32 + ") is different than of its expected cluster (0x%" PRIx32 + ")", + i, + midr_get_revision(cluster_midr), + midr_get_revision(processors[i].midr)); return false; } } else { - cluster_midr = midr_copy_revision(cluster_midr, processors[i].midr); + cluster_midr = + midr_copy_revision(cluster_midr, processors[i].midr); cluster_flags |= CPUINFO_ARM_LINUX_VALID_REVISION; } } @@ -265,16 +346,21 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( for (uint32_t i = 0; i < max_processors; i++) { if (bitmask_all(processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { if (expected_cluster_processors == 0) { - /* Expect this processor to start a new cluster */ + /* Expect this processor to start a new cluster + */ cluster_start = i; expected_cluster_processors = cluster_processors[cluster++]; } else { - /* Expect this processor to belong to the same cluster as processor */ + /* Expect this processor to belong to the same + * cluster as processor */ if (!(processors[i].flags & CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER)) { - cpuinfo_log_debug("assigned processor %"PRIu32" to cluster of processor %"PRIu32" based on heuristic", - i, cluster_start); + cpuinfo_log_debug( + "assigned processor %" PRIu32 " to cluster of processor %" PRIu32 + " based on heuristic", + i, + cluster_start); } processors[i].package_leader_id = cluster_start; @@ -291,38 +377,49 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( * - Clusters detected from OS-provided information are unchanged: * - Processors assigned to these clusters stay assigned to the same clusters * - No new processors are added to these clusters - * - Processors without pre-assigned cluster are clustered in one sequential scan: - * - If known details (min/max frequency, MIDR components) of a processor are compatible with a preceding - * processor, without pre-assigned cluster, the processor is assigned to the cluster of the preceding processor. - * - If known details (min/max frequency, MIDR components) of a processor are not compatible with a preceding - * processor, the processor is assigned to a newly created cluster. + * - Processors without pre-assigned cluster are clustered in one sequential + * scan: + * - If known details (min/max frequency, MIDR components) of a processor are + * compatible with a preceding processor, without pre-assigned cluster, the + * processor is assigned to the cluster of the preceding processor. + * - If known details (min/max frequency, MIDR components) of a processor are + * not compatible with a preceding processor, the processor is assigned to a + * newly created cluster. * - * The function must be called after parsing OS-provided information on core clusters, and usually is called only - * if heuristic assignment of processors to clusters (cpuinfo_arm_linux_cluster_processors_by_heuristic) failed. + * The function must be called after parsing OS-provided information on core + * clusters, and usually is called only if heuristic assignment of processors to + * clusters (cpuinfo_arm_linux_cluster_processors_by_heuristic) failed. * - * Its purpose is to detect clusters of cores when OS-provided information is lacking or incomplete, i.e. - * - Linux kernel is not configured to report information in sysfs topology leaf. - * - Linux kernel reports topology information only for online cores, and all cores on some of the clusters are offline. + * Its purpose is to detect clusters of cores when OS-provided information is + * lacking or incomplete, i.e. + * - Linux kernel is not configured to report information in sysfs topology + * leaf. + * - Linux kernel reports topology information only for online cores, and all + * cores on some of the clusters are offline. * - * Sequential assignment of processors to clusters always succeeds, and upon exit, all usable processors in the + * Sequential assignment of processors to clusters always succeeds, and upon + * exit, all usable processors in the * @p processors array have cluster information. * * @param max_processors - number of elements in the @p processors array. - * @param[in,out] processors - processor descriptors with pre-parsed POSSIBLE and PRESENT flags, minimum/maximum - * frequency, MIDR information, and core cluster (package siblings list) information. + * @param[in,out] processors - processor descriptors with pre-parsed POSSIBLE + * and PRESENT flags, minimum/maximum frequency, MIDR information, and core + * cluster (package siblings list) information. * - * @retval true if the heuristic successfully assigned all processors into clusters of cores. - * @retval false if known details about processors contradict the heuristic configuration of core clusters. + * @retval true if the heuristic successfully assigned all processors into + * clusters of cores. + * @retval false if known details about processors contradict the heuristic + * configuration of core clusters. */ void cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan( uint32_t max_processors, - struct cpuinfo_arm_linux_processor processors[restrict static max_processors]) -{ + struct cpuinfo_arm_linux_processor processors[restrict static max_processors]) { uint32_t cluster_flags = 0; uint32_t cluster_processors = 0; uint32_t cluster_start, cluster_midr, cluster_max_frequency, cluster_min_frequency; for (uint32_t i = 0; i < max_processors; i++) { - if ((processors[i].flags & (CPUINFO_LINUX_FLAG_VALID | CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER)) == CPUINFO_LINUX_FLAG_VALID) { + if ((processors[i].flags & (CPUINFO_LINUX_FLAG_VALID | CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER)) == + CPUINFO_LINUX_FLAG_VALID) { if (cluster_processors == 0) { goto new_cluster; } @@ -331,9 +428,14 @@ void cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan( if (cluster_flags & CPUINFO_LINUX_FLAG_MIN_FREQUENCY) { if (cluster_min_frequency != processors[i].min_frequency) { cpuinfo_log_info( - "minimum frequency of processor %"PRIu32" (%"PRIu32" KHz) is different than of preceding cluster (%"PRIu32" KHz); " - "processor %"PRIu32" starts to a new cluster", - i, processors[i].min_frequency, cluster_min_frequency, i); + "minimum frequency of processor %" PRIu32 " (%" PRIu32 + " KHz) is different than of preceding cluster (%" PRIu32 + " KHz); " + "processor %" PRIu32 " starts to a new cluster", + i, + processors[i].min_frequency, + cluster_min_frequency, + i); goto new_cluster; } } else { @@ -346,9 +448,14 @@ void cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan( if (cluster_flags & CPUINFO_LINUX_FLAG_MAX_FREQUENCY) { if (cluster_max_frequency != processors[i].max_frequency) { cpuinfo_log_debug( - "maximum frequency of processor %"PRIu32" (%"PRIu32" KHz) is different than of preceding cluster (%"PRIu32" KHz); " - "processor %"PRIu32" starts a new cluster", - i, processors[i].max_frequency, cluster_max_frequency, i); + "maximum frequency of processor %" PRIu32 " (%" PRIu32 + " KHz) is different than of preceding cluster (%" PRIu32 + " KHz); " + "processor %" PRIu32 " starts a new cluster", + i, + processors[i].max_frequency, + cluster_max_frequency, + i); goto new_cluster; } } else { @@ -359,11 +466,17 @@ void cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan( if (processors[i].flags & CPUINFO_ARM_LINUX_VALID_IMPLEMENTER) { if (cluster_flags & CPUINFO_ARM_LINUX_VALID_IMPLEMENTER) { - if ((cluster_midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK)) { + if ((cluster_midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) != + (processors[i].midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK)) { cpuinfo_log_debug( - "CPU Implementer of processor %"PRIu32" (0x%02"PRIx32") is different than of preceding cluster (0x%02"PRIx32"); " - "processor %"PRIu32" starts to a new cluster", - i, midr_get_implementer(processors[i].midr), midr_get_implementer(cluster_midr), i); + "CPU Implementer of processor %" PRIu32 " (0x%02" PRIx32 + ") is different than of preceding cluster (0x%02" PRIx32 + "); " + "processor %" PRIu32 " starts to a new cluster", + i, + midr_get_implementer(processors[i].midr), + midr_get_implementer(cluster_midr), + i); goto new_cluster; } } else { @@ -374,11 +487,17 @@ void cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan( if (processors[i].flags & CPUINFO_ARM_LINUX_VALID_VARIANT) { if (cluster_flags & CPUINFO_ARM_LINUX_VALID_VARIANT) { - if ((cluster_midr & CPUINFO_ARM_MIDR_VARIANT_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_VARIANT_MASK)) { + if ((cluster_midr & CPUINFO_ARM_MIDR_VARIANT_MASK) != + (processors[i].midr & CPUINFO_ARM_MIDR_VARIANT_MASK)) { cpuinfo_log_debug( - "CPU Variant of processor %"PRIu32" (0x%"PRIx32") is different than of its expected cluster (0x%"PRIx32")" - "processor %"PRIu32" starts to a new cluster", - i, midr_get_variant(processors[i].midr), midr_get_variant(cluster_midr), i); + "CPU Variant of processor %" PRIu32 " (0x%" PRIx32 + ") is different than of its expected cluster (0x%" PRIx32 + ")" + "processor %" PRIu32 " starts to a new cluster", + i, + midr_get_variant(processors[i].midr), + midr_get_variant(cluster_midr), + i); goto new_cluster; } } else { @@ -389,11 +508,17 @@ void cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan( if (processors[i].flags & CPUINFO_ARM_LINUX_VALID_PART) { if (cluster_flags & CPUINFO_ARM_LINUX_VALID_PART) { - if ((cluster_midr & CPUINFO_ARM_MIDR_PART_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_PART_MASK)) { + if ((cluster_midr & CPUINFO_ARM_MIDR_PART_MASK) != + (processors[i].midr & CPUINFO_ARM_MIDR_PART_MASK)) { cpuinfo_log_debug( - "CPU Part of processor %"PRIu32" (0x%03"PRIx32") is different than of its expected cluster (0x%03"PRIx32")" - "processor %"PRIu32" starts to a new cluster", - i, midr_get_part(processors[i].midr), midr_get_part(cluster_midr), i); + "CPU Part of processor %" PRIu32 " (0x%03" PRIx32 + ") is different than of its expected cluster (0x%03" PRIx32 + ")" + "processor %" PRIu32 " starts to a new cluster", + i, + midr_get_part(processors[i].midr), + midr_get_part(cluster_midr), + i); goto new_cluster; } } else { @@ -404,11 +529,17 @@ void cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan( if (processors[i].flags & CPUINFO_ARM_LINUX_VALID_REVISION) { if (cluster_flags & CPUINFO_ARM_LINUX_VALID_REVISION) { - if ((cluster_midr & CPUINFO_ARM_MIDR_REVISION_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_REVISION_MASK)) { + if ((cluster_midr & CPUINFO_ARM_MIDR_REVISION_MASK) != + (processors[i].midr & CPUINFO_ARM_MIDR_REVISION_MASK)) { cpuinfo_log_debug( - "CPU Revision of processor %"PRIu32" (0x%"PRIx32") is different than of its expected cluster (0x%"PRIx32")" - "processor %"PRIu32" starts to a new cluster", - i, midr_get_revision(cluster_midr), midr_get_revision(processors[i].midr), i); + "CPU Revision of processor %" PRIu32 " (0x%" PRIx32 + ") is different than of its expected cluster (0x%" PRIx32 + ")" + "processor %" PRIu32 " starts to a new cluster", + i, + midr_get_revision(cluster_midr), + midr_get_revision(processors[i].midr), + i); goto new_cluster; } } else { @@ -417,21 +548,26 @@ void cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan( } } - /* All checks passed, attach processor to the preceding cluster */ + /* All checks passed, attach processor to the preceding + * cluster */ cluster_processors++; processors[i].package_leader_id = cluster_start; processors[i].flags |= CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER; - cpuinfo_log_debug("assigned processor %"PRIu32" to preceding cluster of processor %"PRIu32, i, cluster_start); + cpuinfo_log_debug( + "assigned processor %" PRIu32 " to preceding cluster of processor %" PRIu32, + i, + cluster_start); continue; -new_cluster: + new_cluster: /* Create a new cluster starting with processor i */ cluster_start = i; processors[i].package_leader_id = i; processors[i].flags |= CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER; cluster_processors = 1; - /* Copy known information from processor to cluster, and set the flags accordingly */ + /* Copy known information from processor to cluster, and + * set the flags accordingly */ cluster_flags = 0; if (processors[i].flags & CPUINFO_LINUX_FLAG_MIN_FREQUENCY) { cluster_min_frequency = processors[i].min_frequency; @@ -463,27 +599,30 @@ new_cluster: /* * Counts the number of logical processors in each core cluster. - * This function should be called after all processors are assigned to core clusters. + * This function should be called after all processors are assigned to core + * clusters. * * @param max_processors - number of elements in the @p processors array. - * @param[in,out] processors - processor descriptors with pre-parsed POSSIBLE and PRESENT flags, - * and decoded core cluster (package_leader_id) information. - * The function expects the value of processors[i].package_processor_count to be zero. - * Upon return, processors[i].package_processor_count will contain the number of logical + * @param[in,out] processors - processor descriptors with pre-parsed POSSIBLE + * and PRESENT flags, and decoded core cluster (package_leader_id) information. + * The function expects the value of + * processors[i].package_processor_count to be zero. Upon return, + * processors[i].package_processor_count will contain the number of logical * processors in the respective core cluster. */ void cpuinfo_arm_linux_count_cluster_processors( uint32_t max_processors, - struct cpuinfo_arm_linux_processor processors[restrict static max_processors]) -{ - /* First pass: accumulate the number of processors at the group leader's package_processor_count */ + struct cpuinfo_arm_linux_processor processors[restrict static max_processors]) { + /* First pass: accumulate the number of processors at the group leader's + * package_processor_count */ for (uint32_t i = 0; i < max_processors; i++) { if (bitmask_all(processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { const uint32_t package_leader_id = processors[i].package_leader_id; processors[package_leader_id].package_processor_count += 1; } } - /* Second pass: copy the package_processor_count from the group leader processor */ + /* Second pass: copy the package_processor_count from the group leader + * processor */ for (uint32_t i = 0; i < max_processors; i++) { if (bitmask_all(processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { const uint32_t package_leader_id = processors[i].package_leader_id; diff --git a/3rdparty/cpuinfo/src/arm/linux/cp.h b/3rdparty/cpuinfo/src/arm/linux/cp.h index 0abd7d61e8..3f084d6665 100644 --- a/3rdparty/cpuinfo/src/arm/linux/cp.h +++ b/3rdparty/cpuinfo/src/arm/linux/cp.h @@ -1,50 +1,49 @@ #include - #if CPUINFO_MOCK - extern uint32_t cpuinfo_arm_fpsid; - extern uint32_t cpuinfo_arm_mvfr0; - extern uint32_t cpuinfo_arm_wcid; +extern uint32_t cpuinfo_arm_fpsid; +extern uint32_t cpuinfo_arm_mvfr0; +extern uint32_t cpuinfo_arm_wcid; - static inline uint32_t read_fpsid(void) { - return cpuinfo_arm_fpsid; - } +static inline uint32_t read_fpsid(void) { + return cpuinfo_arm_fpsid; +} - static inline uint32_t read_mvfr0(void) { - return cpuinfo_arm_mvfr0; - } +static inline uint32_t read_mvfr0(void) { + return cpuinfo_arm_mvfr0; +} - static inline uint32_t read_wcid(void) { - return cpuinfo_arm_wcid; - } +static inline uint32_t read_wcid(void) { + return cpuinfo_arm_wcid; +} #else - #if !defined(__ARM_ARCH_7A__) && !defined(__ARM_ARCH_8A__) && !(defined(__ARM_ARCH) && (__ARM_ARCH >= 7)) - /* - * CoProcessor 10 is inaccessible from user mode since ARMv7, - * and clang refuses to compile inline assembly when targeting ARMv7+ - */ - static inline uint32_t read_fpsid(void) { - uint32_t fpsid; - __asm__ __volatile__("MRC p10, 0x7, %[fpsid], cr0, cr0, 0" : [fpsid] "=r" (fpsid)); - return fpsid; - } +#if !defined(__ARM_ARCH_7A__) && !defined(__ARM_ARCH_8A__) && !(defined(__ARM_ARCH) && (__ARM_ARCH >= 7)) +/* + * CoProcessor 10 is inaccessible from user mode since ARMv7, + * and clang refuses to compile inline assembly when targeting ARMv7+ + */ +static inline uint32_t read_fpsid(void) { + uint32_t fpsid; + __asm__ __volatile__("MRC p10, 0x7, %[fpsid], cr0, cr0, 0" : [fpsid] "=r"(fpsid)); + return fpsid; +} - static inline uint32_t read_mvfr0(void) { - uint32_t mvfr0; - __asm__ __volatile__("MRC p10, 0x7, %[mvfr0], cr7, cr0, 0" : [mvfr0] "=r" (mvfr0)); - return mvfr0; - } - #endif - #if !defined(__ARM_ARCH_8A__) && !(defined(__ARM_ARCH) && (__ARM_ARCH >= 8)) - /* - * In ARMv8, AArch32 state supports only conceptual coprocessors CP10, CP11, CP14, and CP15. - * AArch64 does not support the concept of coprocessors. - * and clang refuses to compile inline assembly when targeting ARMv8+ - */ - static inline uint32_t read_wcid(void) { - uint32_t wcid; - __asm__ __volatile__("MRC p1, 0, %[wcid], c0, c0" : [wcid] "=r" (wcid)); - return wcid; - } - #endif +static inline uint32_t read_mvfr0(void) { + uint32_t mvfr0; + __asm__ __volatile__("MRC p10, 0x7, %[mvfr0], cr7, cr0, 0" : [mvfr0] "=r"(mvfr0)); + return mvfr0; +} +#endif +#if !defined(__ARM_ARCH_8A__) && !(defined(__ARM_ARCH) && (__ARM_ARCH >= 8)) +/* + * In ARMv8, AArch32 state supports only conceptual coprocessors CP10, CP11, + * CP14, and CP15. AArch64 does not support the concept of coprocessors. and + * clang refuses to compile inline assembly when targeting ARMv8+ + */ +static inline uint32_t read_wcid(void) { + uint32_t wcid; + __asm__ __volatile__("MRC p1, 0, %[wcid], c0, c0" : [wcid] "=r"(wcid)); + return wcid; +} +#endif #endif diff --git a/3rdparty/cpuinfo/src/arm/linux/cpuinfo.c b/3rdparty/cpuinfo/src/arm/linux/cpuinfo.c index b7805b5ef4..081d9aab0d 100644 --- a/3rdparty/cpuinfo/src/arm/linux/cpuinfo.c +++ b/3rdparty/cpuinfo/src/arm/linux/cpuinfo.c @@ -1,26 +1,22 @@ #include +#include #include #include -#include #include -#include #include #include #include +#include /* - * Size, in chars, of the on-stack buffer used for parsing lines of /proc/cpuinfo. - * This is also the limit on the length of a single line. + * Size, in chars, of the on-stack buffer used for parsing lines of + * /proc/cpuinfo. This is also the limit on the length of a single line. */ #define BUFFER_SIZE 1024 - -static uint32_t parse_processor_number( - const char* processor_start, - const char* processor_end) -{ - const size_t processor_length = (size_t) (processor_end - processor_start); +static uint32_t parse_processor_number(const char* processor_start, const char* processor_end) { + const size_t processor_length = (size_t)(processor_end - processor_start); if (processor_length == 0) { cpuinfo_log_warning("Processor number in /proc/cpuinfo is ignored: string is empty"); @@ -29,10 +25,12 @@ static uint32_t parse_processor_number( uint32_t processor_number = 0; for (const char* digit_ptr = processor_start; digit_ptr != processor_end; digit_ptr++) { - const uint32_t digit = (uint32_t) (*digit_ptr - '0'); + const uint32_t digit = (uint32_t)(*digit_ptr - '0'); if (digit > 10) { - cpuinfo_log_warning("non-decimal suffix %.*s in /proc/cpuinfo processor number is ignored", - (int) (processor_end - digit_ptr), digit_ptr); + cpuinfo_log_warning( + "non-decimal suffix %.*s in /proc/cpuinfo processor number is ignored", + (int)(processor_end - digit_ptr), + digit_ptr); break; } @@ -45,42 +43,48 @@ static uint32_t parse_processor_number( /* * Full list of ARM features reported in /proc/cpuinfo: * - * * swp - support for SWP instruction (deprecated in ARMv7, can be removed in future) - * * half - support for half-word loads and stores. These instruction are part of ARMv4, - * so no need to check it on supported CPUs. - * * thumb - support for 16-bit Thumb instruction set. Note that BX instruction is detected - * by ARMv4T architecture, not by this flag. - * * 26bit - old CPUs merged 26-bit PC and program status register (flags) into 32-bit PC - * and had special instructions for working with packed PC. Now it is all deprecated. - * * fastmult - most old ARM CPUs could only compute 2 bits of multiplication result per clock - * cycle, but CPUs with M suffix (e.g. ARM7TDMI) could compute 4 bits per cycle. - * Of course, now it makes no sense. - * * fpa - floating point accelerator available. On original ARM ABI all floating-point operations - * generated FPA instructions. If FPA was not available, these instructions generated - * "illegal operation" interrupts, and the OS processed them by emulating the FPA instructions. - * Debian used this ABI before it switched to EABI. Now FPA is deprecated. - * * vfp - vector floating point instructions. Available on most modern CPUs (as part of VFPv3). - * Required by Android ARMv7A ABI and by Ubuntu on ARM. + * * swp - support for SWP instruction (deprecated in ARMv7, can be removed + *in future) + * * half - support for half-word loads and stores. These instruction are + *part of ARMv4, so no need to check it on supported CPUs. + * * thumb - support for 16-bit Thumb instruction set. Note that BX + *instruction is detected by ARMv4T architecture, not by this flag. + * * 26bit - old CPUs merged 26-bit PC and program status register (flags) + *into 32-bit PC and had special instructions for working with packed PC. Now it + *is all deprecated. + * * fastmult - most old ARM CPUs could only compute 2 bits of + *multiplication result per clock cycle, but CPUs with M suffix (e.g. ARM7TDMI) + *could compute 4 bits per cycle. Of course, now it makes no sense. + * * fpa - floating point accelerator available. On original ARM ABI all + *floating-point operations generated FPA instructions. If FPA was not + *available, these instructions generated "illegal operation" interrupts, and + *the OS processed them by emulating the FPA instructions. Debian used this ABI + *before it switched to EABI. Now FPA is deprecated. + * * vfp - vector floating point instructions. Available on most modern + *CPUs (as part of VFPv3). Required by Android ARMv7A ABI and by Ubuntu on ARM. * Note: there is no flag for VFPv2. - * * edsp - V5E instructions: saturating add/sub and 16-bit x 16-bit -> 32/64-bit multiplications. - * Required on Android, supported by all CPUs in production. + * * edsp - V5E instructions: saturating add/sub and 16-bit x 16-bit -> + *32/64-bit multiplications. Required on Android, supported by all CPUs in + *production. * * java - Jazelle extension. Supported on most CPUs. * * iwmmxt - Intel/Marvell Wireless MMX instructions. 64-bit integer SIMD. - * Supported on XScale (Since PXA270) and Sheeva (PJ1, PJ4) architectures. - * Note that there is no flag for WMMX2 instructions. + * Supported on XScale (Since PXA270) and Sheeva (PJ1, PJ4) + *architectures. Note that there is no flag for WMMX2 instructions. * * crunch - Maverick Crunch instructions. Junk. * * thumbee - ThumbEE instructions. Almost no documentation is available. - * * neon - NEON instructions (aka Advanced SIMD). MVFR1 register gives more - * fine-grained information on particular supported features, but - * the Linux kernel exports only a single flag for all of them. - * According to ARMv7A docs it also implies the availability of VFPv3 - * (with 32 double-precision registers d0-d31). - * * vfpv3 - VFPv3 instructions. Available on most modern CPUs. Augment VFPv2 by - * conversion to/from integers and load constant instructions. - * Required by Android ARMv7A ABI and by Ubuntu on ARM. - * * vfpv3d16 - VFPv3 instructions with only 16 double-precision registers (d0-d15). + * * neon - NEON instructions (aka Advanced SIMD). MVFR1 register gives + *more fine-grained information on particular supported features, but the Linux + *kernel exports only a single flag for all of them. According to ARMv7A docs it + *also implies the availability of VFPv3 (with 32 double-precision registers + *d0-d31). + * * vfpv3 - VFPv3 instructions. Available on most modern CPUs. Augment + *VFPv2 by conversion to/from integers and load constant instructions. Required + *by Android ARMv7A ABI and by Ubuntu on ARM. + * * vfpv3d16 - VFPv3 instructions with only 16 double-precision registers + *(d0-d15). * * tls - software thread ID registers. - * Used by kernel (and likely libc) for efficient implementation of TLS. + * Used by kernel (and likely libc) for efficient implementation of + *TLS. * * vfpv4 - fused multiply-add instructions. * * idiva - DIV instructions available in ARM mode. * * idivt - DIV instructions available in Thumb mode. @@ -93,15 +97,15 @@ static uint32_t parse_processor_number( * * sha2 - SHA2 instructions. * * crc32 - CRC32 instructions. * - * /proc/cpuinfo on ARM is populated in file arch/arm/kernel/setup.c in Linux kernel - * Note that some devices may use patched Linux kernels with different feature names. - * However, the names above were checked on a large number of /proc/cpuinfo listings. + * /proc/cpuinfo on ARM is populated in file arch/arm/kernel/setup.c in + *Linux kernel Note that some devices may use patched Linux kernels with + *different feature names. However, the names above were checked on a large + *number of /proc/cpuinfo listings. */ static void parse_features( const char* features_start, const char* features_end, - struct cpuinfo_arm_linux_processor processor[restrict static 1]) -{ + struct cpuinfo_arm_linux_processor processor[restrict static 1]) { const char* feature_start = features_start; const char* feature_end; @@ -115,7 +119,7 @@ static void parse_features( break; } } - const size_t feature_length = (size_t) (feature_end - feature_start); + const size_t feature_length = (size_t)(feature_end - feature_start); switch (feature_length) { case 2: @@ -126,8 +130,9 @@ static void parse_features( #if CPUINFO_ARCH_ARM } else if (memcmp(feature_start, "wp", feature_length) == 0) { /* - * Some AArch64 kernels, including the one on Nexus 5X, - * erroneously report "swp" as "wp" to AArch32 programs + * Some AArch64 kernels, including the + * one on Nexus 5X, erroneously report + * "swp" as "wp" to AArch32 programs */ processor->features |= CPUINFO_ARM_LINUX_FEATURE_SWP; #endif @@ -137,11 +142,11 @@ static void parse_features( break; case 3: if (memcmp(feature_start, "aes", feature_length) == 0) { - #if CPUINFO_ARCH_ARM - processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_AES; - #elif CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_AES; - #endif +#if CPUINFO_ARCH_ARM + processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_AES; +#elif CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_AES; +#endif #if CPUINFO_ARCH_ARM } else if (memcmp(feature_start, "swp", feature_length) == 0) { processor->features |= CPUINFO_ARM_LINUX_FEATURE_SWP; @@ -158,29 +163,29 @@ static void parse_features( break; case 4: if (memcmp(feature_start, "sha1", feature_length) == 0) { - #if CPUINFO_ARCH_ARM - processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_SHA1; - #elif CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_SHA1; - #endif +#if CPUINFO_ARCH_ARM + processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_SHA1; +#elif CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_SHA1; +#endif } else if (memcmp(feature_start, "sha2", feature_length) == 0) { - #if CPUINFO_ARCH_ARM - processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_SHA2; - #elif CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_SHA2; - #endif +#if CPUINFO_ARCH_ARM + processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_SHA2; +#elif CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_SHA2; +#endif } else if (memcmp(feature_start, "fphp", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_FPHP; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_FPHP; +#endif } else if (memcmp(feature_start, "fcma", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_FCMA; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_FCMA; +#endif } else if (memcmp(feature_start, "i8mm", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_I8MM; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_I8MM; +#endif #if CPUINFO_ARCH_ARM } else if (memcmp(feature_start, "half", feature_length) == 0) { processor->features |= CPUINFO_ARM_LINUX_FEATURE_HALF; @@ -194,8 +199,9 @@ static void parse_features( processor->features |= CPUINFO_ARM_LINUX_FEATURE_LPAE; } else if (memcmp(feature_start, "tlsi", feature_length) == 0) { /* - * Some AArch64 kernels, including the one on Nexus 5X, - * erroneously report "tls" as "tlsi" to AArch32 programs + * Some AArch64 kernels, including the + * one on Nexus 5X, erroneously report + * "tls" as "tlsi" to AArch32 programs */ processor->features |= CPUINFO_ARM_LINUX_FEATURE_TLS; #endif /* CPUINFO_ARCH_ARM */ @@ -205,33 +211,33 @@ static void parse_features( break; case 5: if (memcmp(feature_start, "pmull", feature_length) == 0) { - #if CPUINFO_ARCH_ARM - processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_PMULL; - #elif CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_PMULL; - #endif +#if CPUINFO_ARCH_ARM + processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_PMULL; +#elif CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_PMULL; +#endif } else if (memcmp(feature_start, "crc32", feature_length) == 0) { - #if CPUINFO_ARCH_ARM - processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_CRC32; - #elif CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_CRC32; - #endif +#if CPUINFO_ARCH_ARM + processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_CRC32; +#elif CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_CRC32; +#endif } else if (memcmp(feature_start, "asimd", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMD; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMD; +#endif } else if (memcmp(feature_start, "cpuid", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_CPUID; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_CPUID; +#endif } else if (memcmp(feature_start, "jscvt", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_JSCVT; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_JSCVT; +#endif } else if (memcmp(feature_start, "lrcpc", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_LRCPC; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_LRCPC; +#endif #if CPUINFO_ARCH_ARM } else if (memcmp(feature_start, "thumb", feature_length) == 0) { processor->features |= CPUINFO_ARM_LINUX_FEATURE_THUMB; @@ -249,7 +255,7 @@ static void parse_features( } else { goto unexpected; } - break; + break; #if CPUINFO_ARCH_ARM case 6: if (memcmp(feature_start, "iwmmxt", feature_length) == 0) { @@ -267,13 +273,13 @@ static void parse_features( if (memcmp(feature_start, "evtstrm", feature_length) == 0) { processor->features |= CPUINFO_ARM_LINUX_FEATURE_EVTSTRM; } else if (memcmp(feature_start, "atomics", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_ATOMICS; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_ATOMICS; +#endif } else if (memcmp(feature_start, "asimdhp", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMDHP; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMDHP; +#endif #if CPUINFO_ARCH_ARM } else if (memcmp(feature_start, "thumbee", feature_length) == 0) { processor->features |= CPUINFO_ARM_LINUX_FEATURE_THUMBEE; @@ -284,13 +290,13 @@ static void parse_features( break; case 8: if (memcmp(feature_start, "asimdrdm", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMDRDM; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMDRDM; +#endif } else if (memcmp(feature_start, "asimdfhm", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMDFHM; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMDFHM; +#endif #if CPUINFO_ARCH_ARM } else if (memcmp(feature_start, "fastmult", feature_length) == 0) { processor->features |= CPUINFO_ARM_LINUX_FEATURE_FASTMULT; @@ -303,8 +309,10 @@ static void parse_features( break; default: unexpected: - cpuinfo_log_warning("unexpected /proc/cpuinfo feature \"%.*s\" is ignored", - (int) feature_length, feature_start); + cpuinfo_log_warning( + "unexpected /proc/cpuinfo feature \"%.*s\" is ignored", + (int)feature_length, + feature_start); break; } feature_start = feature_end; @@ -319,10 +327,10 @@ static void parse_features( static void parse_cpu_architecture( const char* cpu_architecture_start, const char* cpu_architecture_end, - struct cpuinfo_arm_linux_processor processor[restrict static 1]) -{ - const size_t cpu_architecture_length = (size_t) (cpu_architecture_end - cpu_architecture_start); - /* Early AArch64 kernels report "CPU architecture: AArch64" instead of a numeric value 8 */ + struct cpuinfo_arm_linux_processor processor[restrict static 1]) { + const size_t cpu_architecture_length = (size_t)(cpu_architecture_end - cpu_architecture_start); + /* Early AArch64 kernels report "CPU architecture: AArch64" instead of a + * numeric value 8 */ if (cpu_architecture_length == 7) { if (memcmp(cpu_architecture_start, "AArch64", cpu_architecture_length) == 0) { processor->midr = midr_set_architecture(processor->midr, UINT32_C(0xF)); @@ -332,7 +340,6 @@ static void parse_cpu_architecture( } } - uint32_t architecture = 0; const char* cpu_architecture_ptr = cpu_architecture_start; for (; cpu_architecture_ptr != cpu_architecture_end; cpu_architecture_ptr++) { @@ -347,8 +354,10 @@ static void parse_cpu_architecture( } if (cpu_architecture_ptr == cpu_architecture_start) { - cpuinfo_log_warning("CPU architecture %.*s in /proc/cpuinfo is ignored due to non-digit at the beginning of the string", - (int) cpu_architecture_length, cpu_architecture_start); + cpuinfo_log_warning( + "CPU architecture %.*s in /proc/cpuinfo is ignored due to non-digit at the beginning of the string", + (int)cpu_architecture_length, + cpu_architecture_start); } else { if (architecture != 0) { processor->architecture_version = architecture; @@ -370,17 +379,22 @@ static void parse_cpu_architecture( #endif /* CPUINFO_ARCH_ARM */ case ' ': case '\t': - /* Ignore whitespace at the end */ + /* Ignore whitespace at the end + */ break; default: - cpuinfo_log_warning("skipped unknown architectural feature '%c' for ARMv%"PRIu32, - feature, architecture); + cpuinfo_log_warning( + "skipped unknown architectural feature '%c' for ARMv%" PRIu32, + feature, + architecture); break; } } } else { - cpuinfo_log_warning("CPU architecture %.*s in /proc/cpuinfo is ignored due to invalid value (0)", - (int) cpu_architecture_length, cpu_architecture_start); + cpuinfo_log_warning( + "CPU architecture %.*s in /proc/cpuinfo is ignored due to invalid value (0)", + (int)cpu_architecture_length, + cpu_architecture_start); } } @@ -391,9 +405,12 @@ static void parse_cpu_architecture( midr_architecture = UINT32_C(0x7); /* ARMv6 */ break; case 5: - if ((processor->architecture_flags & CPUINFO_ARM_LINUX_ARCH_TEJ) == CPUINFO_ARM_LINUX_ARCH_TEJ) { + if ((processor->architecture_flags & CPUINFO_ARM_LINUX_ARCH_TEJ) == + CPUINFO_ARM_LINUX_ARCH_TEJ) { midr_architecture = UINT32_C(0x6); /* ARMv5TEJ */ - } else if ((processor->architecture_flags & CPUINFO_ARM_LINUX_ARCH_TE) == CPUINFO_ARM_LINUX_ARCH_TE) { + } else if ( + (processor->architecture_flags & CPUINFO_ARM_LINUX_ARCH_TE) == + CPUINFO_ARM_LINUX_ARCH_TE) { midr_architecture = UINT32_C(0x5); /* ARMv5TE */ } else { midr_architecture = UINT32_C(0x4); /* ARMv5T */ @@ -407,9 +424,8 @@ static void parse_cpu_architecture( static void parse_cpu_part( const char* cpu_part_start, const char* cpu_part_end, - struct cpuinfo_arm_linux_processor processor[restrict static 1]) -{ - const size_t cpu_part_length = (size_t) (cpu_part_end - cpu_part_start); + struct cpuinfo_arm_linux_processor processor[restrict static 1]) { + const size_t cpu_part_length = (size_t)(cpu_part_end - cpu_part_start); /* * CPU part should contain hex prefix (0x) and one to three hex digits. @@ -419,32 +435,42 @@ static void parse_cpu_part( * Main ID Register (MIDR) assigns only a 12-bit value for CPU part. */ if (cpu_part_length < 3 || cpu_part_length > 5) { - cpuinfo_log_warning("CPU part %.*s in /proc/cpuinfo is ignored due to unexpected length (%zu)", - (int) cpu_part_length, cpu_part_start, cpu_part_length); + cpuinfo_log_warning( + "CPU part %.*s in /proc/cpuinfo is ignored due to unexpected length (%zu)", + (int)cpu_part_length, + cpu_part_start, + cpu_part_length); return; } /* Verify the presence of hex prefix */ if (cpu_part_start[0] != '0' || cpu_part_start[1] != 'x') { - cpuinfo_log_warning("CPU part %.*s in /proc/cpuinfo is ignored due to lack of 0x prefix", - (int) cpu_part_length, cpu_part_start); + cpuinfo_log_warning( + "CPU part %.*s in /proc/cpuinfo is ignored due to lack of 0x prefix", + (int)cpu_part_length, + cpu_part_start); return; } - /* Verify that characters after hex prefix are hexadecimal digits and decode them */ + /* Verify that characters after hex prefix are hexadecimal digits and + * decode them */ uint32_t cpu_part = 0; for (const char* digit_ptr = cpu_part_start + 2; digit_ptr != cpu_part_end; digit_ptr++) { const char digit_char = *digit_ptr; uint32_t digit; if (digit_char >= '0' && digit_char <= '9') { digit = digit_char - '0'; - } else if ((uint32_t) (digit_char - 'A') < 6) { + } else if ((uint32_t)(digit_char - 'A') < 6) { digit = 10 + (digit_char - 'A'); - } else if ((uint32_t) (digit_char - 'a') < 6) { + } else if ((uint32_t)(digit_char - 'a') < 6) { digit = 10 + (digit_char - 'a'); } else { - cpuinfo_log_warning("CPU part %.*s in /proc/cpuinfo is ignored due to unexpected non-hex character %c at offset %zu", - (int) cpu_part_length, cpu_part_start, digit_char, (size_t) (digit_ptr - cpu_part_start)); + cpuinfo_log_warning( + "CPU part %.*s in /proc/cpuinfo is ignored due to unexpected non-hex character %c at offset %zu", + (int)cpu_part_length, + cpu_part_start, + digit_char, + (size_t)(digit_ptr - cpu_part_start)); return; } cpu_part = cpu_part * 16 + digit; @@ -457,8 +483,7 @@ static void parse_cpu_part( static void parse_cpu_implementer( const char* cpu_implementer_start, const char* cpu_implementer_end, - struct cpuinfo_arm_linux_processor processor[restrict static 1]) -{ + struct cpuinfo_arm_linux_processor processor[restrict static 1]) { const size_t cpu_implementer_length = cpu_implementer_end - cpu_implementer_start; /* @@ -466,39 +491,50 @@ static void parse_cpu_implementer( * I have never seen single hex digit as a value of this field, * but I don't think it is impossible in future. * Value can not contain more than two hex digits since - * Main ID Register (MIDR) assigns only an 8-bit value for CPU implementer. + * Main ID Register (MIDR) assigns only an 8-bit value for CPU + * implementer. */ switch (cpu_implementer_length) { case 3: case 4: break; default: - cpuinfo_log_warning("CPU implementer %.*s in /proc/cpuinfo is ignored due to unexpected length (%zu)", - (int) cpu_implementer_length, cpu_implementer_start, cpu_implementer_length); - return; + cpuinfo_log_warning( + "CPU implementer %.*s in /proc/cpuinfo is ignored due to unexpected length (%zu)", + (int)cpu_implementer_length, + cpu_implementer_start, + cpu_implementer_length); + return; } /* Verify the presence of hex prefix */ if (cpu_implementer_start[0] != '0' || cpu_implementer_start[1] != 'x') { - cpuinfo_log_warning("CPU implementer %.*s in /proc/cpuinfo is ignored due to lack of 0x prefix", - (int) cpu_implementer_length, cpu_implementer_start); + cpuinfo_log_warning( + "CPU implementer %.*s in /proc/cpuinfo is ignored due to lack of 0x prefix", + (int)cpu_implementer_length, + cpu_implementer_start); return; } - /* Verify that characters after hex prefix are hexadecimal digits and decode them */ + /* Verify that characters after hex prefix are hexadecimal digits and + * decode them */ uint32_t cpu_implementer = 0; for (const char* digit_ptr = cpu_implementer_start + 2; digit_ptr != cpu_implementer_end; digit_ptr++) { const char digit_char = *digit_ptr; uint32_t digit; if (digit_char >= '0' && digit_char <= '9') { digit = digit_char - '0'; - } else if ((uint32_t) (digit_char - 'A') < 6) { + } else if ((uint32_t)(digit_char - 'A') < 6) { digit = 10 + (digit_char - 'A'); - } else if ((uint32_t) (digit_char - 'a') < 6) { + } else if ((uint32_t)(digit_char - 'a') < 6) { digit = 10 + (digit_char - 'a'); } else { - cpuinfo_log_warning("CPU implementer %.*s in /proc/cpuinfo is ignored due to unexpected non-hex character '%c' at offset %zu", - (int) cpu_implementer_length, cpu_implementer_start, digit_char, (size_t) (digit_ptr - cpu_implementer_start)); + cpuinfo_log_warning( + "CPU implementer %.*s in /proc/cpuinfo is ignored due to unexpected non-hex character '%c' at offset %zu", + (int)cpu_implementer_length, + cpu_implementer_start, + digit_char, + (size_t)(digit_ptr - cpu_implementer_start)); return; } cpu_implementer = cpu_implementer * 16 + digit; @@ -511,8 +547,7 @@ static void parse_cpu_implementer( static void parse_cpu_variant( const char* cpu_variant_start, const char* cpu_variant_end, - struct cpuinfo_arm_linux_processor processor[restrict static 1]) -{ + struct cpuinfo_arm_linux_processor processor[restrict static 1]) { const size_t cpu_variant_length = cpu_variant_end - cpu_variant_start; /* @@ -521,30 +556,39 @@ static void parse_cpu_variant( * Main ID Register (MIDR) assigns only a 4-bit value for CPU variant. */ if (cpu_variant_length != 3) { - cpuinfo_log_warning("CPU variant %.*s in /proc/cpuinfo is ignored due to unexpected length (%zu)", - (int) cpu_variant_length, cpu_variant_start, cpu_variant_length); + cpuinfo_log_warning( + "CPU variant %.*s in /proc/cpuinfo is ignored due to unexpected length (%zu)", + (int)cpu_variant_length, + cpu_variant_start, + cpu_variant_length); return; } /* Skip if there is no hex prefix (0x) */ if (cpu_variant_start[0] != '0' || cpu_variant_start[1] != 'x') { - cpuinfo_log_warning("CPU variant %.*s in /proc/cpuinfo is ignored due to lack of 0x prefix", - (int) cpu_variant_length, cpu_variant_start); + cpuinfo_log_warning( + "CPU variant %.*s in /proc/cpuinfo is ignored due to lack of 0x prefix", + (int)cpu_variant_length, + cpu_variant_start); return; } - /* Check if the value after hex prefix is indeed a hex digit and decode it. */ + /* Check if the value after hex prefix is indeed a hex digit and decode + * it. */ const char digit_char = cpu_variant_start[2]; uint32_t cpu_variant; - if ((uint32_t) (digit_char - '0') < 10) { - cpu_variant = (uint32_t) (digit_char - '0'); - } else if ((uint32_t) (digit_char - 'A') < 6) { - cpu_variant = 10 + (uint32_t) (digit_char - 'A'); - } else if ((uint32_t) (digit_char - 'a') < 6) { - cpu_variant = 10 + (uint32_t) (digit_char - 'a'); + if ((uint32_t)(digit_char - '0') < 10) { + cpu_variant = (uint32_t)(digit_char - '0'); + } else if ((uint32_t)(digit_char - 'A') < 6) { + cpu_variant = 10 + (uint32_t)(digit_char - 'A'); + } else if ((uint32_t)(digit_char - 'a') < 6) { + cpu_variant = 10 + (uint32_t)(digit_char - 'a'); } else { - cpuinfo_log_warning("CPU variant %.*s in /proc/cpuinfo is ignored due to unexpected non-hex character '%c'", - (int) cpu_variant_length, cpu_variant_start, digit_char); + cpuinfo_log_warning( + "CPU variant %.*s in /proc/cpuinfo is ignored due to unexpected non-hex character '%c'", + (int)cpu_variant_length, + cpu_variant_start, + digit_char); return; } @@ -555,17 +599,20 @@ static void parse_cpu_variant( static void parse_cpu_revision( const char* cpu_revision_start, const char* cpu_revision_end, - struct cpuinfo_arm_linux_processor processor[restrict static 1]) -{ + struct cpuinfo_arm_linux_processor processor[restrict static 1]) { uint32_t cpu_revision = 0; for (const char* digit_ptr = cpu_revision_start; digit_ptr != cpu_revision_end; digit_ptr++) { - const uint32_t digit = (uint32_t) (*digit_ptr - '0'); + const uint32_t digit = (uint32_t)(*digit_ptr - '0'); - /* Verify that the character in CPU revision is a decimal digit */ + /* Verify that the character in CPU revision is a decimal digit + */ if (digit >= 10) { - cpuinfo_log_warning("CPU revision %.*s in /proc/cpuinfo is ignored due to unexpected non-digit character '%c' at offset %zu", - (int) (cpu_revision_end - cpu_revision_start), cpu_revision_start, - *digit_ptr, (size_t) (digit_ptr - cpu_revision_start)); + cpuinfo_log_warning( + "CPU revision %.*s in /proc/cpuinfo is ignored due to unexpected non-digit character '%c' at offset %zu", + (int)(cpu_revision_end - cpu_revision_start), + cpu_revision_start, + *digit_ptr, + (size_t)(digit_ptr - cpu_revision_start)); return; } @@ -598,15 +645,18 @@ static void parse_cache_number( const char* number_name, uint32_t number_ptr[restrict static 1], uint32_t flags[restrict static 1], - uint32_t number_mask) -{ + uint32_t number_mask) { uint32_t number = 0; for (const char* digit_ptr = number_start; digit_ptr != number_end; digit_ptr++) { const uint32_t digit = *digit_ptr - '0'; if (digit >= 10) { - cpuinfo_log_warning("%s %.*s in /proc/cpuinfo is ignored due to unexpected non-digit character '%c' at offset %zu", - number_name, (int) (number_end - number_start), number_start, - *digit_ptr, (size_t) (digit_ptr - number_start)); + cpuinfo_log_warning( + "%s %.*s in /proc/cpuinfo is ignored due to unexpected non-digit character '%c' at offset %zu", + number_name, + (int)(number_end - number_start), + number_start, + *digit_ptr, + (size_t)(digit_ptr - number_start)); return; } @@ -614,11 +664,15 @@ static void parse_cache_number( } if (number == 0) { - cpuinfo_log_warning("%s %.*s in /proc/cpuinfo is ignored due to invalid value of zero reported by the kernel", - number_name, (int) (number_end - number_start), number_start); + cpuinfo_log_warning( + "%s %.*s in /proc/cpuinfo is ignored due to invalid value of zero reported by the kernel", + number_name, + (int)(number_end - number_start), + number_start); } - /* If the number specifies a cache line size, verify that is a reasonable power of 2 */ + /* If the number specifies a cache line size, verify that is a + * reasonable power of 2 */ if (number_mask & CPUINFO_ARM_LINUX_VALID_CACHE_LINE) { switch (number) { case 16: @@ -627,8 +681,11 @@ static void parse_cache_number( case 128: break; default: - cpuinfo_log_warning("invalid %s %.*s is ignored: a value of 16, 32, 64, or 128 expected", - number_name, (int) (number_end - number_start), number_start); + cpuinfo_log_warning( + "invalid %s %.*s is ignored: a value of 16, 32, 64, or 128 expected", + number_name, + (int)(number_end - number_start), + number_start); } } @@ -658,12 +715,9 @@ struct proc_cpuinfo_parser_state { * processor : 1 * BogoMIPS : 1363.33 * - * Features : swp half thumb fastmult vfp edsp thumbee neon vfpv3 - * CPU implementer : 0x41 - * CPU architecture: 7 - * CPU variant : 0x2 - * CPU part : 0xc09 - * CPU revision : 10 + * Features : swp half thumb fastmult vfp edsp thumbee neon + *vfpv3 CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x2 CPU + *part : 0xc09 CPU revision : 10 * * Hardware : OMAP4 Panda board * Revision : 0020 @@ -673,8 +727,7 @@ static bool parse_line( const char* line_start, const char* line_end, struct proc_cpuinfo_parser_state state[restrict static 1], - uint64_t line_number) -{ + uint64_t line_number) { /* Empty line. Skip. */ if (line_start == line_end) { return true; @@ -689,8 +742,10 @@ static bool parse_line( } /* Skip line if no ':' separator was found. */ if (separator == line_end) { - cpuinfo_log_info("Line %.*s in /proc/cpuinfo is ignored: key/value separator ':' not found", - (int) (line_end - line_start), line_start); + cpuinfo_log_debug( + "Line %.*s in /proc/cpuinfo is ignored: key/value separator ':' not found", + (int)(line_end - line_start), + line_start); return true; } @@ -703,8 +758,10 @@ static bool parse_line( } /* Skip line if key contains nothing but spaces. */ if (key_end == line_start) { - cpuinfo_log_info("Line %.*s in /proc/cpuinfo is ignored: key contains only spaces", - (int) (line_end - line_start), line_start); + cpuinfo_log_debug( + "Line %.*s in /proc/cpuinfo is ignored: key contains only spaces", + (int)(line_end - line_start), + line_start); return true; } @@ -717,8 +774,10 @@ static bool parse_line( } /* Value part contains nothing but spaces. Skip line. */ if (value_start == line_end) { - cpuinfo_log_info("Line %.*s in /proc/cpuinfo is ignored: value contains only spaces", - (int) (line_end - line_start), line_start); + cpuinfo_log_debug( + "Line %.*s in /proc/cpuinfo is ignored: value contains only spaces", + (int)(line_end - line_start), + line_start); return true; } @@ -730,10 +789,10 @@ static bool parse_line( } } - const uint32_t processor_index = state->processor_index; + const uint32_t processor_index = state->processor_index; const uint32_t max_processors_count = state->max_processors_count; struct cpuinfo_arm_linux_processor* processors = state->processors; - struct cpuinfo_arm_linux_processor* processor = &state->dummy_processor; + struct cpuinfo_arm_linux_processor* processor = &state->dummy_processor; if (processor_index < max_processors_count) { processor = &processors[processor_index]; } @@ -745,21 +804,37 @@ static bool parse_line( /* Usually contains just zeros, useless */ #if CPUINFO_ARCH_ARM } else if (memcmp(line_start, "I size", key_length) == 0) { - parse_cache_number(value_start, value_end, - "instruction cache size", &processor->proc_cpuinfo_cache.i_size, - &processor->flags, CPUINFO_ARM_LINUX_VALID_ICACHE_SIZE); + parse_cache_number( + value_start, + value_end, + "instruction cache size", + &processor->proc_cpuinfo_cache.i_size, + &processor->flags, + CPUINFO_ARM_LINUX_VALID_ICACHE_SIZE); } else if (memcmp(line_start, "I sets", key_length) == 0) { - parse_cache_number(value_start, value_end, - "instruction cache sets", &processor->proc_cpuinfo_cache.i_sets, - &processor->flags, CPUINFO_ARM_LINUX_VALID_ICACHE_SETS); + parse_cache_number( + value_start, + value_end, + "instruction cache sets", + &processor->proc_cpuinfo_cache.i_sets, + &processor->flags, + CPUINFO_ARM_LINUX_VALID_ICACHE_SETS); } else if (memcmp(line_start, "D size", key_length) == 0) { - parse_cache_number(value_start, value_end, - "data cache size", &processor->proc_cpuinfo_cache.d_size, - &processor->flags, CPUINFO_ARM_LINUX_VALID_DCACHE_SIZE); + parse_cache_number( + value_start, + value_end, + "data cache size", + &processor->proc_cpuinfo_cache.d_size, + &processor->flags, + CPUINFO_ARM_LINUX_VALID_DCACHE_SIZE); } else if (memcmp(line_start, "D sets", key_length) == 0) { - parse_cache_number(value_start, value_end, - "data cache sets", &processor->proc_cpuinfo_cache.d_sets, - &processor->flags, CPUINFO_ARM_LINUX_VALID_DCACHE_SETS); + parse_cache_number( + value_start, + value_end, + "data cache sets", + &processor->proc_cpuinfo_cache.d_sets, + &processor->flags, + CPUINFO_ARM_LINUX_VALID_DCACHE_SETS); #endif /* CPUINFO_ARCH_ARM */ } else { goto unknown; @@ -768,13 +843,21 @@ static bool parse_line( #if CPUINFO_ARCH_ARM case 7: if (memcmp(line_start, "I assoc", key_length) == 0) { - parse_cache_number(value_start, value_end, - "instruction cache associativity", &processor->proc_cpuinfo_cache.i_assoc, - &processor->flags, CPUINFO_ARM_LINUX_VALID_ICACHE_WAYS); + parse_cache_number( + value_start, + value_end, + "instruction cache associativity", + &processor->proc_cpuinfo_cache.i_assoc, + &processor->flags, + CPUINFO_ARM_LINUX_VALID_ICACHE_WAYS); } else if (memcmp(line_start, "D assoc", key_length) == 0) { - parse_cache_number(value_start, value_end, - "data cache associativity", &processor->proc_cpuinfo_cache.d_assoc, - &processor->flags, CPUINFO_ARM_LINUX_VALID_DCACHE_WAYS); + parse_cache_number( + value_start, + value_end, + "data cache associativity", + &processor->proc_cpuinfo_cache.d_assoc, + &processor->flags, + CPUINFO_ARM_LINUX_VALID_DCACHE_WAYS); } else { goto unknown; } @@ -790,27 +873,33 @@ static bool parse_line( } else if (memcmp(line_start, "Hardware", key_length) == 0) { size_t value_length = value_end - value_start; if (value_length > CPUINFO_HARDWARE_VALUE_MAX) { - cpuinfo_log_info( + cpuinfo_log_warning( "length of Hardware value \"%.*s\" in /proc/cpuinfo exceeds limit (%d): truncating to the limit", - (int) value_length, value_start, CPUINFO_HARDWARE_VALUE_MAX); + (int)value_length, + value_start, + CPUINFO_HARDWARE_VALUE_MAX); value_length = CPUINFO_HARDWARE_VALUE_MAX; } else { state->hardware[value_length] = '\0'; } memcpy(state->hardware, value_start, value_length); - cpuinfo_log_debug("parsed /proc/cpuinfo Hardware = \"%.*s\"", (int) value_length, value_start); + cpuinfo_log_debug( + "parsed /proc/cpuinfo Hardware = \"%.*s\"", (int)value_length, value_start); } else if (memcmp(line_start, "Revision", key_length) == 0) { size_t value_length = value_end - value_start; if (value_length > CPUINFO_REVISION_VALUE_MAX) { - cpuinfo_log_info( + cpuinfo_log_warning( "length of Revision value \"%.*s\" in /proc/cpuinfo exceeds limit (%d): truncating to the limit", - (int) value_length, value_start, CPUINFO_REVISION_VALUE_MAX); + (int)value_length, + value_start, + CPUINFO_REVISION_VALUE_MAX); value_length = CPUINFO_REVISION_VALUE_MAX; } else { state->revision[value_length] = '\0'; } memcpy(state->revision, value_start, value_length); - cpuinfo_log_debug("parsed /proc/cpuinfo Revision = \"%.*s\"", (int) value_length, value_start); + cpuinfo_log_debug( + "parsed /proc/cpuinfo Revision = \"%.*s\"", (int)value_length, value_start); } else { goto unknown; } @@ -819,28 +908,39 @@ static bool parse_line( if (memcmp(line_start, "processor", key_length) == 0) { const uint32_t new_processor_index = parse_processor_number(value_start, value_end); if (new_processor_index < processor_index) { - /* Strange: decreasing processor number */ + /* Strange: decreasing processor number + */ cpuinfo_log_warning( - "unexpectedly low processor number %"PRIu32" following processor %"PRIu32" in /proc/cpuinfo", - new_processor_index, processor_index); + "unexpectedly low processor number %" PRIu32 + " following processor %" PRIu32 " in /proc/cpuinfo", + new_processor_index, + processor_index); } else if (new_processor_index > processor_index + 1) { - /* Strange, but common: skipped processor $(processor_index + 1) */ - cpuinfo_log_info( - "unexpectedly high processor number %"PRIu32" following processor %"PRIu32" in /proc/cpuinfo", - new_processor_index, processor_index); + /* Strange, but common: skipped + * processor $(processor_index + 1) */ + cpuinfo_log_warning( + "unexpectedly high processor number %" PRIu32 + " following processor %" PRIu32 " in /proc/cpuinfo", + new_processor_index, + processor_index); } if (new_processor_index < max_processors_count) { - /* Record that the processor was mentioned in /proc/cpuinfo */ + /* Record that the processor was + * mentioned in /proc/cpuinfo */ processors[new_processor_index].flags |= CPUINFO_ARM_LINUX_VALID_PROCESSOR; } else { /* Log and ignore processor */ - cpuinfo_log_warning("processor %"PRIu32" in /proc/cpuinfo is ignored: index exceeds system limit %"PRIu32, - new_processor_index, max_processors_count - 1); + cpuinfo_log_warning( + "processor %" PRIu32 + " in /proc/cpuinfo is ignored: index exceeds system limit %" PRIu32, + new_processor_index, + max_processors_count - 1); } state->processor_index = new_processor_index; return true; } else if (memcmp(line_start, "Processor", key_length) == 0) { - /* TODO: parse to fix misreported architecture, similar to Android's cpufeatures */ + /* TODO: parse to fix misreported architecture, + * similar to Android's cpufeatures */ } else { goto unknown; } @@ -862,13 +962,21 @@ static bool parse_line( #if CPUINFO_ARCH_ARM case 13: if (memcmp(line_start, "I line length", key_length) == 0) { - parse_cache_number(value_start, value_end, - "instruction cache line size", &processor->proc_cpuinfo_cache.i_line_length, - &processor->flags, CPUINFO_ARM_LINUX_VALID_ICACHE_LINE); + parse_cache_number( + value_start, + value_end, + "instruction cache line size", + &processor->proc_cpuinfo_cache.i_line_length, + &processor->flags, + CPUINFO_ARM_LINUX_VALID_ICACHE_LINE); } else if (memcmp(line_start, "D line length", key_length) == 0) { - parse_cache_number(value_start, value_end, - "data cache line size", &processor->proc_cpuinfo_cache.d_line_length, - &processor->flags, CPUINFO_ARM_LINUX_VALID_DCACHE_LINE); + parse_cache_number( + value_start, + value_end, + "data cache line size", + &processor->proc_cpuinfo_cache.d_line_length, + &processor->flags, + CPUINFO_ARM_LINUX_VALID_DCACHE_LINE); } else { goto unknown; } @@ -892,8 +1000,7 @@ static bool parse_line( break; default: unknown: - cpuinfo_log_debug("unknown /proc/cpuinfo key: %.*s", (int) key_length, line_start); - + cpuinfo_log_debug("unknown /proc/cpuinfo key: %.*s", (int)key_length, line_start); } return true; } @@ -902,8 +1009,7 @@ bool cpuinfo_arm_linux_parse_proc_cpuinfo( char hardware[restrict static CPUINFO_HARDWARE_VALUE_MAX], char revision[restrict static CPUINFO_REVISION_VALUE_MAX], uint32_t max_processors_count, - struct cpuinfo_arm_linux_processor processors[restrict static max_processors_count]) -{ + struct cpuinfo_arm_linux_processor processors[restrict static max_processors_count]) { hardware[0] = '\0'; struct proc_cpuinfo_parser_state state = { .hardware = hardware, @@ -912,6 +1018,6 @@ bool cpuinfo_arm_linux_parse_proc_cpuinfo( .max_processors_count = max_processors_count, .processors = processors, }; - return cpuinfo_linux_parse_multiline_file("/proc/cpuinfo", BUFFER_SIZE, - (cpuinfo_line_callback) parse_line, &state); + return cpuinfo_linux_parse_multiline_file( + "/proc/cpuinfo", BUFFER_SIZE, (cpuinfo_line_callback)parse_line, &state); } diff --git a/3rdparty/cpuinfo/src/arm/linux/hwcap.c b/3rdparty/cpuinfo/src/arm/linux/hwcap.c index 984ab43c52..e836548db1 100644 --- a/3rdparty/cpuinfo/src/arm/linux/hwcap.c +++ b/3rdparty/cpuinfo/src/arm/linux/hwcap.c @@ -1,163 +1,154 @@ #include #include -#include -#include -#include -#include -#include #include #include +#include +#include +#include +#include +#include #if CPUINFO_MOCK - #include +#include #endif -#include #include +#include #include -#if CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_ARM && \ - defined(__GLIBC__) && defined(__GLIBC_MINOR__) && (__GLIBC__ > 2 || __GLIBC__ == 2 && __GLIBC_MINOR__ >= 16) - #include +#if CPUINFO_ARCH_ARM64 || \ + CPUINFO_ARCH_ARM && defined(__GLIBC__) && defined(__GLIBC_MINOR__) && \ + (__GLIBC__ > 2 || __GLIBC__ == 2 && __GLIBC_MINOR__ >= 16) +#include #else - #define AT_HWCAP 16 - #define AT_HWCAP2 26 +#define AT_HWCAP 16 +#define AT_HWCAP2 26 #endif - #if CPUINFO_MOCK - static uint32_t mock_hwcap = 0; - void cpuinfo_set_hwcap(uint32_t hwcap) { - mock_hwcap = hwcap; - } +static uint32_t mock_hwcap = 0; +void cpuinfo_set_hwcap(uint32_t hwcap) { + mock_hwcap = hwcap; +} - static uint32_t mock_hwcap2 = 0; - void cpuinfo_set_hwcap2(uint32_t hwcap2) { - mock_hwcap2 = hwcap2; - } +static uint32_t mock_hwcap2 = 0; +void cpuinfo_set_hwcap2(uint32_t hwcap2) { + mock_hwcap2 = hwcap2; +} #endif - #if CPUINFO_ARCH_ARM - typedef unsigned long (*getauxval_function_t)(unsigned long); +typedef unsigned long (*getauxval_function_t)(unsigned long); - bool cpuinfo_arm_linux_hwcap_from_getauxval( - uint32_t hwcap[restrict static 1], - uint32_t hwcap2[restrict static 1]) - { - #if CPUINFO_MOCK - *hwcap = mock_hwcap; - *hwcap2 = mock_hwcap2; - return true; - #elif defined(__ANDROID__) - /* Android: dynamically check if getauxval is supported */ - void* libc = NULL; - getauxval_function_t getauxval = NULL; +bool cpuinfo_arm_linux_hwcap_from_getauxval(uint32_t hwcap[restrict static 1], uint32_t hwcap2[restrict static 1]) { +#if CPUINFO_MOCK + *hwcap = mock_hwcap; + *hwcap2 = mock_hwcap2; + return true; +#elif defined(__ANDROID__) + /* Android: dynamically check if getauxval is supported */ + void* libc = NULL; + getauxval_function_t getauxval = NULL; - dlerror(); - libc = dlopen("libc.so", RTLD_LAZY); - if (libc == NULL) { - cpuinfo_log_warning("failed to load libc.so: %s", dlerror()); - goto cleanup; - } - - getauxval = (getauxval_function_t) dlsym(libc, "getauxval"); - if (getauxval == NULL) { - cpuinfo_log_info("failed to locate getauxval in libc.so: %s", dlerror()); - goto cleanup; - } - - *hwcap = getauxval(AT_HWCAP); - *hwcap2 = getauxval(AT_HWCAP2); - - cleanup: - if (libc != NULL) { - dlclose(libc); - libc = NULL; - } - return getauxval != NULL; - #elif defined(__GLIBC__) && defined(__GLIBC_MINOR__) && (__GLIBC__ > 2 || __GLIBC__ == 2 && __GLIBC_MINOR__ >= 16) - /* GNU/Linux: getauxval is supported since glibc-2.16 */ - *hwcap = getauxval(AT_HWCAP); - *hwcap2 = getauxval(AT_HWCAP2); - return true; - #else - return false; - #endif + dlerror(); + libc = dlopen("libc.so", RTLD_LAZY); + if (libc == NULL) { + cpuinfo_log_warning("failed to load libc.so: %s", dlerror()); + goto cleanup; } - #ifdef __ANDROID__ - bool cpuinfo_arm_linux_hwcap_from_procfs( - uint32_t hwcap[restrict static 1], - uint32_t hwcap2[restrict static 1]) - { - #if CPUINFO_MOCK - *hwcap = mock_hwcap; - *hwcap2 = mock_hwcap2; - return true; - #else - uint32_t hwcaps[2] = { 0, 0 }; - bool result = false; - int file = -1; - - file = open("/proc/self/auxv", O_RDONLY); - if (file == -1) { - cpuinfo_log_warning("failed to open /proc/self/auxv: %s", strerror(errno)); - goto cleanup; - } - - ssize_t bytes_read; - do { - Elf32_auxv_t elf_auxv; - bytes_read = read(file, &elf_auxv, sizeof(Elf32_auxv_t)); - if (bytes_read < 0) { - cpuinfo_log_warning("failed to read /proc/self/auxv: %s", strerror(errno)); - goto cleanup; - } else if (bytes_read > 0) { - if (bytes_read == sizeof(elf_auxv)) { - switch (elf_auxv.a_type) { - case AT_HWCAP: - hwcaps[0] = (uint32_t) elf_auxv.a_un.a_val; - break; - case AT_HWCAP2: - hwcaps[1] = (uint32_t) elf_auxv.a_un.a_val; - break; - } - } else { - cpuinfo_log_warning( - "failed to read %zu bytes from /proc/self/auxv: %zu bytes available", - sizeof(elf_auxv), (size_t) bytes_read); - goto cleanup; - } - } - } while (bytes_read == sizeof(Elf32_auxv_t)); - - /* Success, commit results */ - *hwcap = hwcaps[0]; - *hwcap2 = hwcaps[1]; - result = true; - - cleanup: - if (file != -1) { - close(file); - file = -1; - } - return result; - #endif - } - #endif /* __ANDROID__ */ -#elif CPUINFO_ARCH_ARM64 - void cpuinfo_arm_linux_hwcap_from_getauxval( - uint32_t hwcap[restrict static 1], - uint32_t hwcap2[restrict static 1]) - { - #if CPUINFO_MOCK - *hwcap = mock_hwcap; - *hwcap2 = mock_hwcap2; - #else - *hwcap = (uint32_t) getauxval(AT_HWCAP); - *hwcap2 = (uint32_t) getauxval(AT_HWCAP2); - return ; - #endif + getauxval = (getauxval_function_t)dlsym(libc, "getauxval"); + if (getauxval == NULL) { + cpuinfo_log_info("failed to locate getauxval in libc.so: %s", dlerror()); + goto cleanup; } + + *hwcap = getauxval(AT_HWCAP); + *hwcap2 = getauxval(AT_HWCAP2); + +cleanup: + if (libc != NULL) { + dlclose(libc); + libc = NULL; + } + return getauxval != NULL; +#elif defined(__GLIBC__) && defined(__GLIBC_MINOR__) && (__GLIBC__ > 2 || __GLIBC__ == 2 && __GLIBC_MINOR__ >= 16) + /* GNU/Linux: getauxval is supported since glibc-2.16 */ + *hwcap = getauxval(AT_HWCAP); + *hwcap2 = getauxval(AT_HWCAP2); + return true; +#else + return false; +#endif +} + +#ifdef __ANDROID__ +bool cpuinfo_arm_linux_hwcap_from_procfs(uint32_t hwcap[restrict static 1], uint32_t hwcap2[restrict static 1]) { +#if CPUINFO_MOCK + *hwcap = mock_hwcap; + *hwcap2 = mock_hwcap2; + return true; +#else + uint32_t hwcaps[2] = {0, 0}; + bool result = false; + int file = -1; + + file = open("/proc/self/auxv", O_RDONLY); + if (file == -1) { + cpuinfo_log_warning("failed to open /proc/self/auxv: %s", strerror(errno)); + goto cleanup; + } + + ssize_t bytes_read; + do { + Elf32_auxv_t elf_auxv; + bytes_read = read(file, &elf_auxv, sizeof(Elf32_auxv_t)); + if (bytes_read < 0) { + cpuinfo_log_warning("failed to read /proc/self/auxv: %s", strerror(errno)); + goto cleanup; + } else if (bytes_read > 0) { + if (bytes_read == sizeof(elf_auxv)) { + switch (elf_auxv.a_type) { + case AT_HWCAP: + hwcaps[0] = (uint32_t)elf_auxv.a_un.a_val; + break; + case AT_HWCAP2: + hwcaps[1] = (uint32_t)elf_auxv.a_un.a_val; + break; + } + } else { + cpuinfo_log_warning( + "failed to read %zu bytes from /proc/self/auxv: %zu bytes available", + sizeof(elf_auxv), + (size_t)bytes_read); + goto cleanup; + } + } + } while (bytes_read == sizeof(Elf32_auxv_t)); + + /* Success, commit results */ + *hwcap = hwcaps[0]; + *hwcap2 = hwcaps[1]; + result = true; + +cleanup: + if (file != -1) { + close(file); + file = -1; + } + return result; +#endif +} +#endif /* __ANDROID__ */ +#elif CPUINFO_ARCH_ARM64 +void cpuinfo_arm_linux_hwcap_from_getauxval(uint32_t hwcap[restrict static 1], uint32_t hwcap2[restrict static 1]) { +#if CPUINFO_MOCK + *hwcap = mock_hwcap; + *hwcap2 = mock_hwcap2; +#else + *hwcap = (uint32_t)getauxval(AT_HWCAP); + *hwcap2 = (uint32_t)getauxval(AT_HWCAP2); + return; +#endif +} #endif diff --git a/3rdparty/cpuinfo/src/arm/linux/init.c b/3rdparty/cpuinfo/src/arm/linux/init.c index 2501f39c8d..988f05aaa7 100644 --- a/3rdparty/cpuinfo/src/arm/linux/init.c +++ b/3rdparty/cpuinfo/src/arm/linux/init.c @@ -1,23 +1,22 @@ -#include #include +#include #include #include -#include #include +#include #if defined(__ANDROID__) - #include +#include #endif #include #include -#include #include #include +#include +struct cpuinfo_arm_isa cpuinfo_isa = {0}; -struct cpuinfo_arm_isa cpuinfo_isa = { 0 }; - -static struct cpuinfo_package package = { { 0 } }; +static struct cpuinfo_package package = {{0}}; static inline bool bitmask_all(uint32_t bitfield, uint32_t mask) { return (bitfield & mask) == mask; @@ -32,16 +31,19 @@ static inline int cmp(uint32_t a, uint32_t b) { } static bool cluster_siblings_parser( - uint32_t processor, uint32_t siblings_start, uint32_t siblings_end, - struct cpuinfo_arm_linux_processor* processors) -{ + uint32_t processor, + uint32_t siblings_start, + uint32_t siblings_end, + struct cpuinfo_arm_linux_processor* processors) { processors[processor].flags |= CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER; uint32_t package_leader_id = processors[processor].package_leader_id; for (uint32_t sibling = siblings_start; sibling < siblings_end; sibling++) { if (!bitmask_all(processors[sibling].flags, CPUINFO_LINUX_FLAG_VALID)) { - cpuinfo_log_info("invalid processor %"PRIu32" reported as a sibling for processor %"PRIu32, - sibling, processor); + cpuinfo_log_info( + "invalid processor %" PRIu32 " reported as a sibling for processor %" PRIu32, + sibling, + processor); continue; } @@ -60,14 +62,14 @@ static bool cluster_siblings_parser( } static int cmp_arm_linux_processor(const void* ptr_a, const void* ptr_b) { - const struct cpuinfo_arm_linux_processor* processor_a = (const struct cpuinfo_arm_linux_processor*) ptr_a; - const struct cpuinfo_arm_linux_processor* processor_b = (const struct cpuinfo_arm_linux_processor*) ptr_b; + const struct cpuinfo_arm_linux_processor* processor_a = (const struct cpuinfo_arm_linux_processor*)ptr_a; + const struct cpuinfo_arm_linux_processor* processor_b = (const struct cpuinfo_arm_linux_processor*)ptr_b; /* Move usable processors towards the start of the array */ const bool usable_a = bitmask_all(processor_a->flags, CPUINFO_LINUX_FLAG_VALID); const bool usable_b = bitmask_all(processor_b->flags, CPUINFO_LINUX_FLAG_VALID); if (usable_a != usable_b) { - return (int) usable_b - (int) usable_a; + return (int)usable_b - (int)usable_a; } /* Compare based on core type (e.g. Cortex-A57 < Cortex-A53) */ @@ -95,7 +97,8 @@ static int cmp_arm_linux_processor(const void* ptr_a, const void* ptr_b) { return cluster_a > cluster_b ? -1 : 1; } - /* Compare based on system processor id (i.e. processor 0 < processor 1) */ + /* Compare based on system processor id (i.e. processor 0 < processor 1) + */ const uint32_t id_a = processor_a->system_processor_id; const uint32_t id_b = processor_b->system_processor_id; return cmp(id_a, id_b); @@ -116,14 +119,13 @@ void cpuinfo_arm_linux_init(void) { uint32_t* linux_cpu_to_uarch_index_map = NULL; const uint32_t max_processors_count = cpuinfo_linux_get_max_processors_count(); - cpuinfo_log_debug("system maximum processors count: %"PRIu32, max_processors_count); + cpuinfo_log_debug("system maximum processors count: %" PRIu32, max_processors_count); - const uint32_t max_possible_processors_count = 1 + - cpuinfo_linux_get_max_possible_processor(max_processors_count); - cpuinfo_log_debug("maximum possible processors count: %"PRIu32, max_possible_processors_count); - const uint32_t max_present_processors_count = 1 + - cpuinfo_linux_get_max_present_processor(max_processors_count); - cpuinfo_log_debug("maximum present processors count: %"PRIu32, max_present_processors_count); + const uint32_t max_possible_processors_count = + 1 + cpuinfo_linux_get_max_possible_processor(max_processors_count); + cpuinfo_log_debug("maximum possible processors count: %" PRIu32, max_possible_processors_count); + const uint32_t max_present_processors_count = 1 + cpuinfo_linux_get_max_present_processor(max_processors_count); + cpuinfo_log_debug("maximum present processors count: %" PRIu32, max_present_processors_count); uint32_t valid_processor_mask = 0; uint32_t arm_linux_processors_count = max_processors_count; @@ -143,7 +145,7 @@ void cpuinfo_arm_linux_init(void) { arm_linux_processors = calloc(arm_linux_processors_count, sizeof(struct cpuinfo_arm_linux_processor)); if (arm_linux_processors == NULL) { cpuinfo_log_error( - "failed to allocate %zu bytes for descriptions of %"PRIu32" ARM logical processors", + "failed to allocate %zu bytes for descriptions of %" PRIu32 " ARM logical processors", arm_linux_processors_count * sizeof(struct cpuinfo_arm_linux_processor), arm_linux_processors_count); return; @@ -151,14 +153,16 @@ void cpuinfo_arm_linux_init(void) { if (max_possible_processors_count) { cpuinfo_linux_detect_possible_processors( - arm_linux_processors_count, &arm_linux_processors->flags, + arm_linux_processors_count, + &arm_linux_processors->flags, sizeof(struct cpuinfo_arm_linux_processor), CPUINFO_LINUX_FLAG_POSSIBLE); } if (max_present_processors_count) { cpuinfo_linux_detect_present_processors( - arm_linux_processors_count, &arm_linux_processors->flags, + arm_linux_processors_count, + &arm_linux_processors->flags, sizeof(struct cpuinfo_arm_linux_processor), CPUINFO_LINUX_FLAG_PRESENT); } @@ -173,13 +177,13 @@ void cpuinfo_arm_linux_init(void) { if (!cpuinfo_arm_linux_parse_proc_cpuinfo( #if defined(__ANDROID__) - android_properties.proc_cpuinfo_hardware, + android_properties.proc_cpuinfo_hardware, #else - proc_cpuinfo_hardware, + proc_cpuinfo_hardware, #endif - proc_cpuinfo_revision, - arm_linux_processors_count, - arm_linux_processors)) { + proc_cpuinfo_revision, + arm_linux_processors_count, + arm_linux_processors)) { cpuinfo_log_error("failed to parse processor information from /proc/cpuinfo"); return; } @@ -187,45 +191,49 @@ void cpuinfo_arm_linux_init(void) { for (uint32_t i = 0; i < arm_linux_processors_count; i++) { if (bitmask_all(arm_linux_processors[i].flags, valid_processor_mask)) { arm_linux_processors[i].flags |= CPUINFO_LINUX_FLAG_VALID; - cpuinfo_log_debug("parsed processor %"PRIu32" MIDR 0x%08"PRIx32, - i, arm_linux_processors[i].midr); + cpuinfo_log_debug( + "parsed processor %" PRIu32 " MIDR 0x%08" PRIx32, i, arm_linux_processors[i].midr); } } uint32_t valid_processors = 0, last_midr = 0; - #if CPUINFO_ARCH_ARM +#if CPUINFO_ARCH_ARM uint32_t last_architecture_version = 0, last_architecture_flags = 0; - #endif +#endif for (uint32_t i = 0; i < arm_linux_processors_count; i++) { arm_linux_processors[i].system_processor_id = i; if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { if (arm_linux_processors[i].flags & CPUINFO_ARM_LINUX_VALID_PROCESSOR) { /* - * Processor is in possible and present lists, and also reported in /proc/cpuinfo. - * This processor is availble for compute. + * Processor is in possible and present lists, + * and also reported in /proc/cpuinfo. This + * processor is availble for compute. */ valid_processors += 1; } else { /* - * Processor is in possible and present lists, but not reported in /proc/cpuinfo. - * This is fairly common: high-index processors can be not reported if they are offline. + * Processor is in possible and present lists, + * but not reported in /proc/cpuinfo. This is + * fairly common: high-index processors can be + * not reported if they are offline. */ - cpuinfo_log_info("processor %"PRIu32" is not listed in /proc/cpuinfo", i); + cpuinfo_log_info("processor %" PRIu32 " is not listed in /proc/cpuinfo", i); } if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_ARM_LINUX_VALID_MIDR)) { last_midr = arm_linux_processors[i].midr; } - #if CPUINFO_ARCH_ARM - if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_ARM_LINUX_VALID_ARCHITECTURE)) { - last_architecture_version = arm_linux_processors[i].architecture_version; - last_architecture_flags = arm_linux_processors[i].architecture_flags; - } - #endif +#if CPUINFO_ARCH_ARM + if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_ARM_LINUX_VALID_ARCHITECTURE)) { + last_architecture_version = arm_linux_processors[i].architecture_version; + last_architecture_flags = arm_linux_processors[i].architecture_flags; + } +#endif } else { - /* Processor reported in /proc/cpuinfo, but not in possible and/or present lists: log and ignore */ + /* Processor reported in /proc/cpuinfo, but not in + * possible and/or present lists: log and ignore */ if (!(arm_linux_processors[i].flags & CPUINFO_ARM_LINUX_VALID_PROCESSOR)) { - cpuinfo_log_warning("invalid processor %"PRIu32" reported in /proc/cpuinfo", i); + cpuinfo_log_warning("invalid processor %" PRIu32 " reported in /proc/cpuinfo", i); } } } @@ -238,55 +246,65 @@ void cpuinfo_arm_linux_init(void) { cpuinfo_arm_linux_decode_chipset(proc_cpuinfo_hardware, proc_cpuinfo_revision, valid_processors, 0); #endif - #if CPUINFO_ARCH_ARM - uint32_t isa_features = 0, isa_features2 = 0; - #ifdef __ANDROID__ +#if CPUINFO_ARCH_ARM + uint32_t isa_features = 0, isa_features2 = 0; +#ifdef __ANDROID__ + /* + * On Android before API 20, libc.so does not provide getauxval + * function. Thus, we try to dynamically find it, or use two fallback + * mechanisms: + * 1. dlopen libc.so, and try to find getauxval + * 2. Parse /proc/self/auxv procfs file + * 3. Use features reported in /proc/cpuinfo + */ + if (!cpuinfo_arm_linux_hwcap_from_getauxval(&isa_features, &isa_features2)) { + /* getauxval can't be used, fall back to parsing /proc/self/auxv + */ + if (!cpuinfo_arm_linux_hwcap_from_procfs(&isa_features, &isa_features2)) { /* - * On Android before API 20, libc.so does not provide getauxval function. - * Thus, we try to dynamically find it, or use two fallback mechanisms: - * 1. dlopen libc.so, and try to find getauxval - * 2. Parse /proc/self/auxv procfs file - * 3. Use features reported in /proc/cpuinfo + * Reading /proc/self/auxv failed, probably due to file + * permissions. Use information from /proc/cpuinfo to + * detect ISA. + * + * If different processors report different ISA + * features, take the intersection. */ - if (!cpuinfo_arm_linux_hwcap_from_getauxval(&isa_features, &isa_features2)) { - /* getauxval can't be used, fall back to parsing /proc/self/auxv */ - if (!cpuinfo_arm_linux_hwcap_from_procfs(&isa_features, &isa_features2)) { - /* - * Reading /proc/self/auxv failed, probably due to file permissions. - * Use information from /proc/cpuinfo to detect ISA. - * - * If different processors report different ISA features, take the intersection. - */ - uint32_t processors_with_features = 0; - for (uint32_t i = 0; i < arm_linux_processors_count; i++) { - if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_LINUX_FLAG_VALID | CPUINFO_ARM_LINUX_VALID_FEATURES)) { - if (processors_with_features == 0) { - isa_features = arm_linux_processors[i].features; - isa_features2 = arm_linux_processors[i].features2; - } else { - isa_features &= arm_linux_processors[i].features; - isa_features2 &= arm_linux_processors[i].features2; - } - processors_with_features += 1; - } + uint32_t processors_with_features = 0; + for (uint32_t i = 0; i < arm_linux_processors_count; i++) { + if (bitmask_all( + arm_linux_processors[i].flags, + CPUINFO_LINUX_FLAG_VALID | CPUINFO_ARM_LINUX_VALID_FEATURES)) { + if (processors_with_features == 0) { + isa_features = arm_linux_processors[i].features; + isa_features2 = arm_linux_processors[i].features2; + } else { + isa_features &= arm_linux_processors[i].features; + isa_features2 &= arm_linux_processors[i].features2; } + processors_with_features += 1; } } - #else - /* On GNU/Linux getauxval is always available */ - cpuinfo_arm_linux_hwcap_from_getauxval(&isa_features, &isa_features2); - #endif - cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( - isa_features, isa_features2, - last_midr, last_architecture_version, last_architecture_flags, - &chipset, &cpuinfo_isa); - #elif CPUINFO_ARCH_ARM64 - uint32_t isa_features = 0, isa_features2 = 0; - /* getauxval is always available on ARM64 Android */ - cpuinfo_arm_linux_hwcap_from_getauxval(&isa_features, &isa_features2); - cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( - isa_features, isa_features2, last_midr, &chipset, &cpuinfo_isa); - #endif + } + } +#else + /* On GNU/Linux getauxval is always available */ + cpuinfo_arm_linux_hwcap_from_getauxval(&isa_features, &isa_features2); +#endif + cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( + isa_features, + isa_features2, + last_midr, + last_architecture_version, + last_architecture_flags, + &chipset, + &cpuinfo_isa); +#elif CPUINFO_ARCH_ARM64 + uint32_t isa_features = 0, isa_features2 = 0; + /* getauxval is always available on ARM64 Android */ + cpuinfo_arm_linux_hwcap_from_getauxval(&isa_features, &isa_features2); + cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( + isa_features, isa_features2, last_midr, &chipset, &cpuinfo_isa); +#endif /* Detect min/max frequency and package ID */ for (uint32_t i = 0; i < arm_linux_processors_count; i++) { @@ -322,8 +340,9 @@ void cpuinfo_arm_linux_init(void) { if (arm_linux_processors[i].flags & CPUINFO_LINUX_FLAG_PACKAGE_ID) { cpuinfo_linux_detect_core_siblings( - arm_linux_processors_count, i, - (cpuinfo_siblings_callback) cluster_siblings_parser, + arm_linux_processors_count, + i, + (cpuinfo_siblings_callback)cluster_siblings_parser, arm_linux_processors); } } @@ -331,79 +350,107 @@ void cpuinfo_arm_linux_init(void) { /* Propagate all cluster IDs */ uint32_t clustered_processors = 0; for (uint32_t i = 0; i < arm_linux_processors_count; i++) { - if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_LINUX_FLAG_VALID | CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER)) { + if (bitmask_all( + arm_linux_processors[i].flags, + CPUINFO_LINUX_FLAG_VALID | CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER)) { clustered_processors += 1; const uint32_t package_leader_id = arm_linux_processors[i].package_leader_id; if (package_leader_id < i) { - arm_linux_processors[i].package_leader_id = arm_linux_processors[package_leader_id].package_leader_id; + arm_linux_processors[i].package_leader_id = + arm_linux_processors[package_leader_id].package_leader_id; } - cpuinfo_log_debug("processor %"PRIu32" clustered with processor %"PRIu32" as inferred from system siblings lists", - i, arm_linux_processors[i].package_leader_id); + cpuinfo_log_debug( + "processor %" PRIu32 " clustered with processor %" PRIu32 + " as inferred from system siblings lists", + i, + arm_linux_processors[i].package_leader_id); } } if (clustered_processors != valid_processors) { /* - * Topology information about some or all logical processors may be unavailable, for the following reasons: - * - Linux kernel is too old, or configured without support for topology information in sysfs. - * - Core is offline, and Linux kernel is configured to not report topology for offline cores. + * Topology information about some or all logical processors may + * be unavailable, for the following reasons: + * - Linux kernel is too old, or configured without support for + * topology information in sysfs. + * - Core is offline, and Linux kernel is configured to not + * report topology for offline cores. * - * In this case, we assign processors to clusters using two methods: - * - Try heuristic cluster configurations (e.g. 6-core SoC usually has 4+2 big.LITTLE configuration). - * - If heuristic failed, assign processors to core clusters in a sequential scan. + * In this case, we assign processors to clusters using two + * methods: + * - Try heuristic cluster configurations (e.g. 6-core SoC + * usually has 4+2 big.LITTLE configuration). + * - If heuristic failed, assign processors to core clusters in + * a sequential scan. */ - if (!cpuinfo_arm_linux_detect_core_clusters_by_heuristic(valid_processors, arm_linux_processors_count, arm_linux_processors)) { - cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan(arm_linux_processors_count, arm_linux_processors); + if (!cpuinfo_arm_linux_detect_core_clusters_by_heuristic( + valid_processors, arm_linux_processors_count, arm_linux_processors)) { + cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan( + arm_linux_processors_count, arm_linux_processors); } } cpuinfo_arm_linux_count_cluster_processors(arm_linux_processors_count, arm_linux_processors); const uint32_t cluster_count = cpuinfo_arm_linux_detect_cluster_midr( - &chipset, - arm_linux_processors_count, valid_processors, arm_linux_processors); + &chipset, arm_linux_processors_count, valid_processors, arm_linux_processors); - /* Initialize core vendor, uarch, MIDR, and frequency for every logical processor */ + /* Initialize core vendor, uarch, MIDR, and frequency for every logical + * processor */ for (uint32_t i = 0; i < arm_linux_processors_count; i++) { if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { const uint32_t cluster_leader = arm_linux_processors[i].package_leader_id; if (cluster_leader == i) { - /* Cluster leader: decode core vendor and uarch */ + /* Cluster leader: decode core vendor and uarch + */ cpuinfo_arm_decode_vendor_uarch( - arm_linux_processors[cluster_leader].midr, + arm_linux_processors[cluster_leader].midr, #if CPUINFO_ARCH_ARM - !!(arm_linux_processors[cluster_leader].features & CPUINFO_ARM_LINUX_FEATURE_VFPV4), + !!(arm_linux_processors[cluster_leader].features & + CPUINFO_ARM_LINUX_FEATURE_VFPV4), #endif - &arm_linux_processors[cluster_leader].vendor, - &arm_linux_processors[cluster_leader].uarch); + &arm_linux_processors[cluster_leader].vendor, + &arm_linux_processors[cluster_leader].uarch); } else { - /* Cluster non-leader: copy vendor, uarch, MIDR, and frequency from cluster leader */ + /* Cluster non-leader: copy vendor, uarch, MIDR, + * and frequency from cluster leader */ arm_linux_processors[i].flags |= arm_linux_processors[cluster_leader].flags & (CPUINFO_ARM_LINUX_VALID_MIDR | CPUINFO_LINUX_FLAG_MAX_FREQUENCY); arm_linux_processors[i].midr = arm_linux_processors[cluster_leader].midr; arm_linux_processors[i].vendor = arm_linux_processors[cluster_leader].vendor; arm_linux_processors[i].uarch = arm_linux_processors[cluster_leader].uarch; - arm_linux_processors[i].max_frequency = arm_linux_processors[cluster_leader].max_frequency; + arm_linux_processors[i].max_frequency = + arm_linux_processors[cluster_leader].max_frequency; } } } for (uint32_t i = 0; i < arm_linux_processors_count; i++) { if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { - cpuinfo_log_debug("post-analysis processor %"PRIu32": MIDR %08"PRIx32" frequency %"PRIu32, - i, arm_linux_processors[i].midr, arm_linux_processors[i].max_frequency); + cpuinfo_log_debug( + "post-analysis processor %" PRIu32 ": MIDR %08" PRIx32 " frequency %" PRIu32, + i, + arm_linux_processors[i].midr, + arm_linux_processors[i].max_frequency); } } - qsort(arm_linux_processors, arm_linux_processors_count, - sizeof(struct cpuinfo_arm_linux_processor), cmp_arm_linux_processor); + qsort(arm_linux_processors, + arm_linux_processors_count, + sizeof(struct cpuinfo_arm_linux_processor), + cmp_arm_linux_processor); for (uint32_t i = 0; i < arm_linux_processors_count; i++) { if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { - cpuinfo_log_debug("post-sort processor %"PRIu32": system id %"PRIu32" MIDR %08"PRIx32" frequency %"PRIu32, - i, arm_linux_processors[i].system_processor_id, arm_linux_processors[i].midr, arm_linux_processors[i].max_frequency); + cpuinfo_log_debug( + "post-sort processor %" PRIu32 ": system id %" PRIu32 " MIDR %08" PRIx32 + " frequency %" PRIu32, + i, + arm_linux_processors[i].system_processor_id, + arm_linux_processors[i].midr, + arm_linux_processors[i].max_frequency); } } @@ -422,8 +469,10 @@ void cpuinfo_arm_linux_init(void) { /* * Assumptions: * - No SMP (i.e. each core supports only one hardware thread). - * - Level 1 instruction and data caches are private to the core clusters. - * - Level 2 and level 3 cache is shared between cores in the same cluster. + * - Level 1 instruction and data caches are private to the core + * clusters. + * - Level 2 and level 3 cache is shared between cores in the same + * cluster. */ cpuinfo_arm_chipset_to_string(&chipset, package.name); package.processor_count = valid_processors; @@ -432,66 +481,84 @@ void cpuinfo_arm_linux_init(void) { processors = calloc(valid_processors, sizeof(struct cpuinfo_processor)); if (processors == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" logical processors", - valid_processors * sizeof(struct cpuinfo_processor), valid_processors); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " logical processors", + valid_processors * sizeof(struct cpuinfo_processor), + valid_processors); goto cleanup; } cores = calloc(valid_processors, sizeof(struct cpuinfo_core)); if (cores == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" cores", - valid_processors * sizeof(struct cpuinfo_core), valid_processors); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " cores", + valid_processors * sizeof(struct cpuinfo_core), + valid_processors); goto cleanup; } clusters = calloc(cluster_count, sizeof(struct cpuinfo_cluster)); if (clusters == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" core clusters", - cluster_count * sizeof(struct cpuinfo_cluster), cluster_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " core clusters", + cluster_count * sizeof(struct cpuinfo_cluster), + cluster_count); goto cleanup; } uarchs = calloc(uarchs_count, sizeof(struct cpuinfo_uarch_info)); if (uarchs == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" microarchitectures", - uarchs_count * sizeof(struct cpuinfo_uarch_info), uarchs_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " microarchitectures", + uarchs_count * sizeof(struct cpuinfo_uarch_info), + uarchs_count); goto cleanup; } linux_cpu_to_processor_map = calloc(arm_linux_processors_count, sizeof(struct cpuinfo_processor*)); if (linux_cpu_to_processor_map == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %"PRIu32" logical processor mapping entries", - arm_linux_processors_count * sizeof(struct cpuinfo_processor*), arm_linux_processors_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for %" PRIu32 " logical processor mapping entries", + arm_linux_processors_count * sizeof(struct cpuinfo_processor*), + arm_linux_processors_count); goto cleanup; } linux_cpu_to_core_map = calloc(arm_linux_processors_count, sizeof(struct cpuinfo_core*)); if (linux_cpu_to_core_map == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %"PRIu32" core mapping entries", - arm_linux_processors_count * sizeof(struct cpuinfo_core*), arm_linux_processors_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for %" PRIu32 " core mapping entries", + arm_linux_processors_count * sizeof(struct cpuinfo_core*), + arm_linux_processors_count); goto cleanup; } if (uarchs_count > 1) { linux_cpu_to_uarch_index_map = calloc(arm_linux_processors_count, sizeof(uint32_t)); if (linux_cpu_to_uarch_index_map == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %"PRIu32" uarch index mapping entries", - arm_linux_processors_count * sizeof(uint32_t), arm_linux_processors_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for %" PRIu32 " uarch index mapping entries", + arm_linux_processors_count * sizeof(uint32_t), + arm_linux_processors_count); goto cleanup; } } l1i = calloc(valid_processors, sizeof(struct cpuinfo_cache)); if (l1i == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1I caches", - valid_processors * sizeof(struct cpuinfo_cache), valid_processors); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1I caches", + valid_processors * sizeof(struct cpuinfo_cache), + valid_processors); goto cleanup; } l1d = calloc(valid_processors, sizeof(struct cpuinfo_cache)); if (l1d == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1D caches", - valid_processors * sizeof(struct cpuinfo_cache), valid_processors); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1D caches", + valid_processors * sizeof(struct cpuinfo_cache), + valid_processors); goto cleanup; } @@ -500,7 +567,7 @@ void cpuinfo_arm_linux_init(void) { if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { if (uarchs_index == 0 || arm_linux_processors[i].uarch != last_uarch) { last_uarch = arm_linux_processors[i].uarch; - uarchs[uarchs_index] = (struct cpuinfo_uarch_info) { + uarchs[uarchs_index] = (struct cpuinfo_uarch_info){ .uarch = arm_linux_processors[i].uarch, .midr = arm_linux_processors[i].midr, }; @@ -518,7 +585,7 @@ void cpuinfo_arm_linux_init(void) { for (uint32_t i = 0; i < valid_processors; i++) { if (arm_linux_processors[i].package_leader_id == arm_linux_processors[i].system_processor_id) { cluster_id += 1; - clusters[cluster_id] = (struct cpuinfo_cluster) { + clusters[cluster_id] = (struct cpuinfo_cluster){ .processor_start = i, .processor_count = arm_linux_processors[i].package_processor_count, .core_start = i, @@ -535,7 +602,7 @@ void cpuinfo_arm_linux_init(void) { processors[i].core = cores + i; processors[i].cluster = clusters + cluster_id; processors[i].package = &package; - processors[i].linux_id = (int) arm_linux_processors[i].system_processor_id; + processors[i].linux_id = (int)arm_linux_processors[i].system_processor_id; processors[i].cache.l1i = l1i + i; processors[i].cache.l1d = l1d + i; linux_cpu_to_processor_map[arm_linux_processors[i].system_processor_id] = &processors[i]; @@ -555,7 +622,7 @@ void cpuinfo_arm_linux_init(void) { arm_linux_processors[i].uarch_index; } - struct cpuinfo_cache temp_l2 = { 0 }, temp_l3 = { 0 }; + struct cpuinfo_cache temp_l2 = {0}, temp_l3 = {0}; cpuinfo_arm_decode_cache( arm_linux_processors[i].uarch, arm_linux_processors[i].package_processor_count, @@ -563,38 +630,40 @@ void cpuinfo_arm_linux_init(void) { &chipset, cluster_id, arm_linux_processors[i].architecture_version, - &l1i[i], &l1d[i], &temp_l2, &temp_l3); + &l1i[i], + &l1d[i], + &temp_l2, + &temp_l3); l1i[i].processor_start = l1d[i].processor_start = i; l1i[i].processor_count = l1d[i].processor_count = 1; - #if CPUINFO_ARCH_ARM - /* L1I reported in /proc/cpuinfo overrides defaults */ - if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_ARM_LINUX_VALID_ICACHE)) { - l1i[i] = (struct cpuinfo_cache) { - .size = arm_linux_processors[i].proc_cpuinfo_cache.i_size, - .associativity = arm_linux_processors[i].proc_cpuinfo_cache.i_assoc, - .sets = arm_linux_processors[i].proc_cpuinfo_cache.i_sets, - .partitions = 1, - .line_size = arm_linux_processors[i].proc_cpuinfo_cache.i_line_length - }; - } - /* L1D reported in /proc/cpuinfo overrides defaults */ - if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_ARM_LINUX_VALID_DCACHE)) { - l1d[i] = (struct cpuinfo_cache) { - .size = arm_linux_processors[i].proc_cpuinfo_cache.d_size, - .associativity = arm_linux_processors[i].proc_cpuinfo_cache.d_assoc, - .sets = arm_linux_processors[i].proc_cpuinfo_cache.d_sets, - .partitions = 1, - .line_size = arm_linux_processors[i].proc_cpuinfo_cache.d_line_length - }; - } - #endif +#if CPUINFO_ARCH_ARM + /* L1I reported in /proc/cpuinfo overrides defaults */ + if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_ARM_LINUX_VALID_ICACHE)) { + l1i[i] = (struct cpuinfo_cache){ + .size = arm_linux_processors[i].proc_cpuinfo_cache.i_size, + .associativity = arm_linux_processors[i].proc_cpuinfo_cache.i_assoc, + .sets = arm_linux_processors[i].proc_cpuinfo_cache.i_sets, + .partitions = 1, + .line_size = arm_linux_processors[i].proc_cpuinfo_cache.i_line_length}; + } + /* L1D reported in /proc/cpuinfo overrides defaults */ + if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_ARM_LINUX_VALID_DCACHE)) { + l1d[i] = (struct cpuinfo_cache){ + .size = arm_linux_processors[i].proc_cpuinfo_cache.d_size, + .associativity = arm_linux_processors[i].proc_cpuinfo_cache.d_assoc, + .sets = arm_linux_processors[i].proc_cpuinfo_cache.d_sets, + .partitions = 1, + .line_size = arm_linux_processors[i].proc_cpuinfo_cache.d_line_length}; + } +#endif if (temp_l3.size != 0) { /* * Assumptions: * - L2 is private to each core * - L3 is shared by cores in the same cluster - * - If cores in different clusters report the same L3, it is shared between all cores. + * - If cores in different clusters report the same L3, + * it is shared between all cores. */ l2_count += 1; if (arm_linux_processors[i].package_leader_id == arm_linux_processors[i].system_processor_id) { @@ -602,17 +671,22 @@ void cpuinfo_arm_linux_init(void) { big_l3_size = temp_l3.size; l3_count = 1; } else if (temp_l3.size != big_l3_size) { - /* If some cores have different L3 size, L3 is not shared between all cores */ + /* If some cores have different L3 size, + * L3 is not shared between all cores */ shared_l3 = false; l3_count += 1; } } } else { - /* If some cores don't have L3 cache, L3 is not shared between all cores */ + /* If some cores don't have L3 cache, L3 is not shared + * between all cores + */ shared_l3 = false; if (temp_l2.size != 0) { - /* Assume L2 is shared by cores in the same cluster */ - if (arm_linux_processors[i].package_leader_id == arm_linux_processors[i].system_processor_id) { + /* Assume L2 is shared by cores in the same + * cluster */ + if (arm_linux_processors[i].package_leader_id == + arm_linux_processors[i].system_processor_id) { l2_count += 1; } } @@ -622,16 +696,20 @@ void cpuinfo_arm_linux_init(void) { if (l2_count != 0) { l2 = calloc(l2_count, sizeof(struct cpuinfo_cache)); if (l2 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L2 caches", - l2_count * sizeof(struct cpuinfo_cache), l2_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L2 caches", + l2_count * sizeof(struct cpuinfo_cache), + l2_count); goto cleanup; } if (l3_count != 0) { l3 = calloc(l3_count, sizeof(struct cpuinfo_cache)); if (l3 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L3 caches", - l3_count * sizeof(struct cpuinfo_cache), l3_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L3 caches", + l3_count * sizeof(struct cpuinfo_cache), + l3_count); goto cleanup; } } @@ -644,7 +722,7 @@ void cpuinfo_arm_linux_init(void) { cluster_id++; } - struct cpuinfo_cache dummy_l1i, dummy_l1d, temp_l2 = { 0 }, temp_l3 = { 0 }; + struct cpuinfo_cache dummy_l1i, dummy_l1d, temp_l2 = {0}, temp_l3 = {0}; cpuinfo_arm_decode_cache( arm_linux_processors[i].uarch, arm_linux_processors[i].package_processor_count, @@ -652,23 +730,27 @@ void cpuinfo_arm_linux_init(void) { &chipset, cluster_id, arm_linux_processors[i].architecture_version, - &dummy_l1i, &dummy_l1d, &temp_l2, &temp_l3); + &dummy_l1i, + &dummy_l1d, + &temp_l2, + &temp_l3); if (temp_l3.size != 0) { /* * Assumptions: * - L2 is private to each core * - L3 is shared by cores in the same cluster - * - If cores in different clusters report the same L3, it is shared between all cores. + * - If cores in different clusters report the same L3, + * it is shared between all cores. */ l2_index += 1; - l2[l2_index] = (struct cpuinfo_cache) { - .size = temp_l2.size, - .associativity = temp_l2.associativity, - .sets = temp_l2.sets, - .partitions = 1, - .line_size = temp_l2.line_size, - .flags = temp_l2.flags, + l2[l2_index] = (struct cpuinfo_cache){ + .size = temp_l2.size, + .associativity = temp_l2.associativity, + .sets = temp_l2.sets, + .partitions = 1, + .line_size = temp_l2.line_size, + .flags = temp_l2.flags, .processor_start = i, .processor_count = 1, }; @@ -676,16 +758,17 @@ void cpuinfo_arm_linux_init(void) { if (arm_linux_processors[i].package_leader_id == arm_linux_processors[i].system_processor_id) { l3_index += 1; if (l3_index < l3_count) { - l3[l3_index] = (struct cpuinfo_cache) { - .size = temp_l3.size, - .associativity = temp_l3.associativity, - .sets = temp_l3.sets, - .partitions = 1, - .line_size = temp_l3.line_size, - .flags = temp_l3.flags, + l3[l3_index] = (struct cpuinfo_cache){ + .size = temp_l3.size, + .associativity = temp_l3.associativity, + .sets = temp_l3.sets, + .partitions = 1, + .line_size = temp_l3.line_size, + .flags = temp_l3.flags, .processor_start = i, - .processor_count = - shared_l3 ? valid_processors : arm_linux_processors[i].package_processor_count, + .processor_count = shared_l3 + ? valid_processors + : arm_linux_processors[i].package_processor_count, }; } } @@ -698,13 +781,13 @@ void cpuinfo_arm_linux_init(void) { /* Assume L2 is shared by cores in the same cluster */ if (arm_linux_processors[i].package_leader_id == arm_linux_processors[i].system_processor_id) { l2_index += 1; - l2[l2_index] = (struct cpuinfo_cache) { - .size = temp_l2.size, - .associativity = temp_l2.associativity, - .sets = temp_l2.sets, - .partitions = 1, - .line_size = temp_l2.line_size, - .flags = temp_l2.flags, + l2[l2_index] = (struct cpuinfo_cache){ + .size = temp_l2.size, + .associativity = temp_l2.associativity, + .sets = temp_l2.sets, + .partitions = 1, + .line_size = temp_l2.line_size, + .flags = temp_l2.flags, .processor_start = i, .processor_count = arm_linux_processors[i].package_processor_count, }; @@ -721,8 +804,8 @@ void cpuinfo_arm_linux_init(void) { cpuinfo_uarchs = uarchs; cpuinfo_cache[cpuinfo_cache_level_1i] = l1i; cpuinfo_cache[cpuinfo_cache_level_1d] = l1d; - cpuinfo_cache[cpuinfo_cache_level_2] = l2; - cpuinfo_cache[cpuinfo_cache_level_3] = l3; + cpuinfo_cache[cpuinfo_cache_level_2] = l2; + cpuinfo_cache[cpuinfo_cache_level_3] = l3; cpuinfo_processors_count = valid_processors; cpuinfo_cores_count = valid_processors; @@ -731,8 +814,8 @@ void cpuinfo_arm_linux_init(void) { cpuinfo_uarchs_count = uarchs_count; cpuinfo_cache_count[cpuinfo_cache_level_1i] = valid_processors; cpuinfo_cache_count[cpuinfo_cache_level_1d] = valid_processors; - cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; - cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; + cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; + cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; cpuinfo_max_cache_size = cpuinfo_arm_compute_max_cache_size(&processors[0]); cpuinfo_linux_cpu_max = arm_linux_processors_count; diff --git a/3rdparty/cpuinfo/src/arm/linux/midr.c b/3rdparty/cpuinfo/src/arm/linux/midr.c index 0d8f03fa82..10db278849 100644 --- a/3rdparty/cpuinfo/src/arm/linux/midr.c +++ b/3rdparty/cpuinfo/src/arm/linux/midr.c @@ -1,20 +1,19 @@ -#include #include +#include #include #include -#include #include +#include #if defined(__ANDROID__) - #include +#include #endif #include #include -#include +#include #include #include -#include - +#include #define CLUSTERS_MAX 3 @@ -22,7 +21,8 @@ static inline bool bitmask_all(uint32_t bitfield, uint32_t mask) { return (bitfield & mask) == mask; } -/* Description of core clusters configuration in a chipset (identified by series and model number) */ +/* Description of core clusters configuration in a chipset (identified by series + * and model number) */ struct cluster_config { /* Number of cores (logical processors) */ uint8_t cores; @@ -36,29 +36,36 @@ struct cluster_config { * Number of cores in each cluster: # - Symmetric configurations: [0] = # cores * - big.LITTLE configurations: [0] = # LITTLE cores, [1] = # big cores - * - Max.Med.Min configurations: [0] = # Min cores, [1] = # Med cores, [2] = # Max cores + * - Max.Med.Min configurations: [0] = # Min cores, [1] = # Med cores, + [2] = # Max cores */ uint8_t cluster_cores[CLUSTERS_MAX]; /* * MIDR of cores in each cluster: * - Symmetric configurations: [0] = core MIDR - * - big.LITTLE configurations: [0] = LITTLE core MIDR, [1] = big core MIDR - * - Max.Med.Min configurations: [0] = Min core MIDR, [1] = Med core MIDR, [2] = Max core MIDR + * - big.LITTLE configurations: [0] = LITTLE core MIDR, [1] = big core + * MIDR + * - Max.Med.Min configurations: [0] = Min core MIDR, [1] = Med core + * MIDR, [2] = Max core MIDR */ uint32_t cluster_midr[CLUSTERS_MAX]; }; /* - * The list of chipsets where MIDR may not be unambigiously decoded at least on some devices. - * The typical reasons for impossibility to decoded MIDRs are buggy kernels, which either do not report all MIDR - * information (e.g. on ATM7029 kernel doesn't report CPU Part), or chipsets have more than one type of cores - * (i.e. 4x Cortex-A53 + 4x Cortex-A53 is out) and buggy kernels report MIDR information only about some cores - * in /proc/cpuinfo (either only online cores, or only the core that reads /proc/cpuinfo). On these kernels/chipsets, - * it is not possible to detect all core types by just parsing /proc/cpuinfo, so we use chipset name and this table to - * find their MIDR (and thus microarchitecture, cache, etc). + * The list of chipsets where MIDR may not be unambigiously decoded at least on + * some devices. The typical reasons for impossibility to decoded MIDRs are + * buggy kernels, which either do not report all MIDR information (e.g. on + * ATM7029 kernel doesn't report CPU Part), or chipsets have more than one type + * of cores (i.e. 4x Cortex-A53 + 4x Cortex-A53 is out) and buggy kernels report + * MIDR information only about some cores in /proc/cpuinfo (either only online + * cores, or only the core that reads /proc/cpuinfo). On these kernels/chipsets, + * it is not possible to detect all core types by just parsing /proc/cpuinfo, so + * we use chipset name and this table to find their MIDR (and thus + * microarchitecture, cache, etc). * - * Note: not all chipsets with heterogeneous multiprocessing need an entry in this table. The following HMP - * chipsets always list information about all cores in /proc/cpuinfo: + * Note: not all chipsets with heterogeneous multiprocessing need an entry in + * this table. The following HMP chipsets always list information about all + * cores in /proc/cpuinfo: * * - Snapdragon 660 * - Snapdragon 820 (MSM8996) @@ -67,446 +74,510 @@ struct cluster_config { * - Exynos 8895 * - Kirin 960 * - * As these are all new processors, there is hope that this table won't uncontrollably grow over time. + * As these are all new processors, there is hope that this table won't + * uncontrollably grow over time. */ -static const struct cluster_config cluster_configs[] = { +static const struct cluster_config + cluster_configs[] = + { #if CPUINFO_ARCH_ARM - { - /* - * MSM8916 (Snapdragon 410): 4x Cortex-A53 - * Some AArch32 phones use non-standard /proc/cpuinfo format. - */ - .cores = 4, - .series = cpuinfo_arm_chipset_series_qualcomm_msm, - .model = UINT16_C(8916), - .clusters = 1, - .cluster_cores = { - [0] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD030), - }, - }, - { - /* - * MSM8939 (Snapdragon 615): 4x Cortex-A53 + 4x Cortex-A53 - * Some AArch32 phones use non-standard /proc/cpuinfo format. - */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_qualcomm_msm, - .model = UINT16_C(8939), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD034), - [1] = UINT32_C(0x410FD034), - }, - }, + { + /* + * MSM8916 (Snapdragon 410): 4x Cortex-A53 + * Some AArch32 phones use non-standard /proc/cpuinfo format. + */ + .cores = 4, + .series = cpuinfo_arm_chipset_series_qualcomm_msm, + .model = UINT16_C(8916), + .clusters = 1, + .cluster_cores = + { + [0] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD030), + }, + }, + { + /* + * MSM8939 (Snapdragon 615): 4x Cortex-A53 + 4x Cortex-A53 + * Some AArch32 phones use non-standard /proc/cpuinfo format. + */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_qualcomm_msm, + .model = UINT16_C(8939), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD034), + [1] = UINT32_C(0x410FD034), + }, + }, #endif - { - /* MSM8956 (Snapdragon 650): 2x Cortex-A72 + 4x Cortex-A53 */ - .cores = 6, - .series = cpuinfo_arm_chipset_series_qualcomm_msm, - .model = UINT16_C(8956), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 2, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD034), - [1] = UINT32_C(0x410FD080), - }, - }, - { - /* MSM8976/MSM8976PRO (Snapdragon 652/653): 4x Cortex-A72 + 4x Cortex-A53 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_qualcomm_msm, - .model = UINT16_C(8976), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD034), - [1] = UINT32_C(0x410FD080), - }, - }, - { - /* MSM8992 (Snapdragon 808): 2x Cortex-A57 + 4x Cortex-A53 */ - .cores = 6, - .series = cpuinfo_arm_chipset_series_qualcomm_msm, - .model = UINT16_C(8992), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 2, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD033), - [1] = UINT32_C(0x411FD072), - }, - }, - { - /* MSM8994/MSM8994V (Snapdragon 810): 4x Cortex-A57 + 4x Cortex-A53 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_qualcomm_msm, - .model = UINT16_C(8994), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD032), - [1] = UINT32_C(0x411FD071), - }, - }, + { + /* MSM8956 (Snapdragon 650): 2x Cortex-A72 + 4x Cortex-A53 */ + .cores = 6, + .series = cpuinfo_arm_chipset_series_qualcomm_msm, + .model = UINT16_C(8956), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 2, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD034), + [1] = UINT32_C(0x410FD080), + }, + }, + { + /* MSM8976/MSM8976PRO (Snapdragon 652/653): 4x Cortex-A72 + 4x + Cortex-A53 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_qualcomm_msm, + .model = UINT16_C(8976), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD034), + [1] = UINT32_C(0x410FD080), + }, + }, + { + /* MSM8992 (Snapdragon 808): 2x Cortex-A57 + 4x Cortex-A53 */ + .cores = 6, + .series = cpuinfo_arm_chipset_series_qualcomm_msm, + .model = UINT16_C(8992), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 2, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD033), + [1] = UINT32_C(0x411FD072), + }, + }, + { + /* MSM8994/MSM8994V (Snapdragon 810): 4x Cortex-A57 + 4x + Cortex-A53 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_qualcomm_msm, + .model = UINT16_C(8994), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD032), + [1] = UINT32_C(0x411FD071), + }, + }, #if CPUINFO_ARCH_ARM - { - /* Exynos 5422: 4x Cortex-A15 + 4x Cortex-A7 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_samsung_exynos, - .model = UINT16_C(5422), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FC073), - [1] = UINT32_C(0x412FC0F3), - }, - }, - { - /* Exynos 5430: 4x Cortex-A15 + 4x Cortex-A7 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_samsung_exynos, - .model = UINT16_C(5430), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FC074), - [1] = UINT32_C(0x413FC0F3), - }, - }, + { + /* Exynos 5422: 4x Cortex-A15 + 4x Cortex-A7 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_samsung_exynos, + .model = UINT16_C(5422), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FC073), + [1] = UINT32_C(0x412FC0F3), + }, + }, + { + /* Exynos 5430: 4x Cortex-A15 + 4x Cortex-A7 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_samsung_exynos, + .model = UINT16_C(5430), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FC074), + [1] = UINT32_C(0x413FC0F3), + }, + }, #endif /* CPUINFO_ARCH_ARM */ - { - /* Exynos 5433: 4x Cortex-A57 + 4x Cortex-A53 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_samsung_exynos, - .model = UINT16_C(5433), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD031), - [1] = UINT32_C(0x411FD070), - }, - }, - { - /* Exynos 7420: 4x Cortex-A57 + 4x Cortex-A53 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_samsung_exynos, - .model = UINT16_C(7420), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD032), - [1] = UINT32_C(0x411FD070), - }, - }, - { - /* Exynos 8890: 4x Exynos M1 + 4x Cortex-A53 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_samsung_exynos, - .model = UINT16_C(8890), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD034), - [1] = UINT32_C(0x531F0011), - }, - }, + { + /* Exynos 5433: 4x Cortex-A57 + 4x Cortex-A53 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_samsung_exynos, + .model = UINT16_C(5433), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD031), + [1] = UINT32_C(0x411FD070), + }, + }, + { + /* Exynos 7420: 4x Cortex-A57 + 4x Cortex-A53 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_samsung_exynos, + .model = UINT16_C(7420), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD032), + [1] = UINT32_C(0x411FD070), + }, + }, + { + /* Exynos 8890: 4x Exynos M1 + 4x Cortex-A53 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_samsung_exynos, + .model = UINT16_C(8890), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD034), + [1] = UINT32_C(0x531F0011), + }, + }, #if CPUINFO_ARCH_ARM - { - /* Kirin 920: 4x Cortex-A15 + 4x Cortex-A7 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = UINT16_C(920), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FC075), - [1] = UINT32_C(0x413FC0F3), - }, - }, - { - /* Kirin 925: 4x Cortex-A15 + 4x Cortex-A7 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = UINT16_C(925), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FC075), - [1] = UINT32_C(0x413FC0F3), - }, - }, - { - /* Kirin 928: 4x Cortex-A15 + 4x Cortex-A7 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = UINT16_C(928), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FC075), - [1] = UINT32_C(0x413FC0F3), - }, - }, + { + /* Kirin 920: 4x Cortex-A15 + 4x Cortex-A7 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = UINT16_C(920), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FC075), + [1] = UINT32_C(0x413FC0F3), + }, + }, + { + /* Kirin 925: 4x Cortex-A15 + 4x Cortex-A7 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = UINT16_C(925), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FC075), + [1] = UINT32_C(0x413FC0F3), + }, + }, + { + /* Kirin 928: 4x Cortex-A15 + 4x Cortex-A7 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = UINT16_C(928), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FC075), + [1] = UINT32_C(0x413FC0F3), + }, + }, #endif /* CPUINFO_ARCH_ARM */ - { - /* Kirin 950: 4x Cortex-A72 + 4x Cortex-A53 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = UINT16_C(950), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD034), - [1] = UINT32_C(0x410FD080), - }, - }, - { - /* Kirin 955: 4x Cortex-A72 + 4x Cortex-A53 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = UINT16_C(955), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD034), - [1] = UINT32_C(0x410FD080), - }, - }, + { + /* Kirin 950: 4x Cortex-A72 + 4x Cortex-A53 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = UINT16_C(950), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD034), + [1] = UINT32_C(0x410FD080), + }, + }, + { + /* Kirin 955: 4x Cortex-A72 + 4x Cortex-A53 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = UINT16_C(955), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD034), + [1] = UINT32_C(0x410FD080), + }, + }, #if CPUINFO_ARCH_ARM - { - /* MediaTek MT8135: 2x Cortex-A7 + 2x Cortex-A15 */ - .cores = 4, - .series = cpuinfo_arm_chipset_series_mediatek_mt, - .model = UINT16_C(8135), - .clusters = 2, - .cluster_cores = { - [0] = 2, - [1] = 2, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FC073), - [1] = UINT32_C(0x413FC0F2), - }, - }, + { + /* MediaTek MT8135: 2x Cortex-A7 + 2x Cortex-A15 */ + .cores = 4, + .series = cpuinfo_arm_chipset_series_mediatek_mt, + .model = UINT16_C(8135), + .clusters = 2, + .cluster_cores = + { + [0] = 2, + [1] = 2, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FC073), + [1] = UINT32_C(0x413FC0F2), + }, + }, #endif - { - /* MediaTek MT8173: 2x Cortex-A72 + 2x Cortex-A53 */ - .cores = 4, - .series = cpuinfo_arm_chipset_series_mediatek_mt, - .model = UINT16_C(8173), - .clusters = 2, - .cluster_cores = { - [0] = 2, - [1] = 2, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD032), - [1] = UINT32_C(0x410FD080), - }, - }, - { - /* MediaTek MT8176: 2x Cortex-A72 + 4x Cortex-A53 */ - .cores = 6, - .series = cpuinfo_arm_chipset_series_mediatek_mt, - .model = UINT16_C(8176), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 2, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD032), - [1] = UINT32_C(0x410FD080), - }, - }, + { + /* MediaTek MT8173: 2x Cortex-A72 + 2x Cortex-A53 */ + .cores = 4, + .series = cpuinfo_arm_chipset_series_mediatek_mt, + .model = UINT16_C(8173), + .clusters = 2, + .cluster_cores = + { + [0] = 2, + [1] = 2, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD032), + [1] = UINT32_C(0x410FD080), + }, + }, + { + /* MediaTek MT8176: 2x Cortex-A72 + 4x Cortex-A53 */ + .cores = 6, + .series = cpuinfo_arm_chipset_series_mediatek_mt, + .model = UINT16_C(8176), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 2, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD032), + [1] = UINT32_C(0x410FD080), + }, + }, #if CPUINFO_ARCH_ARM64 - { - /* - * MediaTek MT8735: 4x Cortex-A53 - * Some AArch64 phones use non-standard /proc/cpuinfo format. - */ - .cores = 4, - .series = cpuinfo_arm_chipset_series_mediatek_mt, - .model = UINT16_C(8735), - .clusters = 1, - .cluster_cores = { - [0] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD034), - }, - }, + { + /* + * MediaTek MT8735: 4x Cortex-A53 + * Some AArch64 phones use non-standard /proc/cpuinfo format. + */ + .cores = 4, + .series = cpuinfo_arm_chipset_series_mediatek_mt, + .model = UINT16_C(8735), + .clusters = 1, + .cluster_cores = + { + [0] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD034), + }, + }, #endif #if CPUINFO_ARCH_ARM - { - /* - * MediaTek MT6592: 4x Cortex-A7 + 4x Cortex-A7 - * Some phones use non-standard /proc/cpuinfo format. - */ - .cores = 4, - .series = cpuinfo_arm_chipset_series_mediatek_mt, - .model = UINT16_C(6592), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FC074), - [1] = UINT32_C(0x410FC074), - }, - }, - { - /* MediaTek MT6595: 4x Cortex-A17 + 4x Cortex-A7 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_mediatek_mt, - .model = UINT16_C(6595), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FC075), - [1] = UINT32_C(0x410FC0E0), - }, - }, + { + /* + * MediaTek MT6592: 4x Cortex-A7 + 4x Cortex-A7 + * Some phones use non-standard /proc/cpuinfo format. + */ + .cores = 4, + .series = cpuinfo_arm_chipset_series_mediatek_mt, + .model = UINT16_C(6592), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FC074), + [1] = UINT32_C(0x410FC074), + }, + }, + { + /* MediaTek MT6595: 4x Cortex-A17 + 4x Cortex-A7 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_mediatek_mt, + .model = UINT16_C(6595), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FC075), + [1] = UINT32_C(0x410FC0E0), + }, + }, #endif - { - /* MediaTek MT6797: 2x Cortex-A72 + 4x Cortex-A53 + 4x Cortex-A53 */ - .cores = 10, - .series = cpuinfo_arm_chipset_series_mediatek_mt, - .model = UINT16_C(6797), - .clusters = 3, - .cluster_cores = { - [0] = 4, - [1] = 4, - [2] = 2, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD034), - [1] = UINT32_C(0x410FD034), - [2] = UINT32_C(0x410FD081), - }, - }, - { - /* MediaTek MT6799: 2x Cortex-A73 + 4x Cortex-A53 + 4x Cortex-A35 */ - .cores = 10, - .series = cpuinfo_arm_chipset_series_mediatek_mt, - .model = UINT16_C(6799), - .clusters = 3, - .cluster_cores = { - [0] = 4, - [1] = 4, - [2] = 2, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD041), - [1] = UINT32_C(0x410FD034), - [2] = UINT32_C(0x410FD092), - }, - }, - { - /* Rockchip RK3399: 2x Cortex-A72 + 4x Cortex-A53 */ - .cores = 6, - .series = cpuinfo_arm_chipset_series_rockchip_rk, - .model = UINT16_C(3399), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 2, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD034), - [1] = UINT32_C(0x410FD082), - }, - }, + { + /* MediaTek MT6797: 2x Cortex-A72 + 4x Cortex-A53 + 4x + Cortex-A53 */ + .cores = 10, + .series = cpuinfo_arm_chipset_series_mediatek_mt, + .model = UINT16_C(6797), + .clusters = 3, + .cluster_cores = + { + [0] = 4, + [1] = 4, + [2] = 2, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD034), + [1] = UINT32_C(0x410FD034), + [2] = UINT32_C(0x410FD081), + }, + }, + { + /* MediaTek MT6799: 2x Cortex-A73 + 4x Cortex-A53 + 4x + Cortex-A35 */ + .cores = 10, + .series = cpuinfo_arm_chipset_series_mediatek_mt, + .model = UINT16_C(6799), + .clusters = 3, + .cluster_cores = + { + [0] = 4, + [1] = 4, + [2] = 2, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD041), + [1] = UINT32_C(0x410FD034), + [2] = UINT32_C(0x410FD092), + }, + }, + { + /* Rockchip RK3399: 2x Cortex-A72 + 4x Cortex-A53 */ + .cores = 6, + .series = cpuinfo_arm_chipset_series_rockchip_rk, + .model = UINT16_C(3399), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 2, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD034), + [1] = UINT32_C(0x410FD082), + }, + }, #if CPUINFO_ARCH_ARM - { - /* Actions ATM8029: 4x Cortex-A5 - * Most devices use non-standard /proc/cpuinfo format. - */ - .cores = 4, - .series = cpuinfo_arm_chipset_series_actions_atm, - .model = UINT16_C(7029), - .clusters = 1, - .cluster_cores = { - [0] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FC051), - }, - }, + { + /* Actions ATM8029: 4x Cortex-A5 + * Most devices use non-standard /proc/cpuinfo format. + */ + .cores = 4, + .series = cpuinfo_arm_chipset_series_actions_atm, + .model = UINT16_C(7029), + .clusters = 1, + .cluster_cores = + { + [0] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FC051), + }, + }, #endif }; /* - * Searches chipset name in mapping of chipset name to cores' MIDR values. If match is successful, initializes MIDR - * for all clusters' leaders with tabulated values. + * Searches chipset name in mapping of chipset name to cores' MIDR values. If + * match is successful, initializes MIDR for all clusters' leaders with + * tabulated values. * * @param[in] chipset - chipset (SoC) name information. * @param clusters_count - number of CPU core clusters detected in the SoC. - * @param cluster_leaders - indices of core clusters' leaders in the @p processors array. + * @param cluster_leaders - indices of core clusters' leaders in the @p + * processors array. * @param processors_count - number of usable logical processors in the system. - * @param[in,out] processors - array of logical processor descriptions with pre-parsed MIDR, maximum frequency, - * and decoded core cluster (package_leader_id) information. - * Upon successful return, processors[i].midr for all clusters' leaders contains the - * tabulated MIDR values. - * @param verify_midr - indicated whether the function should check that the MIDR values to be assigned to leaders of - * core clusters are consistent with known parts of their parsed values. - * Set if to false if the only MIDR value parsed from /proc/cpuinfo is for the last processor - * reported in /proc/cpuinfo and thus can't be unambiguously attributed to that processor. + * @param[in,out] processors - array of logical processor descriptions with + * pre-parsed MIDR, maximum frequency, and decoded core cluster + * (package_leader_id) information. Upon successful return, processors[i].midr + * for all clusters' leaders contains the tabulated MIDR values. + * @param verify_midr - indicated whether the function should check that the + * MIDR values to be assigned to leaders of core clusters are consistent with + * known parts of their parsed values. Set if to false if the only MIDR value + * parsed from /proc/cpuinfo is for the last processor reported in /proc/cpuinfo + * and thus can't be unambiguously attributed to that processor. * - * @retval true if the chipset was found in the mapping and core clusters' leaders initialized with MIDR values. - * @retval false if the chipset was not found in the mapping, or any consistency check failed. + * @retval true if the chipset was found in the mapping and core clusters' + * leaders initialized with MIDR values. + * @retval false if the chipset was not found in the mapping, or any consistency + * check failed. */ static bool cpuinfo_arm_linux_detect_cluster_midr_by_chipset( const struct cpuinfo_arm_chipset chipset[restrict static 1], @@ -514,20 +585,24 @@ static bool cpuinfo_arm_linux_detect_cluster_midr_by_chipset( const uint32_t cluster_leaders[restrict static CLUSTERS_MAX], uint32_t processors_count, struct cpuinfo_arm_linux_processor processors[restrict static processors_count], - bool verify_midr) -{ + bool verify_midr) { if (clusters_count <= CLUSTERS_MAX) { for (uint32_t c = 0; c < CPUINFO_COUNT_OF(cluster_configs); c++) { - if (cluster_configs[c].model == chipset->model && cluster_configs[c].series == chipset->series) { - /* Verify that the total number of cores and clusters of cores matches expectation */ - if (cluster_configs[c].cores != processors_count || cluster_configs[c].clusters != clusters_count) { + if (cluster_configs[c].model == chipset->model && + cluster_configs[c].series == chipset->series) { + /* Verify that the total number of cores and + * clusters of cores matches expectation */ + if (cluster_configs[c].cores != processors_count || + cluster_configs[c].clusters != clusters_count) { return false; } - /* Verify that core cluster configuration matches expectation */ + /* Verify that core cluster configuration + * matches expectation */ for (uint32_t cluster = 0; cluster < clusters_count; cluster++) { const uint32_t cluster_leader = cluster_leaders[cluster]; - if (cluster_configs[c].cluster_cores[cluster] != processors[cluster_leader].package_processor_count) { + if (cluster_configs[c].cluster_cores[cluster] != + processors[cluster_leader].package_processor_count) { return false; } } @@ -537,36 +612,50 @@ static bool cpuinfo_arm_linux_detect_cluster_midr_by_chipset( for (uint32_t cluster = 0; cluster < clusters_count; cluster++) { const uint32_t cluster_leader = cluster_leaders[cluster]; - /* Create a mask of known midr bits */ + /* Create a mask of known midr + * bits */ uint32_t midr_mask = 0; - if (processors[cluster_leader].flags & CPUINFO_ARM_LINUX_VALID_IMPLEMENTER) { + if (processors[cluster_leader].flags & + CPUINFO_ARM_LINUX_VALID_IMPLEMENTER) { midr_mask |= CPUINFO_ARM_MIDR_IMPLEMENTER_MASK; } - if (processors[cluster_leader].flags & CPUINFO_ARM_LINUX_VALID_VARIANT) { + if (processors[cluster_leader].flags & + CPUINFO_ARM_LINUX_VALID_VARIANT) { midr_mask |= CPUINFO_ARM_MIDR_VARIANT_MASK; } if (processors[cluster_leader].flags & CPUINFO_ARM_LINUX_VALID_PART) { midr_mask |= CPUINFO_ARM_MIDR_PART_MASK; } - if (processors[cluster_leader].flags & CPUINFO_ARM_LINUX_VALID_REVISION) { + if (processors[cluster_leader].flags & + CPUINFO_ARM_LINUX_VALID_REVISION) { midr_mask |= CPUINFO_ARM_MIDR_REVISION_MASK; } - /* Verify the bits under the mask */ - if ((processors[cluster_leader].midr ^ cluster_configs[c].cluster_midr[cluster]) & midr_mask) { - cpuinfo_log_debug("parsed MIDR of cluster %08"PRIu32" does not match tabulated value %08"PRIu32, - processors[cluster_leader].midr, cluster_configs[c].cluster_midr[cluster]); + /* Verify the bits under the + * mask */ + if ((processors[cluster_leader].midr ^ + cluster_configs[c].cluster_midr[cluster]) & + midr_mask) { + cpuinfo_log_debug( + "parsed MIDR of cluster %08" PRIu32 + " does not match tabulated value %08" PRIu32, + processors[cluster_leader].midr, + cluster_configs[c].cluster_midr[cluster]); return false; } } } - /* Assign MIDRs according to tabulated configurations */ + /* Assign MIDRs according to tabulated + * configurations */ for (uint32_t cluster = 0; cluster < clusters_count; cluster++) { const uint32_t cluster_leader = cluster_leaders[cluster]; processors[cluster_leader].midr = cluster_configs[c].cluster_midr[cluster]; processors[cluster_leader].flags |= CPUINFO_ARM_LINUX_VALID_MIDR; - cpuinfo_log_debug("cluster %"PRIu32" MIDR = 0x%08"PRIx32, cluster, cluster_configs[c].cluster_midr[cluster]); + cpuinfo_log_debug( + "cluster %" PRIu32 " MIDR = 0x%08" PRIx32, + cluster, + cluster_configs[c].cluster_midr[cluster]); } return true; } @@ -576,26 +665,35 @@ static bool cpuinfo_arm_linux_detect_cluster_midr_by_chipset( } /* - * Initializes MIDR for leaders of core clusters using a heuristic for big.LITTLE systems: - * - If the only known MIDR is for the big core cluster, guess the matching MIDR for the LITTLE cluster. - * - Estimate which of the clusters is big using maximum frequency, if known, otherwise using system processor ID. - * - Initialize the MIDR for big and LITTLE core clusters using the guesstimates values. + * Initializes MIDR for leaders of core clusters using a heuristic for + * big.LITTLE systems: + * - If the only known MIDR is for the big core cluster, guess the matching MIDR + * for the LITTLE cluster. + * - Estimate which of the clusters is big using maximum frequency, if known, + * otherwise using system processor ID. + * - Initialize the MIDR for big and LITTLE core clusters using the guesstimates + * values. * * @param clusters_count - number of CPU core clusters detected in the SoC. - * @param cluster_with_midr_count - number of CPU core clusters in the SoC with known MIDR values. - * @param last_processor_with_midr - index of the last logical processor with known MIDR in the @p processors array. - * @param cluster_leaders - indices of core clusters' leaders in the @p processors array. - * @param[in,out] processors - array of logical processor descriptions with pre-parsed MIDR, maximum frequency, - * and decoded core cluster (package_leader_id) information. - * Upon successful return, processors[i].midr for all core clusters' leaders contains - * the heuristically detected MIDR value. - * @param verify_midr - indicated whether the function should check that the MIDR values to be assigned to leaders of - * core clusters are consistent with known parts of their parsed values. - * Set if to false if the only MIDR value parsed from /proc/cpuinfo is for the last processor - * reported in /proc/cpuinfo and thus can't be unambiguously attributed to that processor. + * @param cluster_with_midr_count - number of CPU core clusters in the SoC with + * known MIDR values. + * @param last_processor_with_midr - index of the last logical processor with + * known MIDR in the @p processors array. + * @param cluster_leaders - indices of core clusters' leaders in the @p + * processors array. + * @param[in,out] processors - array of logical processor descriptions with + * pre-parsed MIDR, maximum frequency, and decoded core cluster + * (package_leader_id) information. Upon successful return, processors[i].midr + * for all core clusters' leaders contains the heuristically detected MIDR + * value. + * @param verify_midr - indicated whether the function should check that the + * MIDR values to be assigned to leaders of core clusters are consistent with + * known parts of their parsed values. Set if to false if the only MIDR value + * parsed from /proc/cpuinfo is for the last processor reported in /proc/cpuinfo + * and thus can't be unambiguously attributed to that processor. * - * @retval true if this is a big.LITTLE system with only one known MIDR and the CPU core clusters' leaders were - * initialized with MIDR values. + * @retval true if this is a big.LITTLE system with only one known MIDR and the + * CPU core clusters' leaders were initialized with MIDR values. * @retval false if this is not a big.LITTLE system. */ static bool cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic( @@ -604,23 +702,27 @@ static bool cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic( uint32_t last_processor_with_midr, const uint32_t cluster_leaders[restrict static CLUSTERS_MAX], struct cpuinfo_arm_linux_processor processors[restrict static last_processor_with_midr], - bool verify_midr) -{ + bool verify_midr) { if (clusters_count != 2 || cluster_with_midr_count != 1) { - /* Not a big.LITTLE system, or MIDR is known for both/neither clusters */ + /* Not a big.LITTLE system, or MIDR is known for both/neither + * clusters */ return false; } const uint32_t midr_flags = - (processors[processors[last_processor_with_midr].package_leader_id].flags & CPUINFO_ARM_LINUX_VALID_MIDR); + (processors[processors[last_processor_with_midr].package_leader_id].flags & + CPUINFO_ARM_LINUX_VALID_MIDR); const uint32_t big_midr = processors[processors[last_processor_with_midr].package_leader_id].midr; const uint32_t little_midr = midr_little_core_for_big(big_midr); - /* Default assumption: the first reported cluster is LITTLE cluster (this holds on most Linux kernels) */ + /* Default assumption: the first reported cluster is LITTLE cluster + * (this holds on most Linux kernels) */ uint32_t little_cluster_leader = cluster_leaders[0]; const uint32_t other_cluster_leader = cluster_leaders[1]; - /* If maximum frequency is known for both clusters, assume LITTLE cluster is the one with lower frequency */ - if (processors[little_cluster_leader].flags & processors[other_cluster_leader].flags & CPUINFO_LINUX_FLAG_MAX_FREQUENCY) { + /* If maximum frequency is known for both clusters, assume LITTLE + * cluster is the one with lower frequency */ + if (processors[little_cluster_leader].flags & processors[other_cluster_leader].flags & + CPUINFO_LINUX_FLAG_MAX_FREQUENCY) { if (processors[little_cluster_leader].max_frequency > processors[other_cluster_leader].max_frequency) { little_cluster_leader = other_cluster_leader; } @@ -650,8 +752,11 @@ static bool cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic( const uint32_t midr = (cluster_leader == little_cluster_leader) ? little_midr : big_midr; if ((processors[cluster_leader].midr ^ midr) & midr_mask) { cpuinfo_log_debug( - "parsed MIDR %08"PRIu32" of cluster leader %"PRIu32" is inconsistent with expected value %08"PRIu32, - processors[cluster_leader].midr, cluster_leader, midr); + "parsed MIDR %08" PRIu32 " of cluster leader %" PRIu32 + " is inconsistent with expected value %08" PRIu32, + processors[cluster_leader].midr, + cluster_leader, + midr); return false; } } @@ -665,8 +770,9 @@ static bool cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic( } const uint32_t midr = (cluster_leader == little_cluster_leader) ? little_midr : big_midr; - cpuinfo_log_info("assume processor %"PRIu32" to have MIDR %08"PRIx32, cluster_leader, midr); - /* To be consistent, we copy the MIDR entirely, rather than by parts */ + cpuinfo_log_info("assume processor %" PRIu32 " to have MIDR %08" PRIx32, cluster_leader, midr); + /* To be consistent, we copy the MIDR entirely, rather than by + * parts */ processors[cluster_leader].midr = midr; processors[cluster_leader].flags |= midr_flags; } @@ -675,21 +781,23 @@ static bool cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic( /* * Initializes MIDR for leaders of core clusters in a single sequential scan: - * - Clusters preceding the first reported MIDR value are assumed to have default MIDR value. + * - Clusters preceding the first reported MIDR value are assumed to have + * default MIDR value. * - Clusters following any reported MIDR value to have that MIDR value. * - * @param default_midr - MIDR value that will be assigned to cluster leaders preceding any reported MIDR value. - * @param processors_count - number of logical processor descriptions in the @p processors array. - * @param[in,out] processors - array of logical processor descriptions with pre-parsed MIDR, maximum frequency, - * and decoded core cluster (package_leader_id) information. - * Upon successful return, processors[i].midr for all core clusters' leaders contains - * the assigned MIDR value. + * @param default_midr - MIDR value that will be assigned to cluster leaders + * preceding any reported MIDR value. + * @param processors_count - number of logical processor descriptions in the @p + * processors array. + * @param[in,out] processors - array of logical processor descriptions with + * pre-parsed MIDR, maximum frequency, and decoded core cluster + * (package_leader_id) information. Upon successful return, processors[i].midr + * for all core clusters' leaders contains the assigned MIDR value. */ static void cpuinfo_arm_linux_detect_cluster_midr_by_sequential_scan( uint32_t default_midr, uint32_t processors_count, - struct cpuinfo_arm_linux_processor processors[restrict static processors_count]) -{ + struct cpuinfo_arm_linux_processor processors[restrict static processors_count]) { uint32_t midr = default_midr; for (uint32_t i = 0; i < processors_count; i++) { if (bitmask_all(processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { @@ -697,8 +805,11 @@ static void cpuinfo_arm_linux_detect_cluster_midr_by_sequential_scan( if (bitmask_all(processors[i].flags, CPUINFO_ARM_LINUX_VALID_MIDR)) { midr = processors[i].midr; } else { - cpuinfo_log_info("assume processor %"PRIu32" to have MIDR %08"PRIx32, i, midr); - /* To be consistent, we copy the MIDR entirely, rather than by parts */ + cpuinfo_log_info( + "assume processor %" PRIu32 " to have MIDR %08" PRIx32, i, midr); + /* To be consistent, we copy the MIDR + * entirely, rather than by parts + */ processors[i].midr = midr; processors[i].flags |= CPUINFO_ARM_LINUX_VALID_MIDR; } @@ -711,12 +822,14 @@ static void cpuinfo_arm_linux_detect_cluster_midr_by_sequential_scan( * Detects MIDR of each CPU core clusters' leader. * * @param[in] chipset - chipset (SoC) name information. - * @param max_processors - number of processor descriptions in the @p processors array. - * @param usable_processors - number of processor descriptions in the @p processors array with both POSSIBLE and - * PRESENT flags. - * @param[in,out] processors - array of logical processor descriptions with pre-parsed MIDR, maximum frequency, - * and decoded core cluster (package_leader_id) information. - * Upon return, processors[i].midr for all clusters' leaders contains the MIDR value. + * @param max_processors - number of processor descriptions in the @p processors + * array. + * @param usable_processors - number of processor descriptions in the @p + * processors array with both POSSIBLE and PRESENT flags. + * @param[in,out] processors - array of logical processor descriptions with + * pre-parsed MIDR, maximum frequency, and decoded core cluster + * (package_leader_id) information. Upon return, processors[i].midr for all + * clusters' leaders contains the MIDR value. * * @returns The number of core clusters */ @@ -724,8 +837,7 @@ uint32_t cpuinfo_arm_linux_detect_cluster_midr( const struct cpuinfo_arm_chipset chipset[restrict static 1], uint32_t max_processors, uint32_t usable_processors, - struct cpuinfo_arm_linux_processor processors[restrict static max_processors]) -{ + struct cpuinfo_arm_linux_processor processors[restrict static max_processors]) { uint32_t clusters_count = 0; uint32_t cluster_leaders[CLUSTERS_MAX]; uint32_t last_processor_in_cpuinfo = max_processors; @@ -736,7 +848,9 @@ uint32_t cpuinfo_arm_linux_detect_cluster_midr( if (processors[i].flags & CPUINFO_ARM_LINUX_VALID_PROCESSOR) { last_processor_in_cpuinfo = i; } - if (bitmask_all(processors[i].flags, CPUINFO_ARM_LINUX_VALID_IMPLEMENTER | CPUINFO_ARM_LINUX_VALID_PART)) { + if (bitmask_all( + processors[i].flags, + CPUINFO_ARM_LINUX_VALID_IMPLEMENTER | CPUINFO_ARM_LINUX_VALID_PART)) { last_processor_with_midr = i; processors_with_midr_count += 1; } @@ -747,73 +861,86 @@ uint32_t cpuinfo_arm_linux_detect_cluster_midr( } clusters_count += 1; } else { - /* Copy known bits of information to cluster leader */ + /* Copy known bits of information to cluster + * leader */ - if ((processors[i].flags & ~processors[group_leader].flags) & CPUINFO_LINUX_FLAG_MAX_FREQUENCY) { + if ((processors[i].flags & ~processors[group_leader].flags) & + CPUINFO_LINUX_FLAG_MAX_FREQUENCY) { processors[group_leader].max_frequency = processors[i].max_frequency; processors[group_leader].flags |= CPUINFO_LINUX_FLAG_MAX_FREQUENCY; } if (!bitmask_all(processors[group_leader].flags, CPUINFO_ARM_LINUX_VALID_MIDR) && - bitmask_all(processors[i].flags, CPUINFO_ARM_LINUX_VALID_MIDR)) - { + bitmask_all(processors[i].flags, CPUINFO_ARM_LINUX_VALID_MIDR)) { processors[group_leader].midr = processors[i].midr; processors[group_leader].flags |= CPUINFO_ARM_LINUX_VALID_MIDR; } } } } - cpuinfo_log_debug("detected %"PRIu32" core clusters", clusters_count); + cpuinfo_log_debug("detected %" PRIu32 " core clusters", clusters_count); /* - * Two relations between reported /proc/cpuinfo information, and cores is possible: - * - /proc/cpuinfo reports information for all or some of the cores below the corresponding - * "processor : " lines. Information on offline cores may be missing. - * - /proc/cpuinfo reports information only once, after all "processor : " lines. - * The reported information may relate to processor #0 or to the processor which - * executed the system calls to read /proc/cpuinfo. It is also indistinguishable - * from /proc/cpuinfo reporting information only for the last core (e.g. if all other - * cores are offline). + * Two relations between reported /proc/cpuinfo information, and cores + * is possible: + * - /proc/cpuinfo reports information for all or some of the cores + * below the corresponding "processor : " lines. Information on + * offline cores may be missing. + * - /proc/cpuinfo reports information only once, after all "processor : + * " lines. The reported information may relate to processor #0 + * or to the processor which executed the system calls to read + * /proc/cpuinfo. It is also indistinguishable from /proc/cpuinfo + * reporting information only for the last core (e.g. if all other cores + * are offline). * - * We detect the second case by checking if /proc/cpuinfo contains valid MIDR only for one, - * last reported, processor. Note, that the last reported core may be not the last - * present & possible processor, as /proc/cpuinfo may non-report high-index offline cores. + * We detect the second case by checking if /proc/cpuinfo contains valid + * MIDR only for one, last reported, processor. Note, that the last + * reported core may be not the last present & possible processor, as + * /proc/cpuinfo may non-report high-index offline cores. */ - if (processors_with_midr_count == 1 && last_processor_in_cpuinfo == last_processor_with_midr && clusters_count > 1) { + if (processors_with_midr_count == 1 && last_processor_in_cpuinfo == last_processor_with_midr && + clusters_count > 1) { /* - * There are multiple core clusters, but /proc/cpuinfo reported MIDR only for one - * processor, and we don't even know which logical processor this information refers to. + * There are multiple core clusters, but /proc/cpuinfo reported + * MIDR only for one processor, and we don't even know which + * logical processor this information refers to. * * We make three attempts to detect MIDR for all clusters: - * 1. Search tabulated MIDR values for chipsets which have heterogeneous clusters and ship with Linux - * kernels which do not always report all cores in /proc/cpuinfo. If found, use the tabulated values. - * 2. For systems with 2 clusters and MIDR known for one cluster, assume big.LITTLE configuration, - * and estimate MIDR for the other cluster under assumption that MIDR for the big cluster is known. - * 3. Initialize MIDRs for all core clusters to the only parsed MIDR value. + * 1. Search tabulated MIDR values for chipsets which have + * heterogeneous clusters and ship with Linux kernels which do + * not always report all cores in /proc/cpuinfo. If found, use + * the tabulated values. + * 2. For systems with 2 clusters and MIDR known for one + * cluster, assume big.LITTLE configuration, and estimate MIDR + * for the other cluster under assumption that MIDR for the big + * cluster is known. + * 3. Initialize MIDRs for all core clusters to the only parsed + * MIDR value. */ cpuinfo_log_debug("the only reported MIDR can not be attributed to a particular processor"); if (cpuinfo_arm_linux_detect_cluster_midr_by_chipset( - chipset, clusters_count, cluster_leaders, usable_processors, processors, false)) - { + chipset, clusters_count, cluster_leaders, usable_processors, processors, false)) { return clusters_count; } /* Try big.LITTLE heuristic */ if (cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic( - clusters_count, 1, last_processor_with_midr, - cluster_leaders, processors, false)) - { + clusters_count, 1, last_processor_with_midr, cluster_leaders, processors, false)) { return clusters_count; } - /* Fall back to sequential initialization of MIDR values for core clusters */ + /* Fall back to sequential initialization of MIDR values for + * core clusters + */ cpuinfo_arm_linux_detect_cluster_midr_by_sequential_scan( processors[processors[last_processor_with_midr].package_leader_id].midr, - max_processors, processors); + max_processors, + processors); } else if (processors_with_midr_count < usable_processors) { /* - * /proc/cpuinfo reported MIDR only for some processors, and probably some core clusters do not have MIDR - * for any of the cores. Check if this is the case. + * /proc/cpuinfo reported MIDR only for some processors, and + * probably some core clusters do not have MIDR for any of the + * cores. Check if this is the case. */ uint32_t clusters_with_midr_count = 0; for (uint32_t i = 0; i < max_processors; i++) { @@ -826,36 +953,48 @@ uint32_t cpuinfo_arm_linux_detect_cluster_midr( if (clusters_with_midr_count < clusters_count) { /* - * /proc/cpuinfo reported MIDR only for some clusters, need to reconstruct others. - * We make three attempts to detect MIDR for clusters without it: - * 1. Search tabulated MIDR values for chipsets which have heterogeneous clusters and ship with Linux - * kernels which do not always report all cores in /proc/cpuinfo. If found, use the tabulated values. - * 2. For systems with 2 clusters and MIDR known for one cluster, assume big.LITTLE configuration, - * and estimate MIDR for the other cluster under assumption that MIDR for the big cluster is known. - * 3. Initialize MIDRs for core clusters in a single sequential scan: - * - Clusters preceding the first reported MIDR value are assumed to have the last reported MIDR value. - * - Clusters following any reported MIDR value to have that MIDR value. + * /proc/cpuinfo reported MIDR only for some clusters, + * need to reconstruct others. We make three attempts to + * detect MIDR for clusters without it: + * 1. Search tabulated MIDR values for chipsets which + * have heterogeneous clusters and ship with Linux + * kernels which do not always report all cores in + * /proc/cpuinfo. If found, use the tabulated values. + * 2. For systems with 2 clusters and MIDR known for one + * cluster, assume big.LITTLE configuration, and + * estimate MIDR for the other cluster under assumption + * that MIDR for the big cluster is known. + * 3. Initialize MIDRs for core clusters in a single + * sequential scan: + * - Clusters preceding the first reported MIDR value + * are assumed to have the last reported MIDR value. + * - Clusters following any reported MIDR value to + * have that MIDR value. */ if (cpuinfo_arm_linux_detect_cluster_midr_by_chipset( - chipset, clusters_count, cluster_leaders, usable_processors, processors, true)) - { + chipset, clusters_count, cluster_leaders, usable_processors, processors, true)) { return clusters_count; } if (last_processor_with_midr != max_processors) { /* Try big.LITTLE heuristic */ if (cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic( - clusters_count, processors_with_midr_count, last_processor_with_midr, - cluster_leaders, processors, true)) - { + clusters_count, + processors_with_midr_count, + last_processor_with_midr, + cluster_leaders, + processors, + true)) { return clusters_count; } - /* Fall back to sequential initialization of MIDR values for core clusters */ + /* Fall back to sequential initialization of + * MIDR values for core clusters */ cpuinfo_arm_linux_detect_cluster_midr_by_sequential_scan( processors[processors[last_processor_with_midr].package_leader_id].midr, - max_processors, processors); + max_processors, + processors); } } } diff --git a/3rdparty/cpuinfo/src/arm/mach/init.c b/3rdparty/cpuinfo/src/arm/mach/init.c index 6a28b2db2f..9d83c05a95 100644 --- a/3rdparty/cpuinfo/src/arm/mach/init.c +++ b/3rdparty/cpuinfo/src/arm/mach/init.c @@ -1,31 +1,31 @@ -#include +#include #include +#include #include #include -#include #include -#include -#include #include +#include +#include #include -#include #include #include +#include /* Polyfill recent CPUFAMILY_ARM_* values for older SDKs */ #ifndef CPUFAMILY_ARM_VORTEX_TEMPEST - #define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07D34B9F +#define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07D34B9F #endif #ifndef CPUFAMILY_ARM_LIGHTNING_THUNDER - #define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504D2 +#define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504D2 #endif #ifndef CPUFAMILY_ARM_FIRESTORM_ICESTORM - #define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1B588BB3 +#define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1B588BB3 #endif #ifndef CPUFAMILY_ARM_AVALANCHE_BLIZZARD - #define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xDA33D83D +#define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xDA33D83D #endif struct cpuinfo_arm_isa cpuinfo_isa = { @@ -39,12 +39,12 @@ struct cpuinfo_arm_isa cpuinfo_isa = { static uint32_t get_sys_info(int type_specifier, const char* name) { size_t size = 0; uint32_t result = 0; - int mib[2] = { CTL_HW, type_specifier }; + int mib[2] = {CTL_HW, type_specifier}; if (sysctl(mib, 2, NULL, &size, NULL, 0) != 0) { cpuinfo_log_info("sysctl(\"%s\") failed: %s", name, strerror(errno)); } else if (size == sizeof(uint32_t)) { sysctl(mib, 2, &result, &size, NULL, 0); - cpuinfo_log_debug("%s: %"PRIu32 ", size = %lu", name, result, size); + cpuinfo_log_debug("%s: %" PRIu32 ", size = %lu", name, result, size); } else { cpuinfo_log_info("sysctl does not support non-integer lookup for (\"%s\")", name); } @@ -58,7 +58,7 @@ static uint32_t get_sys_info_by_name(const char* type_specifier) { cpuinfo_log_info("sysctlbyname(\"%s\") failed: %s", type_specifier, strerror(errno)); } else if (size == sizeof(uint32_t)) { sysctlbyname(type_specifier, &result, &size, NULL, 0); - cpuinfo_log_debug("%s: %"PRIu32 ", size = %lu", type_specifier, result, size); + cpuinfo_log_debug("%s: %" PRIu32 ", size = %lu", type_specifier, result, size); } else { cpuinfo_log_info("sysctl does not support non-integer lookup for (\"%s\")", type_specifier); } @@ -79,13 +79,16 @@ static enum cpuinfo_uarch decode_uarch(uint32_t cpu_family, uint32_t core_index, /* 2x Monsoon + 4x Mistral cores */ return core_index < 2 ? cpuinfo_uarch_monsoon : cpuinfo_uarch_mistral; case CPUFAMILY_ARM_VORTEX_TEMPEST: - /* Hexa-core: 2x Vortex + 4x Tempest; Octa-core: 4x Cortex + 4x Tempest */ + /* Hexa-core: 2x Vortex + 4x Tempest; Octa-core: 4x + * Cortex + 4x Tempest */ return core_index + 4 < core_count ? cpuinfo_uarch_vortex : cpuinfo_uarch_tempest; case CPUFAMILY_ARM_LIGHTNING_THUNDER: - /* Hexa-core: 2x Lightning + 4x Thunder; Octa-core (presumed): 4x Lightning + 4x Thunder */ + /* Hexa-core: 2x Lightning + 4x Thunder; Octa-core + * (presumed): 4x Lightning + 4x Thunder */ return core_index + 4 < core_count ? cpuinfo_uarch_lightning : cpuinfo_uarch_thunder; case CPUFAMILY_ARM_FIRESTORM_ICESTORM: - /* Hexa-core: 2x Firestorm + 4x Icestorm; Octa-core: 4x Firestorm + 4x Icestorm */ + /* Hexa-core: 2x Firestorm + 4x Icestorm; Octa-core: 4x + * Firestorm + 4x Icestorm */ return core_index + 4 < core_count ? cpuinfo_uarch_firestorm : cpuinfo_uarch_icestorm; case CPUFAMILY_ARM_AVALANCHE_BLIZZARD: /* Hexa-core: 2x Avalanche + 4x Blizzard */ @@ -105,7 +108,7 @@ static void decode_package_name(char* package_name) { return; } - char *machine_name = alloca(size); + char* machine_name = alloca(size); if (sysctlbyname("hw.machine", machine_name, &size, NULL, 0) != 0) { cpuinfo_log_warning("sysctlbyname(\"hw.machine\") failed: %s", strerror(errno)); return; @@ -114,7 +117,7 @@ static void decode_package_name(char* package_name) { char name[10]; uint32_t major = 0, minor = 0; - if (sscanf(machine_name, "%9[^,0123456789]%"SCNu32",%"SCNu32, name, &major, &minor) != 3) { + if (sscanf(machine_name, "%9[^,0123456789]%" SCNu32 ",%" SCNu32, name, &major, &minor) != 3) { cpuinfo_log_warning("parsing \"hw.machine\" failed: %s", strerror(errno)); return; } @@ -149,8 +152,9 @@ static void decode_package_name(char* package_name) { /* iPad 2 and up are supported */ case 2: /* - * iPad 2 [A5]: iPad2,1, iPad2,2, iPad2,3, iPad2,4 - * iPad mini [A5]: iPad2,5, iPad2,6, iPad2,7 + * iPad 2 [A5]: iPad2,1, iPad2,2, iPad2,3, + * iPad2,4 iPad mini [A5]: iPad2,5, iPad2,6, + * iPad2,7 */ chip_model = major + 3; break; @@ -164,9 +168,10 @@ static void decode_package_name(char* package_name) { break; case 4: /* - * iPad Air [A7]: iPad4,1, iPad4,2, iPad4,3 - * iPad mini Retina [A7]: iPad4,4, iPad4,5, iPad4,6 - * iPad mini 3 [A7]: iPad4,7, iPad4,8, iPad4,9 + * iPad Air [A7]: iPad4,1, iPad4,2, + * iPad4,3 iPad mini Retina [A7]: iPad4,4, + * iPad4,5, iPad4,6 iPad mini 3 [A7]: + * iPad4,7, iPad4,8, iPad4,9 */ chip_model = major + 3; break; @@ -218,7 +223,7 @@ static void decode_package_name(char* package_name) { cpuinfo_log_info("unknown device: %s", machine_name); } if (chip_model != 0) { - snprintf(package_name, CPUINFO_PACKAGE_NAME_MAX, "Apple A%"PRIu32"%c", chip_model, suffix); + snprintf(package_name, CPUINFO_PACKAGE_NAME_MAX, "Apple A%" PRIu32 "%c", chip_model, suffix); } } @@ -236,20 +241,26 @@ void cpuinfo_arm_mach_init(void) { struct cpuinfo_mach_topology mach_topology = cpuinfo_mach_detect_topology(); processors = calloc(mach_topology.threads, sizeof(struct cpuinfo_processor)); if (processors == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" logical processors", - mach_topology.threads * sizeof(struct cpuinfo_processor), mach_topology.threads); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " logical processors", + mach_topology.threads * sizeof(struct cpuinfo_processor), + mach_topology.threads); goto cleanup; } cores = calloc(mach_topology.cores, sizeof(struct cpuinfo_core)); if (cores == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" cores", - mach_topology.cores * sizeof(struct cpuinfo_core), mach_topology.cores); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " cores", + mach_topology.cores * sizeof(struct cpuinfo_core), + mach_topology.cores); goto cleanup; } packages = calloc(mach_topology.packages, sizeof(struct cpuinfo_package)); if (packages == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" packages", - mach_topology.packages * sizeof(struct cpuinfo_package), mach_topology.packages); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " packages", + mach_topology.packages * sizeof(struct cpuinfo_package), + mach_topology.packages); goto cleanup; } @@ -258,7 +269,7 @@ void cpuinfo_arm_mach_init(void) { const uint32_t cores_per_package = mach_topology.cores / mach_topology.packages; for (uint32_t i = 0; i < mach_topology.packages; i++) { - packages[i] = (struct cpuinfo_package) { + packages[i] = (struct cpuinfo_package){ .processor_start = i * threads_per_package, .processor_count = threads_per_package, .core_start = i * cores_per_package, @@ -267,18 +278,19 @@ void cpuinfo_arm_mach_init(void) { decode_package_name(packages[i].name); } - const uint32_t cpu_family = get_sys_info_by_name("hw.cpufamily"); /* - * iOS 15 and macOS 12 added sysctls for ARM features, use them where possible. - * Otherwise, fallback to hardcoded set of CPUs with known support. + * iOS 15 and macOS 12 added sysctls for ARM features, use them where + * possible. Otherwise, fallback to hardcoded set of CPUs with known + * support. */ const uint32_t has_feat_lse = get_sys_info_by_name("hw.optional.arm.FEAT_LSE"); if (has_feat_lse != 0) { cpuinfo_isa.atomics = true; } else { - // Mandatory in ARMv8.1-A, list only cores released before iOS 15 / macOS 12 + // Mandatory in ARMv8.1-A, list only cores released before iOS + // 15 / macOS 12 switch (cpu_family) { case CPUFAMILY_ARM_MONSOON_MISTRAL: case CPUFAMILY_ARM_VORTEX_TEMPEST: @@ -327,8 +339,9 @@ void cpuinfo_arm_mach_init(void) { if (has_feat_fhm_legacy != 0) { cpuinfo_isa.fhm = true; } else { - // Mandatory in ARMv8.4-A when FP16 arithmetics is implemented, - // list only cores released before iOS 15 / macOS 12 + // Mandatory in ARMv8.4-A when FP16 arithmetics is + // implemented, list only cores released before iOS 15 / + // macOS 12 switch (cpu_family) { case CPUFAMILY_ARM_LIGHTNING_THUNDER: case CPUFAMILY_ARM_FIRESTORM_ICESTORM: @@ -346,7 +359,8 @@ void cpuinfo_arm_mach_init(void) { if (has_feat_fcma != 0) { cpuinfo_isa.fcma = true; } else { - // Mandatory in ARMv8.3-A, list only cores released before iOS 15 / macOS 12 + // Mandatory in ARMv8.3-A, list only cores released before iOS + // 15 / macOS 12 switch (cpu_family) { case CPUFAMILY_ARM_LIGHTNING_THUNDER: case CPUFAMILY_ARM_FIRESTORM_ICESTORM: @@ -358,7 +372,8 @@ void cpuinfo_arm_mach_init(void) { if (has_feat_jscvt != 0) { cpuinfo_isa.jscvt = true; } else { - // Mandatory in ARMv8.3-A, list only cores released before iOS 15 / macOS 12 + // Mandatory in ARMv8.3-A, list only cores released before iOS + // 15 / macOS 12 switch (cpu_family) { case CPUFAMILY_ARM_LIGHTNING_THUNDER: case CPUFAMILY_ARM_FIRESTORM_ICESTORM: @@ -370,7 +385,8 @@ void cpuinfo_arm_mach_init(void) { if (has_feat_dotprod != 0) { cpuinfo_isa.dot = true; } else { - // Mandatory in ARMv8.4-A, list only cores released before iOS 15 / macOS 12 + // Mandatory in ARMv8.4-A, list only cores released before iOS + // 15 / macOS 12 switch (cpu_family) { case CPUFAMILY_ARM_LIGHTNING_THUNDER: case CPUFAMILY_ARM_FIRESTORM_ICESTORM: @@ -385,7 +401,7 @@ void cpuinfo_arm_mach_init(void) { uint32_t num_clusters = 1; for (uint32_t i = 0; i < mach_topology.cores; i++) { - cores[i] = (struct cpuinfo_core) { + cores[i] = (struct cpuinfo_core){ .processor_start = i * threads_per_core, .processor_count = threads_per_core, .core_id = i % cores_per_package, @@ -410,27 +426,29 @@ void cpuinfo_arm_mach_init(void) { clusters = calloc(num_clusters, sizeof(struct cpuinfo_cluster)); if (clusters == NULL) { cpuinfo_log_error( - "failed to allocate %zu bytes for descriptions of %"PRIu32" clusters", - num_clusters * sizeof(struct cpuinfo_cluster), num_clusters); + "failed to allocate %zu bytes for descriptions of %" PRIu32 " clusters", + num_clusters * sizeof(struct cpuinfo_cluster), + num_clusters); goto cleanup; } uarchs = calloc(num_clusters, sizeof(struct cpuinfo_uarch_info)); if (uarchs == NULL) { cpuinfo_log_error( - "failed to allocate %zu bytes for descriptions of %"PRIu32" uarchs", - num_clusters * sizeof(enum cpuinfo_uarch), num_clusters); + "failed to allocate %zu bytes for descriptions of %" PRIu32 " uarchs", + num_clusters * sizeof(enum cpuinfo_uarch), + num_clusters); goto cleanup; } uint32_t cluster_idx = UINT32_MAX; for (uint32_t i = 0; i < mach_topology.cores; i++) { if (i == 0 || cores[i].uarch != cores[i - 1].uarch) { cluster_idx++; - uarchs[cluster_idx] = (struct cpuinfo_uarch_info) { + uarchs[cluster_idx] = (struct cpuinfo_uarch_info){ .uarch = cores[i].uarch, .processor_count = 1, .core_count = 1, }; - clusters[cluster_idx] = (struct cpuinfo_cluster) { + clusters[cluster_idx] = (struct cpuinfo_cluster){ .processor_start = i * threads_per_core, .processor_count = 1, .core_start = i, @@ -475,7 +493,7 @@ void cpuinfo_arm_mach_init(void) { /* Assume L1 caches are private to each core */ threads_per_l1 = 1; l1_count = mach_topology.threads / threads_per_l1; - cpuinfo_log_debug("detected %"PRIu32" L1 caches", l1_count); + cpuinfo_log_debug("detected %" PRIu32 " L1 caches", l1_count); } uint32_t threads_per_l2 = 0, l2_count = 0; @@ -483,7 +501,7 @@ void cpuinfo_arm_mach_init(void) { /* Assume L2 cache is shared between all cores */ threads_per_l2 = mach_topology.cores; l2_count = 1; - cpuinfo_log_debug("detected %"PRIu32" L2 caches", l2_count); + cpuinfo_log_debug("detected %" PRIu32 " L2 caches", l2_count); } uint32_t threads_per_l3 = 0, l3_count = 0; @@ -491,24 +509,26 @@ void cpuinfo_arm_mach_init(void) { /* Assume L3 cache is shared between all cores */ threads_per_l3 = mach_topology.cores; l3_count = 1; - cpuinfo_log_debug("detected %"PRIu32" L3 caches", l3_count); + cpuinfo_log_debug("detected %" PRIu32 " L3 caches", l3_count); } if (l1i_cache_size != 0) { l1i = calloc(l1_count, sizeof(struct cpuinfo_cache)); if (l1i == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1I caches", - l1_count * sizeof(struct cpuinfo_cache), l1_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1I caches", + l1_count * sizeof(struct cpuinfo_cache), + l1_count); goto cleanup; } for (uint32_t c = 0; c < l1_count; c++) { - l1i[c] = (struct cpuinfo_cache) { - .size = l1i_cache_size, - .associativity = l1_cache_associativity, - .sets = l1i_cache_size / (l1_cache_associativity * cacheline_size), - .partitions = cache_partitions, - .line_size = cacheline_size, - .flags = cache_flags, + l1i[c] = (struct cpuinfo_cache){ + .size = l1i_cache_size, + .associativity = l1_cache_associativity, + .sets = l1i_cache_size / (l1_cache_associativity * cacheline_size), + .partitions = cache_partitions, + .line_size = cacheline_size, + .flags = cache_flags, .processor_start = c * threads_per_l1, .processor_count = threads_per_l1, }; @@ -521,18 +541,20 @@ void cpuinfo_arm_mach_init(void) { if (l1d_cache_size != 0) { l1d = calloc(l1_count, sizeof(struct cpuinfo_cache)); if (l1d == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1D caches", - l1_count * sizeof(struct cpuinfo_cache), l1_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1D caches", + l1_count * sizeof(struct cpuinfo_cache), + l1_count); goto cleanup; } for (uint32_t c = 0; c < l1_count; c++) { - l1d[c] = (struct cpuinfo_cache) { - .size = l1d_cache_size, - .associativity = l1_cache_associativity, - .sets = l1d_cache_size / (l1_cache_associativity * cacheline_size), - .partitions = cache_partitions, - .line_size = cacheline_size, - .flags = cache_flags, + l1d[c] = (struct cpuinfo_cache){ + .size = l1d_cache_size, + .associativity = l1_cache_associativity, + .sets = l1d_cache_size / (l1_cache_associativity * cacheline_size), + .partitions = cache_partitions, + .line_size = cacheline_size, + .flags = cache_flags, .processor_start = c * threads_per_l1, .processor_count = threads_per_l1, }; @@ -545,18 +567,20 @@ void cpuinfo_arm_mach_init(void) { if (l2_count != 0) { l2 = calloc(l2_count, sizeof(struct cpuinfo_cache)); if (l2 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L2 caches", - l2_count * sizeof(struct cpuinfo_cache), l2_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L2 caches", + l2_count * sizeof(struct cpuinfo_cache), + l2_count); goto cleanup; } for (uint32_t c = 0; c < l2_count; c++) { - l2[c] = (struct cpuinfo_cache) { - .size = l2_cache_size, - .associativity = l2_cache_associativity, - .sets = l2_cache_size / (l2_cache_associativity * cacheline_size), - .partitions = cache_partitions, - .line_size = cacheline_size, - .flags = cache_flags, + l2[c] = (struct cpuinfo_cache){ + .size = l2_cache_size, + .associativity = l2_cache_associativity, + .sets = l2_cache_size / (l2_cache_associativity * cacheline_size), + .partitions = cache_partitions, + .line_size = cacheline_size, + .flags = cache_flags, .processor_start = c * threads_per_l2, .processor_count = threads_per_l2, }; @@ -569,18 +593,20 @@ void cpuinfo_arm_mach_init(void) { if (l3_count != 0) { l3 = calloc(l3_count, sizeof(struct cpuinfo_cache)); if (l3 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L3 caches", - l3_count * sizeof(struct cpuinfo_cache), l3_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L3 caches", + l3_count * sizeof(struct cpuinfo_cache), + l3_count); goto cleanup; } for (uint32_t c = 0; c < l3_count; c++) { - l3[c] = (struct cpuinfo_cache) { - .size = l3_cache_size, - .associativity = l3_cache_associativity, - .sets = l3_cache_size / (l3_cache_associativity * cacheline_size), - .partitions = cache_partitions, - .line_size = cacheline_size, - .flags = cache_flags, + l3[c] = (struct cpuinfo_cache){ + .size = l3_cache_size, + .associativity = l3_cache_associativity, + .sets = l3_cache_size / (l3_cache_associativity * cacheline_size), + .partitions = cache_partitions, + .line_size = cacheline_size, + .flags = cache_flags, .processor_start = c * threads_per_l3, .processor_count = threads_per_l3, }; @@ -598,8 +624,8 @@ void cpuinfo_arm_mach_init(void) { cpuinfo_uarchs = uarchs; cpuinfo_cache[cpuinfo_cache_level_1i] = l1i; cpuinfo_cache[cpuinfo_cache_level_1d] = l1d; - cpuinfo_cache[cpuinfo_cache_level_2] = l2; - cpuinfo_cache[cpuinfo_cache_level_3] = l3; + cpuinfo_cache[cpuinfo_cache_level_2] = l2; + cpuinfo_cache[cpuinfo_cache_level_3] = l3; cpuinfo_processors_count = mach_topology.threads; cpuinfo_cores_count = mach_topology.cores; @@ -608,8 +634,8 @@ void cpuinfo_arm_mach_init(void) { cpuinfo_uarchs_count = num_clusters; cpuinfo_cache_count[cpuinfo_cache_level_1i] = l1_count; cpuinfo_cache_count[cpuinfo_cache_level_1d] = l1_count; - cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; - cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; + cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; + cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; cpuinfo_max_cache_size = cpuinfo_compute_max_cache_size(&processors[0]); __sync_synchronize(); diff --git a/3rdparty/cpuinfo/src/arm/midr.h b/3rdparty/cpuinfo/src/arm/midr.h index 7255cfcf9f..89ebbb5836 100644 --- a/3rdparty/cpuinfo/src/arm/midr.h +++ b/3rdparty/cpuinfo/src/arm/midr.h @@ -1,40 +1,39 @@ #pragma once #include - -#define CPUINFO_ARM_MIDR_IMPLEMENTER_MASK UINT32_C(0xFF000000) -#define CPUINFO_ARM_MIDR_VARIANT_MASK UINT32_C(0x00F00000) +#define CPUINFO_ARM_MIDR_IMPLEMENTER_MASK UINT32_C(0xFF000000) +#define CPUINFO_ARM_MIDR_VARIANT_MASK UINT32_C(0x00F00000) #define CPUINFO_ARM_MIDR_ARCHITECTURE_MASK UINT32_C(0x000F0000) -#define CPUINFO_ARM_MIDR_PART_MASK UINT32_C(0x0000FFF0) -#define CPUINFO_ARM_MIDR_REVISION_MASK UINT32_C(0x0000000F) +#define CPUINFO_ARM_MIDR_PART_MASK UINT32_C(0x0000FFF0) +#define CPUINFO_ARM_MIDR_REVISION_MASK UINT32_C(0x0000000F) -#define CPUINFO_ARM_MIDR_IMPLEMENTER_OFFSET 24 -#define CPUINFO_ARM_MIDR_VARIANT_OFFSET 20 +#define CPUINFO_ARM_MIDR_IMPLEMENTER_OFFSET 24 +#define CPUINFO_ARM_MIDR_VARIANT_OFFSET 20 #define CPUINFO_ARM_MIDR_ARCHITECTURE_OFFSET 16 -#define CPUINFO_ARM_MIDR_PART_OFFSET 4 -#define CPUINFO_ARM_MIDR_REVISION_OFFSET 0 +#define CPUINFO_ARM_MIDR_PART_OFFSET 4 +#define CPUINFO_ARM_MIDR_REVISION_OFFSET 0 -#define CPUINFO_ARM_MIDR_ARM1156 UINT32_C(0x410FB560) -#define CPUINFO_ARM_MIDR_CORTEX_A7 UINT32_C(0x410FC070) -#define CPUINFO_ARM_MIDR_CORTEX_A9 UINT32_C(0x410FC090) -#define CPUINFO_ARM_MIDR_CORTEX_A15 UINT32_C(0x410FC0F0) -#define CPUINFO_ARM_MIDR_CORTEX_A17 UINT32_C(0x410FC0E0) -#define CPUINFO_ARM_MIDR_CORTEX_A35 UINT32_C(0x410FD040) -#define CPUINFO_ARM_MIDR_CORTEX_A53 UINT32_C(0x410FD030) -#define CPUINFO_ARM_MIDR_CORTEX_A55 UINT32_C(0x410FD050) -#define CPUINFO_ARM_MIDR_CORTEX_A57 UINT32_C(0x410FD070) -#define CPUINFO_ARM_MIDR_CORTEX_A72 UINT32_C(0x410FD080) -#define CPUINFO_ARM_MIDR_CORTEX_A73 UINT32_C(0x410FD090) -#define CPUINFO_ARM_MIDR_CORTEX_A75 UINT32_C(0x410FD0A0) -#define CPUINFO_ARM_MIDR_KRYO280_GOLD UINT32_C(0x51AF8001) -#define CPUINFO_ARM_MIDR_KRYO280_SILVER UINT32_C(0x51AF8014) -#define CPUINFO_ARM_MIDR_KRYO385_GOLD UINT32_C(0x518F802D) -#define CPUINFO_ARM_MIDR_KRYO385_SILVER UINT32_C(0x518F803C) +#define CPUINFO_ARM_MIDR_ARM1156 UINT32_C(0x410FB560) +#define CPUINFO_ARM_MIDR_CORTEX_A7 UINT32_C(0x410FC070) +#define CPUINFO_ARM_MIDR_CORTEX_A9 UINT32_C(0x410FC090) +#define CPUINFO_ARM_MIDR_CORTEX_A15 UINT32_C(0x410FC0F0) +#define CPUINFO_ARM_MIDR_CORTEX_A17 UINT32_C(0x410FC0E0) +#define CPUINFO_ARM_MIDR_CORTEX_A35 UINT32_C(0x410FD040) +#define CPUINFO_ARM_MIDR_CORTEX_A53 UINT32_C(0x410FD030) +#define CPUINFO_ARM_MIDR_CORTEX_A55 UINT32_C(0x410FD050) +#define CPUINFO_ARM_MIDR_CORTEX_A57 UINT32_C(0x410FD070) +#define CPUINFO_ARM_MIDR_CORTEX_A72 UINT32_C(0x410FD080) +#define CPUINFO_ARM_MIDR_CORTEX_A73 UINT32_C(0x410FD090) +#define CPUINFO_ARM_MIDR_CORTEX_A75 UINT32_C(0x410FD0A0) +#define CPUINFO_ARM_MIDR_KRYO280_GOLD UINT32_C(0x51AF8001) +#define CPUINFO_ARM_MIDR_KRYO280_SILVER UINT32_C(0x51AF8014) +#define CPUINFO_ARM_MIDR_KRYO385_GOLD UINT32_C(0x518F802D) +#define CPUINFO_ARM_MIDR_KRYO385_SILVER UINT32_C(0x518F803C) #define CPUINFO_ARM_MIDR_KRYO_SILVER_821 UINT32_C(0x510F2010) -#define CPUINFO_ARM_MIDR_KRYO_GOLD UINT32_C(0x510F2050) +#define CPUINFO_ARM_MIDR_KRYO_GOLD UINT32_C(0x510F2050) #define CPUINFO_ARM_MIDR_KRYO_SILVER_820 UINT32_C(0x510F2110) -#define CPUINFO_ARM_MIDR_EXYNOS_M1_M2 UINT32_C(0x530F0010) -#define CPUINFO_ARM_MIDR_DENVER2 UINT32_C(0x4E0F0030) +#define CPUINFO_ARM_MIDR_EXYNOS_M1_M2 UINT32_C(0x530F0010) +#define CPUINFO_ARM_MIDR_DENVER2 UINT32_C(0x4E0F0030) inline static uint32_t midr_set_implementer(uint32_t midr, uint32_t implementer) { return (midr & ~CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) | @@ -176,7 +175,9 @@ inline static uint32_t midr_score_core(uint32_t midr) { case UINT32_C(0x4100D440): /* Cortex-X1 */ case UINT32_C(0x4100D480): /* Cortex-X2 */ case UINT32_C(0x4100D4E0): /* Cortex-X3 */ - /* These cores are in big role w.r.t Cortex-A75/-A76/-A77/-A78/-A710/-A715 */ + /* These cores are in big role w.r.t + * Cortex-A75/-A76/-A77/-A78/-A710/-A715 + */ return 6; case UINT32_C(0x4100D080): /* Cortex-A72 */ case UINT32_C(0x4100D090): /* Cortex-A73 */ @@ -204,7 +205,8 @@ inline static uint32_t midr_score_core(uint32_t midr) { /* These cores are always in big role */ return 5; case UINT32_C(0x4100D070): /* Cortex-A57 */ - /* Cortex-A57 can be in LITTLE role w.r.t. Denver 2, or in big role w.r.t. Cortex-A53 */ + /* Cortex-A57 can be in LITTLE role w.r.t. Denver 2, or + * in big role w.r.t. Cortex-A53 */ return 4; #if CPUINFO_ARCH_ARM64 case UINT32_C(0x4100D060): /* Cortex-A65 */ @@ -212,7 +214,8 @@ inline static uint32_t midr_score_core(uint32_t midr) { case UINT32_C(0x4100D030): /* Cortex-A53 */ case UINT32_C(0x4100D050): /* Cortex-A55 */ case UINT32_C(0x4100D460): /* Cortex-A510 */ - /* Cortex-A53 is usually in LITTLE role, but can be in big role w.r.t. Cortex-A35 */ + /* Cortex-A53 is usually in LITTLE role, but can be in + * big role w.r.t. Cortex-A35 */ return 2; case UINT32_C(0x4100D040): /* Cortex-A35 */ #if CPUINFO_ARCH_ARM @@ -227,10 +230,12 @@ inline static uint32_t midr_score_core(uint32_t midr) { return 1; default: /* - * Unknown cores, or cores which do not have big/LITTLE roles. - * To be future-proof w.r.t. cores not yet recognized in cpuinfo, assume position between - * Cortex-A57/A72/A73/A75 and Cortex-A53/A55. Then at least future cores paired with - * one of these known cores will be properly scored. + * Unknown cores, or cores which do not have big/LITTLE + * roles. To be future-proof w.r.t. cores not yet + * recognized in cpuinfo, assume position between + * Cortex-A57/A72/A73/A75 and Cortex-A53/A55. Then at + * least future cores paired with one of these known + * cores will be properly scored. */ return 3; } diff --git a/3rdparty/cpuinfo/src/arm/tlb.c b/3rdparty/cpuinfo/src/arm/tlb.c index 9beb8327e8..ba39e6bc14 100644 --- a/3rdparty/cpuinfo/src/arm/tlb.c +++ b/3rdparty/cpuinfo/src/arm/tlb.c @@ -5,23 +5,24 @@ switch (uarch) { /* * Cortex-A5 Technical Reference Manual: * 6.3.1. Micro TLB - * The first level of caching for the page table information is a micro TLB of - * 10 entries that is implemented on each of the instruction and data sides. - * 6.3.2. Main TLB - * Misses from the instruction and data micro TLBs are handled by a unified main TLB. - * The main TLB is 128-entry two-way set-associative. + * The first level of caching for the page table information + * is a micro TLB of 10 entries that is implemented on each of + * the instruction and data sides. 6.3.2. Main TLB Misses from + * the instruction and data micro TLBs are handled by a unified + * main TLB. The main TLB is 128-entry two-way set-associative. */ break; case cpuinfo_uarch_cortex_a7: /* * Cortex-A7 MPCore Technical Reference Manual: * 5.3.1. Micro TLB - * The first level of caching for the page table information is a micro TLB of - * 10 entries that is implemented on each of the instruction and data sides. - * 5.3.2. Main TLB - * Misses from the micro TLBs are handled by a unified main TLB. This is a 256-entry 2-way - * set-associative structure. The main TLB supports all the VMSAv7 page sizes of - * 4KB, 64KB, 1MB and 16MB in addition to the LPAE page sizes of 2MB and 1G. + * The first level of caching for the page table information + * is a micro TLB of 10 entries that is implemented on each of + * the instruction and data sides. 5.3.2. Main TLB Misses from + * the micro TLBs are handled by a unified main TLB. This is a + * 256-entry 2-way set-associative structure. The main TLB + * supports all the VMSAv7 page sizes of 4KB, 64KB, 1MB and 16MB + * in addition to the LPAE page sizes of 2MB and 1G. */ break; case cpuinfo_uarch_cortex_a8: @@ -29,7 +30,8 @@ switch (uarch) { * Cortex-A8 Technical Reference Manual: * 6.1. About the MMU * The MMU features include the following: - * - separate, fully-associative, 32-entry data and instruction TLBs + * - separate, fully-associative, 32-entry data and + * instruction TLBs * - TLB entries that support 4KB, 64KB, 1MB, and 16MB pages */ break; @@ -37,51 +39,63 @@ switch (uarch) { /* * ARM Cortex‑A9 Technical Reference Manual: * 6.2.1 Micro TLB - * The first level of caching for the page table information is a micro TLB of 32 entries on the data side, - * and configurable 32 or 64 entries on the instruction side. - * 6.2.2 Main TLB - * The main TLB is implemented as a combination of: + * The first level of caching for the page table information + * is a micro TLB of 32 entries on the data side, and + * configurable 32 or 64 entries on the instruction side. 6.2.2 + * Main TLB The main TLB is implemented as a combination of: * - A fully-associative, lockable array of four elements. - * - A 2-way associative structure of 2x32, 2x64, 2x128 or 2x256 entries. + * - A 2-way associative structure of 2x32, 2x64, 2x128 or + * 2x256 entries. */ break; case cpuinfo_uarch_cortex_a15: /* * ARM Cortex-A15 MPCore Processor Technical Reference Manual: * 5.2.1. L1 instruction TLB - * The L1 instruction TLB is a 32-entry fully-associative structure. This TLB caches entries at the 4KB - * granularity of Virtual Address (VA) to Physical Address (PA) mapping only. If the page tables map the - * memory region to a larger granularity than 4K, it only allocates one mapping for the particular 4K region - * to which the current access corresponds. - * 5.2.2. L1 data TLB - * There are two separate 32-entry fully-associative TLBs that are used for data loads and stores, - * respectively. Similar to the L1 instruction TLB, both of these cache entries at the 4KB granularity of - * VA to PA mappings only. At implementation time, the Cortex-A15 MPCore processor can be configured with - * the -l1tlb_1m option, to have the L1 data TLB cache entries at both the 4KB and 1MB granularity. - * With this configuration, any translation that results in a 1MB or larger page is cached in the L1 data - * TLB as a 1MB entry. Any translation that results in a page smaller than 1MB is cached in the L1 data TLB - * as a 4KB entry. By default, all translations are cached in the L1 data TLB as a 4KB entry. - * 5.2.3. L2 TLB - * Misses from the L1 instruction and data TLBs are handled by a unified L2 TLB. This is a 512-entry 4-way - * set-associative structure. The L2 TLB supports all the VMSAv7 page sizes of 4K, 64K, 1MB and 16MB in - * addition to the LPAE page sizes of 2MB and 1GB. + * The L1 instruction TLB is a 32-entry fully-associative + * structure. This TLB caches entries at the 4KB granularity of + * Virtual Address (VA) to Physical Address (PA) mapping only. + * If the page tables map the memory region to a larger + * granularity than 4K, it only allocates one mapping for the + * particular 4K region to which the current access + * corresponds. 5.2.2. L1 data TLB There are two separate + * 32-entry fully-associative TLBs that are used for data loads + * and stores, respectively. Similar to the L1 instruction TLB, + * both of these cache entries at the 4KB granularity of VA to + * PA mappings only. At implementation time, the Cortex-A15 + * MPCore processor can be configured with the -l1tlb_1m option, + * to have the L1 data TLB cache entries at both the 4KB and 1MB + * granularity. With this configuration, any translation that + * results in a 1MB or larger page is cached in the L1 data TLB + * as a 1MB entry. Any translation that results in a page + * smaller than 1MB is cached in the L1 data TLB as a 4KB entry. + * By default, all translations are cached in the L1 data TLB as + * a 4KB entry. 5.2.3. L2 TLB Misses from the L1 instruction and + * data TLBs are handled by a unified L2 TLB. This is a + * 512-entry 4-way set-associative structure. The L2 TLB + * supports all the VMSAv7 page sizes of 4K, 64K, 1MB and 16MB + * in addition to the LPAE page sizes of 2MB and 1GB. */ break; case cpuinfo_uarch_cortex_a17: /* * ARM Cortex-A17 MPCore Processor Technical Reference Manual: * 5.2.1. Instruction micro TLB - * The instruction micro TLB is implemented as a 32, 48 or 64 entry, fully-associative structure. This TLB - * caches entries at the 4KB and 1MB granularity of Virtual Address (VA) to Physical Address (PA) mapping - * only. If the translation tables map the memory region to a larger granularity than 4KB or 1MB, it only - * allocates one mapping for the particular 4KB region to which the current access corresponds. - * 5.2.2. Data micro TLB - * The data micro TLB is a 32 entry fully-associative TLB that is used for data loads and stores. The cache - * entries have a 4KB and 1MB granularity of VA to PA mappings only. - * 5.2.3. Unified main TLB - * Misses from the instruction and data micro TLBs are handled by a unified main TLB. This is a 1024 entry - * 4-way set-associative structure. The main TLB supports all the VMSAv7 page sizes of 4K, 64K, 1MB and 16MB - * in addition to the LPAE page sizes of 2MB and 1GB. + * The instruction micro TLB is implemented as a 32, 48 or 64 + * entry, fully-associative structure. This TLB caches entries + * at the 4KB and 1MB granularity of Virtual Address (VA) to + * Physical Address (PA) mapping only. If the translation tables + * map the memory region to a larger granularity than 4KB or + * 1MB, it only allocates one mapping for the particular 4KB + * region to which the current access corresponds. 5.2.2. Data + * micro TLB The data micro TLB is a 32 entry fully-associative + * TLB that is used for data loads and stores. The cache entries + * have a 4KB and 1MB granularity of VA to PA mappings + * only. 5.2.3. Unified main TLB Misses from the instruction and + * data micro TLBs are handled by a unified main TLB. This is a + * 1024 entry 4-way set-associative structure. The main TLB + * supports all the VMSAv7 page sizes of 4K, 64K, 1MB and 16MB + * in addition to the LPAE page sizes of 2MB and 1GB. */ break; case cpuinfo_uarch_cortex_a35: @@ -89,45 +103,52 @@ switch (uarch) { * ARM Cortex‑A35 Processor Technical Reference Manual: * A6.2 TLB Organization * Micro TLB - * The first level of caching for the translation table information is a micro TLB of ten entries that - * is implemented on each of the instruction and data sides. - * Main TLB - * A unified main TLB handles misses from the micro TLBs. It has a 512-entry, 2-way, set-associative - * structure and supports all VMSAv8 block sizes, except 1GB. If it fetches a 1GB block, the TLB splits - * it into 512MB blocks and stores the appropriate block for the lookup. + * The first level of caching for the translation table + * information is a micro TLB of ten entries that is implemented + * on each of the instruction and data sides. Main TLB A unified + * main TLB handles misses from the micro TLBs. It has a + * 512-entry, 2-way, set-associative structure and supports all + * VMSAv8 block sizes, except 1GB. If it fetches a 1GB block, + * the TLB splits it into 512MB blocks and stores the + * appropriate block for the lookup. */ break; case cpuinfo_uarch_cortex_a53: /* * ARM Cortex-A53 MPCore Processor Technical Reference Manual: * 5.2.1. Micro TLB - * The first level of caching for the translation table information is a micro TLB of ten entries that is - * implemented on each of the instruction and data sides. - * 5.2.2. Main TLB - * A unified main TLB handles misses from the micro TLBs. This is a 512-entry, 4-way, set-associative - * structure. The main TLB supports all VMSAv8 block sizes, except 1GB. If a 1GB block is fetched, it is - * split into 512MB blocks and the appropriate block for the lookup stored. + * The first level of caching for the translation table + * information is a micro TLB of ten entries that is implemented + * on each of the instruction and data sides. 5.2.2. Main TLB A + * unified main TLB handles misses from the micro TLBs. This is + * a 512-entry, 4-way, set-associative structure. The main TLB + * supports all VMSAv8 block sizes, except 1GB. If a 1GB block + * is fetched, it is split into 512MB blocks and the appropriate + * block for the lookup stored. */ break; case cpuinfo_uarch_cortex_a57: /* * ARM® Cortex-A57 MPCore Processor Technical Reference Manual: * 5.2.1 L1 instruction TLB - * The L1 instruction TLB is a 48-entry fully-associative structure. This TLB caches entries of three - * different page sizes, natively 4KB, 64KB, and 1MB, of VA to PA mappings. If the page tables map the memory - * region to a larger granularity than 1MB, it only allocates one mapping for the particular 1MB region to - * which the current access corresponds. - * 5.2.2 L1 data TLB - * The L1 data TLB is a 32-entry fully-associative TLB that is used for data loads and stores. This TLB - * caches entries of three different page sizes, natively 4KB, 64KB, and 1MB, of VA to PA mappings. - * 5.2.3 L2 TLB - * Misses from the L1 instruction and data TLBs are handled by a unified L2 TLB. This is a 1024-entry 4-way - * set-associative structure. The L2 TLB supports the page sizes of 4K, 64K, 1MB and 16MB. It also supports - * page sizes of 2MB and 1GB for the long descriptor format translation in AArch32 state and in AArch64 state - * when using the 4KB translation granule. In addition, the L2 TLB supports the 512MB page map size defined - * for the AArch64 translations that use a 64KB translation granule. + * The L1 instruction TLB is a 48-entry fully-associative + * structure. This TLB caches entries of three different page + * sizes, natively 4KB, 64KB, and 1MB, of VA to PA mappings. If + * the page tables map the memory region to a larger granularity + * than 1MB, it only allocates one mapping for the particular + * 1MB region to which the current access corresponds. 5.2.2 L1 + * data TLB The L1 data TLB is a 32-entry fully-associative TLB + * that is used for data loads and stores. This TLB caches + * entries of three different page sizes, natively 4KB, 64KB, + * and 1MB, of VA to PA mappings. 5.2.3 L2 TLB Misses from the + * L1 instruction and data TLBs are handled by a unified L2 TLB. + * This is a 1024-entry 4-way set-associative structure. The L2 + * TLB supports the page sizes of 4K, 64K, 1MB and 16MB. It also + * supports page sizes of 2MB and 1GB for the long descriptor + * format translation in AArch32 state and in AArch64 state when + * using the 4KB translation granule. In addition, the L2 TLB + * supports the 512MB page map size defined for the AArch64 + * translations that use a 64KB translation granule. */ break; } - - diff --git a/3rdparty/cpuinfo/src/arm/uarch.c b/3rdparty/cpuinfo/src/arm/uarch.c index f1dd49349a..68531e4d1d 100644 --- a/3rdparty/cpuinfo/src/arm/uarch.c +++ b/3rdparty/cpuinfo/src/arm/uarch.c @@ -4,15 +4,13 @@ #include #include - void cpuinfo_arm_decode_vendor_uarch( uint32_t midr, #if CPUINFO_ARCH_ARM bool has_vfpv4, #endif /* CPUINFO_ARCH_ARM */ enum cpuinfo_vendor vendor[restrict static 1], - enum cpuinfo_uarch uarch[restrict static 1]) -{ + enum cpuinfo_uarch uarch[restrict static 1]) { switch (midr_get_implementer(midr)) { case 'A': *vendor = cpuinfo_vendor_arm; @@ -39,8 +37,9 @@ void cpuinfo_arm_decode_vendor_uarch( case 0xC0D: /* * Rockchip RK3288 only. - * Core information is ambiguous: some sources specify Cortex-A12, others - Cortex-A17. - * Assume it is Cortex-A12. + * Core information is ambiguous: some + * sources specify Cortex-A12, others - + * Cortex-A17. Assume it is Cortex-A12. */ *uarch = cpuinfo_uarch_cortex_a12; break; @@ -58,9 +57,11 @@ void cpuinfo_arm_decode_vendor_uarch( *uarch = cpuinfo_uarch_cortex_a35; break; case 0xD05: - // Note: use Variant, not Revision, field - *uarch = (midr & CPUINFO_ARM_MIDR_VARIANT_MASK) == 0 ? - cpuinfo_uarch_cortex_a55r0 : cpuinfo_uarch_cortex_a55; + // Note: use Variant, not Revision, + // field + *uarch = (midr & CPUINFO_ARM_MIDR_VARIANT_MASK) == 0 + ? cpuinfo_uarch_cortex_a55r0 + : cpuinfo_uarch_cortex_a55; break; case 0xD06: *uarch = cpuinfo_uarch_cortex_a65; @@ -138,7 +139,9 @@ void cpuinfo_arm_decode_vendor_uarch( break; #endif /* CPUINFO_ARCH_ARM */ default: - cpuinfo_log_warning("unknown ARM CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); + cpuinfo_log_warning( + "unknown ARM CPU part 0x%03" PRIx32 " ignored", + midr_get_part(midr)); } } break; @@ -153,13 +156,17 @@ void cpuinfo_arm_decode_vendor_uarch( break; #if CPUINFO_ARCH_ARM64 case 0x516: - /* Broadcom Vulkan was sold to Cavium before it reached the market, so we identify it as Cavium ThunderX2 */ + /* Broadcom Vulkan was sold to Cavium + * before it reached the market, so we + * identify it as Cavium ThunderX2 */ *vendor = cpuinfo_vendor_cavium; *uarch = cpuinfo_uarch_thunderx2; break; #endif /* CPUINFO_ARCH_ARM64 */ default: - cpuinfo_log_warning("unknown Broadcom CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); + cpuinfo_log_warning( + "unknown Broadcom CPU part 0x%03" PRIx32 " ignored", + midr_get_part(midr)); } break; #if CPUINFO_ARCH_ARM64 @@ -176,7 +183,8 @@ void cpuinfo_arm_decode_vendor_uarch( *uarch = cpuinfo_uarch_thunderx2; break; default: - cpuinfo_log_warning("unknown Cavium CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); + cpuinfo_log_warning( + "unknown Cavium CPU part 0x%03" PRIx32 " ignored", midr_get_part(midr)); } break; #endif /* CPUINFO_ARCH_ARM64 */ @@ -188,12 +196,14 @@ void cpuinfo_arm_decode_vendor_uarch( *uarch = cpuinfo_uarch_taishan_v110; break; #endif /* CPUINFO_ARCH_ARM64 */ - case 0xD40: /* Kirin 980 Big/Medium cores -> Cortex-A76 */ + case 0xD40: /* Kirin 980 Big/Medium cores -> + Cortex-A76 */ *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a76; break; default: - cpuinfo_log_warning("unknown Huawei CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); + cpuinfo_log_warning( + "unknown Huawei CPU part 0x%03" PRIx32 " ignored", midr_get_part(midr)); } break; #if CPUINFO_ARCH_ARM @@ -206,7 +216,8 @@ void cpuinfo_arm_decode_vendor_uarch( *uarch = cpuinfo_uarch_xscale; break; default: - cpuinfo_log_warning("unknown Intel CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); + cpuinfo_log_warning( + "unknown Intel CPU part 0x%03" PRIx32 " ignored", midr_get_part(midr)); } break; #endif /* CPUINFO_ARCH_ARM */ @@ -223,7 +234,8 @@ void cpuinfo_arm_decode_vendor_uarch( *uarch = cpuinfo_uarch_carmel; break; default: - cpuinfo_log_warning("unknown Nvidia CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); + cpuinfo_log_warning( + "unknown Nvidia CPU part 0x%03" PRIx32 " ignored", midr_get_part(midr)); } break; case 'P': @@ -233,7 +245,9 @@ void cpuinfo_arm_decode_vendor_uarch( *uarch = cpuinfo_uarch_xgene; break; default: - cpuinfo_log_warning("unknown Applied Micro CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); + cpuinfo_log_warning( + "unknown Applied Micro CPU part 0x%03" PRIx32 " ignored", + midr_get_part(midr)); } break; case 'Q': @@ -241,9 +255,12 @@ void cpuinfo_arm_decode_vendor_uarch( switch (midr_get_part(midr)) { #if CPUINFO_ARCH_ARM case 0x00F: - /* Mostly Scorpions, but some Cortex A5 may report this value as well */ + /* Mostly Scorpions, but some Cortex A5 + * may report this value as well + */ if (has_vfpv4) { - /* Unlike Scorpion, Cortex-A5 comes with VFPv4 */ + /* Unlike Scorpion, Cortex-A5 + * comes with VFPv4 */ *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a5; } else { @@ -266,39 +283,51 @@ void cpuinfo_arm_decode_vendor_uarch( * - r0p1 -> Krait 200 * - r0p2 -> Krait 200 * - r1p0 -> Krait 300 - * - r2p0 -> Krait 400 (Snapdragon 800 MSMxxxx) - * - r2p1 -> Krait 400 (Snapdragon 801 MSMxxxxPRO) + * - r2p0 -> Krait 400 (Snapdragon 800 + * MSMxxxx) + * - r2p1 -> Krait 400 (Snapdragon 801 + * MSMxxxxPRO) * - r3p1 -> Krait 450 */ *uarch = cpuinfo_uarch_krait; break; #endif /* CPUINFO_ARCH_ARM */ - case 0x201: /* Qualcomm Snapdragon 821: Low-power Kryo "Silver" */ - case 0x205: /* Qualcomm Snapdragon 820 & 821: High-performance Kryo "Gold" */ - case 0x211: /* Qualcomm Snapdragon 820: Low-power Kryo "Silver" */ + case 0x201: /* Qualcomm Snapdragon 821: + Low-power Kryo "Silver" */ + case 0x205: /* Qualcomm Snapdragon 820 & 821: + High-performance Kryo "Gold" */ + case 0x211: /* Qualcomm Snapdragon 820: + Low-power Kryo "Silver" */ *uarch = cpuinfo_uarch_kryo; break; - case 0x800: /* High-performance Kryo 260 (r10p2) / Kryo 280 (r10p1) "Gold" -> Cortex-A73 */ + case 0x800: /* High-performance Kryo 260 (r10p2) + / Kryo 280 (r10p1) "Gold" -> + Cortex-A73 */ *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a73; break; - case 0x801: /* Low-power Kryo 260 / 280 "Silver" -> Cortex-A53 */ + case 0x801: /* Low-power Kryo 260 / 280 "Silver" + -> Cortex-A53 */ *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a53; break; - case 0x802: /* High-performance Kryo 385 "Gold" -> Cortex-A75 */ + case 0x802: /* High-performance Kryo 385 "Gold" + -> Cortex-A75 */ *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a75; break; - case 0x803: /* Low-power Kryo 385 "Silver" -> Cortex-A55r0 */ + case 0x803: /* Low-power Kryo 385 "Silver" -> + Cortex-A55r0 */ *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a55r0; break; - case 0x804: /* High-performance Kryo 485 "Gold" / "Gold Prime" -> Cortex-A76 */ + case 0x804: /* High-performance Kryo 485 "Gold" + / "Gold Prime" -> Cortex-A76 */ *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a76; break; - case 0x805: /* Low-performance Kryo 485 "Silver" -> Cortex-A55 */ + case 0x805: /* Low-performance Kryo 485 "Silver" + -> Cortex-A55 */ *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a55; break; @@ -311,7 +340,9 @@ void cpuinfo_arm_decode_vendor_uarch( break; #endif /* CPUINFO_ARCH_ARM64 */ default: - cpuinfo_log_warning("unknown Qualcomm CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); + cpuinfo_log_warning( + "unknown Qualcomm CPU part 0x%03" PRIx32 " ignored", + midr_get_part(midr)); } break; case 'S': @@ -319,7 +350,8 @@ void cpuinfo_arm_decode_vendor_uarch( switch (midr & (CPUINFO_ARM_MIDR_VARIANT_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { case 0x00100010: /* - * Exynos 8890 MIDR = 0x531F0011, assume Exynos M1 has: + * Exynos 8890 MIDR = 0x531F0011, assume + * Exynos M1 has: * - CPU variant 0x1 * - CPU part 0x001 */ @@ -327,7 +359,8 @@ void cpuinfo_arm_decode_vendor_uarch( break; case 0x00400010: /* - * Exynos 8895 MIDR = 0x534F0010, assume Exynos M2 has: + * Exynos 8895 MIDR = 0x534F0010, assume + * Exynos M2 has: * - CPU variant 0x4 * - CPU part 0x001 */ @@ -335,7 +368,8 @@ void cpuinfo_arm_decode_vendor_uarch( break; case 0x00100020: /* - * Exynos 9810 MIDR = 0x531F0020, assume Exynos M3 has: + * Exynos 9810 MIDR = 0x531F0020, assume + * Exynos M3 has: * - CPU variant 0x1 * - CPU part 0x002 */ @@ -343,7 +377,8 @@ void cpuinfo_arm_decode_vendor_uarch( break; case 0x00100030: /* - * Exynos 9820 MIDR = 0x531F0030, assume Exynos M4 has: + * Exynos 9820 MIDR = 0x531F0030, assume + * Exynos M4 has: * - CPU variant 0x1 * - CPU part 0x003 */ @@ -351,15 +386,19 @@ void cpuinfo_arm_decode_vendor_uarch( break; case 0x00100040: /* - * Exynos 9820 MIDR = 0x531F0040, assume Exynos M5 has: + * Exynos 9820 MIDR = 0x531F0040, assume + * Exynos M5 has: * - CPU variant 0x1 * - CPU part 0x004 */ *uarch = cpuinfo_uarch_exynos_m5; break; default: - cpuinfo_log_warning("unknown Samsung CPU variant 0x%01"PRIx32" part 0x%03"PRIx32" ignored", - midr_get_variant(midr), midr_get_part(midr)); + cpuinfo_log_warning( + "unknown Samsung CPU variant 0x%01" PRIx32 " part 0x%03" PRIx32 + " ignored", + midr_get_variant(midr), + midr_get_part(midr)); } break; #if CPUINFO_ARCH_ARM @@ -371,12 +410,17 @@ void cpuinfo_arm_decode_vendor_uarch( *uarch = cpuinfo_uarch_pj4; break; default: - cpuinfo_log_warning("unknown Marvell CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); + cpuinfo_log_warning( + "unknown Marvell CPU part 0x%03" PRIx32 " ignored", + midr_get_part(midr)); } break; #endif /* CPUINFO_ARCH_ARM */ default: - cpuinfo_log_warning("unknown CPU implementer '%c' (0x%02"PRIx32") with CPU part 0x%03"PRIx32" ignored", - (char) midr_get_implementer(midr), midr_get_implementer(midr), midr_get_part(midr)); + cpuinfo_log_warning( + "unknown CPU implementer '%c' (0x%02" PRIx32 ") with CPU part 0x%03" PRIx32 " ignored", + (char)midr_get_implementer(midr), + midr_get_implementer(midr), + midr_get_part(midr)); } } diff --git a/3rdparty/cpuinfo/src/arm/windows/init-by-logical-sys-info.c b/3rdparty/cpuinfo/src/arm/windows/init-by-logical-sys-info.c index b7b3990c15..a644b1d019 100644 --- a/3rdparty/cpuinfo/src/arm/windows/init-by-logical-sys-info.c +++ b/3rdparty/cpuinfo/src/arm/windows/init-by-logical-sys-info.c @@ -1,9 +1,9 @@ -#include +#include +#include #include +#include #include #include -#include -#include #include #include @@ -12,7 +12,7 @@ #include "windows-arm-init.h" -#define MAX_NR_OF_CACHES (cpuinfo_cache_level_max - 1) +#define MAX_NR_OF_CACHES (cpuinfo_cache_level_max - 1) /* Call chain: * cpu_info_init_by_logical_sys_info @@ -27,30 +27,28 @@ * store_cache_info_per_processor */ -static uint32_t count_logical_processors( - const uint32_t max_group_count, - uint32_t* global_proc_index_per_group); +static uint32_t count_logical_processors(const uint32_t max_group_count, uint32_t* global_proc_index_per_group); static uint32_t read_packages_for_processors( struct cpuinfo_processor* processors, const uint32_t number_of_processors, const uint32_t* global_proc_index_per_group, - const struct woa_chip_info *chip_info); + const struct woa_chip_info* chip_info); static uint32_t read_cores_for_processors( struct cpuinfo_processor* processors, const uint32_t number_of_processors, const uint32_t* global_proc_index_per_group, struct cpuinfo_core* cores, - const struct woa_chip_info *chip_info); + const struct woa_chip_info* chip_info); static uint32_t read_caches_for_processors( - struct cpuinfo_processor *processors, + struct cpuinfo_processor* processors, const uint32_t number_of_processors, - struct cpuinfo_cache *caches, + struct cpuinfo_cache* caches, uint32_t* numbers_of_caches, const uint32_t* global_proc_index_per_group, - const struct woa_chip_info *chip_info); + const struct woa_chip_info* chip_info); static uint32_t read_all_logical_processor_info_of_relation( LOGICAL_PROCESSOR_RELATIONSHIP info_type, @@ -60,7 +58,7 @@ static uint32_t read_all_logical_processor_info_of_relation( uint32_t* numbers_of_caches, struct cpuinfo_core* cores, const uint32_t* global_proc_index_per_group, - const struct woa_chip_info *chip_info); + const struct woa_chip_info* chip_info); static bool parse_relation_processor_info( struct cpuinfo_processor* processors, @@ -69,7 +67,7 @@ static bool parse_relation_processor_info( PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX info, const uint32_t info_id, struct cpuinfo_core* cores, - const struct woa_chip_info *chip_info); + const struct woa_chip_info* chip_info); static bool parse_relation_cache_info( struct cpuinfo_processor* processors, @@ -91,7 +89,7 @@ static void store_core_info_per_processor( const uint32_t core_id, PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX core_info, struct cpuinfo_core* cores, - const struct woa_chip_info *chip_info); + const struct woa_chip_info* chip_info); static void store_cache_info_per_processor( struct cpuinfo_processor* processors, @@ -112,11 +110,7 @@ static bool connect_packages_cores_clusters_by_processors( static inline uint32_t low_index_from_kaffinity(KAFFINITY kaffinity); - -bool cpu_info_init_by_logical_sys_info( - const struct woa_chip_info *chip_info, - const enum cpuinfo_vendor vendor) -{ +bool cpu_info_init_by_logical_sys_info(const struct woa_chip_info* chip_info, const enum cpuinfo_vendor vendor) { struct cpuinfo_processor* processors = NULL; struct cpuinfo_package* packages = NULL; struct cpuinfo_cluster* clusters = NULL; @@ -128,147 +122,156 @@ bool cpu_info_init_by_logical_sys_info( uint32_t nr_of_cores = 0; uint32_t nr_of_all_caches = 0; uint32_t numbers_of_caches[MAX_NR_OF_CACHES] = {0}; - + uint32_t nr_of_uarchs = 0; bool result = false; - + HANDLE heap = GetProcessHeap(); /* 1. Count available logical processor groups and processors */ - const uint32_t max_group_count = (uint32_t) GetMaximumProcessorGroupCount(); - cpuinfo_log_debug("detected %"PRIu32" processor group(s)", max_group_count); - /* We need to store the absolute processor ID offsets for every groups, because + const uint32_t max_group_count = (uint32_t)GetMaximumProcessorGroupCount(); + cpuinfo_log_debug("detected %" PRIu32 " processor group(s)", max_group_count); + /* We need to store the absolute processor ID offsets for every groups, + * because * 1. We can't assume every processor groups include the same number of * logical processors. - * 2. Every processor groups know its group number and processor IDs within - * the group, but not the global processor IDs. + * 2. Every processor groups know its group number and processor IDs + * within the group, but not the global processor IDs. * 3. We need to list every logical processors by global IDs. - */ - uint32_t* global_proc_index_per_group = - (uint32_t*) HeapAlloc(heap, 0, max_group_count * sizeof(uint32_t)); + */ + uint32_t* global_proc_index_per_group = (uint32_t*)HeapAlloc(heap, 0, max_group_count * sizeof(uint32_t)); if (global_proc_index_per_group == NULL) { cpuinfo_log_error( - "failed to allocate %zu bytes for descriptions of %"PRIu32" processor groups", - max_group_count * sizeof(struct cpuinfo_processor), max_group_count); - goto clean_up; - } - - uint32_t nr_of_processors = - count_logical_processors(max_group_count, global_proc_index_per_group); - processors = HeapAlloc(heap, HEAP_ZERO_MEMORY, nr_of_processors * sizeof(struct cpuinfo_processor)); - if (processors == NULL) { - cpuinfo_log_error( - "failed to allocate %zu bytes for descriptions of %"PRIu32" logical processors", - nr_of_processors * sizeof(struct cpuinfo_processor), nr_of_processors); + "failed to allocate %zu bytes for descriptions of %" PRIu32 " processor groups", + max_group_count * sizeof(struct cpuinfo_processor), + max_group_count); goto clean_up; } - /* 2. Read topology information via MSDN API: packages, cores and caches*/ - nr_of_packages = read_packages_for_processors( - processors, nr_of_processors, - global_proc_index_per_group, - chip_info); + uint32_t nr_of_processors = count_logical_processors(max_group_count, global_proc_index_per_group); + processors = HeapAlloc(heap, HEAP_ZERO_MEMORY, nr_of_processors * sizeof(struct cpuinfo_processor)); + if (processors == NULL) { + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " logical processors", + nr_of_processors * sizeof(struct cpuinfo_processor), + nr_of_processors); + goto clean_up; + } + + /* 2. Read topology information via MSDN API: packages, cores and + * caches*/ + nr_of_packages = + read_packages_for_processors(processors, nr_of_processors, global_proc_index_per_group, chip_info); if (!nr_of_packages) { cpuinfo_log_error("error in reading package information"); goto clean_up; } - cpuinfo_log_debug("detected %"PRIu32" processor package(s)", nr_of_packages); + cpuinfo_log_debug("detected %" PRIu32 " processor package(s)", nr_of_packages); /* We need the EfficiencyClass to parse uarch from the core information, * but we need to iterate first to count cores and allocate memory then - * we will iterate again to read and store data to cpuinfo_core structures. + * we will iterate again to read and store data to cpuinfo_core + * structures. */ - nr_of_cores = read_cores_for_processors( - processors, nr_of_processors, - global_proc_index_per_group, NULL, - chip_info); + nr_of_cores = + read_cores_for_processors(processors, nr_of_processors, global_proc_index_per_group, NULL, chip_info); if (!nr_of_cores) { cpuinfo_log_error("error in reading core information"); goto clean_up; } - cpuinfo_log_debug("detected %"PRIu32" processor core(s)", nr_of_cores); + cpuinfo_log_debug("detected %" PRIu32 " processor core(s)", nr_of_cores); - /* There is no API to read number of caches, so we need to iterate twice on caches: + /* There is no API to read number of caches, so we need to iterate twice + on caches: 1. Count all type of caches -> allocate memory 2. Read out cache data and store to allocated memory */ nr_of_all_caches = read_caches_for_processors( - processors, nr_of_processors, - caches, numbers_of_caches, - global_proc_index_per_group, chip_info); + processors, nr_of_processors, caches, numbers_of_caches, global_proc_index_per_group, chip_info); if (!nr_of_all_caches) { cpuinfo_log_error("error in reading cache information"); goto clean_up; } - cpuinfo_log_debug("detected %"PRIu32" processor cache(s)", nr_of_all_caches); + cpuinfo_log_debug("detected %" PRIu32 " processor cache(s)", nr_of_all_caches); /* 3. Allocate memory for package, cluster, core and cache structures */ packages = HeapAlloc(heap, HEAP_ZERO_MEMORY, nr_of_packages * sizeof(struct cpuinfo_package)); if (packages == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" physical packages", - nr_of_packages * sizeof(struct cpuinfo_package), nr_of_packages); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " physical packages", + nr_of_packages * sizeof(struct cpuinfo_package), + nr_of_packages); goto clean_up; } - /* We don't have cluster information so we explicitly set clusters to equal to cores. */ + /* We don't have cluster information so we explicitly set clusters to + * equal to cores. */ clusters = HeapAlloc(heap, HEAP_ZERO_MEMORY, nr_of_cores * sizeof(struct cpuinfo_cluster)); if (clusters == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" core clusters", - nr_of_cores * sizeof(struct cpuinfo_cluster), nr_of_cores); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " core clusters", + nr_of_cores * sizeof(struct cpuinfo_cluster), + nr_of_cores); goto clean_up; } cores = HeapAlloc(heap, HEAP_ZERO_MEMORY, nr_of_cores * sizeof(struct cpuinfo_core)); if (cores == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" cores", - nr_of_cores * sizeof(struct cpuinfo_core), nr_of_cores); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " cores", + nr_of_cores * sizeof(struct cpuinfo_core), + nr_of_cores); goto clean_up; } - /* We allocate one contiguous cache array for all caches, then use offsets per cache type. */ + /* We allocate one contiguous cache array for all caches, then use + * offsets per cache type. */ caches = HeapAlloc(heap, HEAP_ZERO_MEMORY, nr_of_all_caches * sizeof(struct cpuinfo_cache)); if (caches == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" caches", - nr_of_all_caches * sizeof(struct cpuinfo_cache), nr_of_all_caches); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " caches", + nr_of_all_caches * sizeof(struct cpuinfo_cache), + nr_of_all_caches); goto clean_up; } - /* 4.Read missing topology information that can't be saved without counted - * allocate structures in the first round. + /* 4.Read missing topology information that can't be saved without + * counted allocate structures in the first round. */ nr_of_all_caches = read_caches_for_processors( - processors, nr_of_processors, - caches, numbers_of_caches, global_proc_index_per_group, chip_info); + processors, nr_of_processors, caches, numbers_of_caches, global_proc_index_per_group, chip_info); if (!nr_of_all_caches) { cpuinfo_log_error("error in reading cache information"); goto clean_up; } - nr_of_cores = read_cores_for_processors( - processors, nr_of_processors, - global_proc_index_per_group, cores, - chip_info); + nr_of_cores = + read_cores_for_processors(processors, nr_of_processors, global_proc_index_per_group, cores, chip_info); if (!nr_of_cores) { cpuinfo_log_error("error in reading core information"); goto clean_up; } - /* 5. Now that we read out everything from the system we can, fill the package, cluster - * and core structures respectively. + /* 5. Now that we read out everything from the system we can, fill the + * package, cluster and core structures respectively. */ result = connect_packages_cores_clusters_by_processors( - processors, nr_of_processors, - packages, nr_of_packages, - clusters, - cores, nr_of_cores, - chip_info, - vendor); - if(!result) { + processors, + nr_of_processors, + packages, + nr_of_packages, + clusters, + cores, + nr_of_cores, + chip_info, + vendor); + if (!result) { cpuinfo_log_error("error in connecting information"); goto clean_up; } - /* 6. Count and store uarchs of cores, assuming same uarchs are neighbors */ + /* 6. Count and store uarchs of cores, assuming same uarchs are + * neighbors */ enum cpuinfo_uarch prev_uarch = cpuinfo_uarch_unknown; for (uint32_t i = 0; i < nr_of_cores; i++) { if (prev_uarch != cores[i].uarch) { @@ -278,8 +281,10 @@ bool cpu_info_init_by_logical_sys_info( } uarchs = HeapAlloc(heap, HEAP_ZERO_MEMORY, nr_of_uarchs * sizeof(struct cpuinfo_uarch_info)); if (uarchs == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" uarchs", - nr_of_uarchs * sizeof(struct cpuinfo_uarch_info), nr_of_uarchs); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " uarchs", + nr_of_uarchs * sizeof(struct cpuinfo_uarch_info), + nr_of_uarchs); goto clean_up; } prev_uarch = cpuinfo_uarch_unknown; @@ -318,10 +323,14 @@ bool cpu_info_init_by_logical_sys_info( cpuinfo_cache_count[i] = numbers_of_caches[i]; } cpuinfo_cache[cpuinfo_cache_level_1i] = caches; - cpuinfo_cache[cpuinfo_cache_level_1d] = cpuinfo_cache[cpuinfo_cache_level_1i] + cpuinfo_cache_count[cpuinfo_cache_level_1i]; - cpuinfo_cache[cpuinfo_cache_level_2] = cpuinfo_cache[cpuinfo_cache_level_1d] + cpuinfo_cache_count[cpuinfo_cache_level_1d]; - cpuinfo_cache[cpuinfo_cache_level_3] = cpuinfo_cache[cpuinfo_cache_level_2] + cpuinfo_cache_count[cpuinfo_cache_level_2]; - cpuinfo_cache[cpuinfo_cache_level_4] = cpuinfo_cache[cpuinfo_cache_level_3] + cpuinfo_cache_count[cpuinfo_cache_level_3]; + cpuinfo_cache[cpuinfo_cache_level_1d] = + cpuinfo_cache[cpuinfo_cache_level_1i] + cpuinfo_cache_count[cpuinfo_cache_level_1i]; + cpuinfo_cache[cpuinfo_cache_level_2] = + cpuinfo_cache[cpuinfo_cache_level_1d] + cpuinfo_cache_count[cpuinfo_cache_level_1d]; + cpuinfo_cache[cpuinfo_cache_level_3] = + cpuinfo_cache[cpuinfo_cache_level_2] + cpuinfo_cache_count[cpuinfo_cache_level_2]; + cpuinfo_cache[cpuinfo_cache_level_4] = + cpuinfo_cache[cpuinfo_cache_level_3] + cpuinfo_cache_count[cpuinfo_cache_level_3]; cpuinfo_max_cache_size = cpuinfo_compute_max_cache_size(&processors[0]); result = true; @@ -363,16 +372,13 @@ clean_up: return result; } -static uint32_t count_logical_processors( - const uint32_t max_group_count, - uint32_t* global_proc_index_per_group) -{ +static uint32_t count_logical_processors(const uint32_t max_group_count, uint32_t* global_proc_index_per_group) { uint32_t nr_of_processors = 0; for (uint32_t i = 0; i < max_group_count; i++) { - uint32_t nr_of_processors_per_group = GetMaximumProcessorCount((WORD) i); - cpuinfo_log_debug("detected %"PRIu32" processor(s) in group %"PRIu32"", - nr_of_processors_per_group, i); + uint32_t nr_of_processors_per_group = GetMaximumProcessorCount((WORD)i); + cpuinfo_log_debug( + "detected %" PRIu32 " processor(s) in group %" PRIu32 "", nr_of_processors_per_group, i); global_proc_index_per_group[i] = nr_of_processors; nr_of_processors += nr_of_processors_per_group; } @@ -383,8 +389,7 @@ static uint32_t read_packages_for_processors( struct cpuinfo_processor* processors, const uint32_t number_of_processors, const uint32_t* global_proc_index_per_group, - const struct woa_chip_info *chip_info) -{ + const struct woa_chip_info* chip_info) { return read_all_logical_processor_info_of_relation( RelationProcessorPackage, processors, @@ -401,8 +406,7 @@ uint32_t read_cores_for_processors( const uint32_t number_of_processors, const uint32_t* global_proc_index_per_group, struct cpuinfo_core* cores, - const struct woa_chip_info *chip_info) -{ + const struct woa_chip_info* chip_info) { return read_all_logical_processor_info_of_relation( RelationProcessorCore, processors, @@ -420,8 +424,7 @@ static uint32_t read_caches_for_processors( struct cpuinfo_cache* caches, uint32_t* numbers_of_caches, const uint32_t* global_proc_index_per_group, - const struct woa_chip_info *chip_info) -{ + const struct woa_chip_info* chip_info) { /* Reset processor start indexes */ if (caches) { uint32_t cache_offset = 0; @@ -452,8 +455,7 @@ static uint32_t read_all_logical_processor_info_of_relation( uint32_t* numbers_of_caches, struct cpuinfo_core* cores, const uint32_t* global_proc_index_per_group, - const struct woa_chip_info* chip_info) -{ + const struct woa_chip_info* chip_info) { PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX infos = NULL; uint32_t nr_of_structs = 0; DWORD info_size = 0; @@ -465,76 +467,74 @@ static uint32_t read_all_logical_processor_info_of_relation( const DWORD last_error = GetLastError(); if (last_error != ERROR_INSUFFICIENT_BUFFER) { cpuinfo_log_error( - "failed to query size of processor %"PRIu32" information information: error %"PRIu32"", - (uint32_t)info_type, (uint32_t) last_error); + "failed to query size of processor %" PRIu32 " information information: error %" PRIu32 + "", + (uint32_t)info_type, + (uint32_t)last_error); goto clean_up; } } /* 2. Allocate memory for the information structure */ infos = HeapAlloc(heap, 0, info_size); if (infos == NULL) { - cpuinfo_log_error("failed to allocate %"PRIu32" bytes for logical processor information", - (uint32_t) info_size); + cpuinfo_log_error( + "failed to allocate %" PRIu32 " bytes for logical processor information", (uint32_t)info_size); goto clean_up; } /* 3. Read the information structure */ if (GetLogicalProcessorInformationEx(info_type, infos, &info_size) == FALSE) { - cpuinfo_log_error("failed to query processor %"PRIu32" information: error %"PRIu32"", - (uint32_t)info_type, (uint32_t) GetLastError()); + cpuinfo_log_error( + "failed to query processor %" PRIu32 " information: error %" PRIu32 "", + (uint32_t)info_type, + (uint32_t)GetLastError()); goto clean_up; } /* 4. Parse the structure and store relevant data */ PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX info_end = - (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX) ((uintptr_t) infos + info_size); - for (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX info = infos; - info < info_end; - info = (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX) ((uintptr_t) info + info->Size)) - { + (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX)((uintptr_t)infos + info_size); + for (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX info = infos; info < info_end; + info = (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX)((uintptr_t)info + info->Size)) { if (info->Relationship != info_type) { cpuinfo_log_warning( - "unexpected processor info type (%"PRIu32") for processor information", - (uint32_t) info->Relationship); + "unexpected processor info type (%" PRIu32 ") for processor information", + (uint32_t)info->Relationship); continue; } const uint32_t info_id = nr_of_structs++; - switch(info_type) { + switch (info_type) { case RelationProcessorPackage: result = parse_relation_processor_info( - processors, - number_of_processors, - global_proc_index_per_group, - info, - info_id, - cores, - chip_info); - break; + processors, + number_of_processors, + global_proc_index_per_group, + info, + info_id, + cores, + chip_info); + break; case RelationProcessorCore: result = parse_relation_processor_info( - processors, - number_of_processors, - global_proc_index_per_group, - info, - info_id, - cores, - chip_info); - break; + processors, + number_of_processors, + global_proc_index_per_group, + info, + info_id, + cores, + chip_info); + break; case RelationCache: result = parse_relation_cache_info( - processors, - caches, - numbers_of_caches, - global_proc_index_per_group, - info); - break; + processors, caches, numbers_of_caches, global_proc_index_per_group, info); + break; default: cpuinfo_log_error( - "unexpected processor info type (%"PRIu32") for processor information", - (uint32_t) info->Relationship); + "unexpected processor info type (%" PRIu32 ") for processor information", + (uint32_t)info->Relationship); result = false; - break; + break; } if (!result) { nr_of_structs = 0; @@ -555,43 +555,45 @@ static bool parse_relation_processor_info( PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX info, const uint32_t info_id, struct cpuinfo_core* cores, - const struct woa_chip_info *chip_info) -{ + const struct woa_chip_info* chip_info) { for (uint32_t i = 0; i < info->Processor.GroupCount; i++) { const uint32_t group_id = info->Processor.GroupMask[i].Group; - /* Bitmask representing processors in this group belonging to this package */ + /* Bitmask representing processors in this group belonging to + * this package + */ KAFFINITY group_processors_mask = info->Processor.GroupMask[i].Mask; while (group_processors_mask != 0) { - const uint32_t processor_id_in_group = - low_index_from_kaffinity(group_processors_mask); + const uint32_t processor_id_in_group = low_index_from_kaffinity(group_processors_mask); const uint32_t processor_global_index = global_proc_index_per_group[group_id] + processor_id_in_group; - if(processor_global_index >= nr_of_processors) { - cpuinfo_log_error("unexpected processor index %"PRIu32"", - processor_global_index); + if (processor_global_index >= nr_of_processors) { + cpuinfo_log_error("unexpected processor index %" PRIu32 "", processor_global_index); return false; } - switch(info->Relationship) { + switch (info->Relationship) { case RelationProcessorPackage: store_package_info_per_processor( - processors, processor_global_index, info_id, - group_id, processor_id_in_group); - break; + processors, + processor_global_index, + info_id, + group_id, + processor_id_in_group); + break; case RelationProcessorCore: store_core_info_per_processor( - processors, processor_global_index, - info_id, info, - cores, chip_info); - break; + processors, processor_global_index, info_id, info, cores, chip_info); + break; default: cpuinfo_log_error( - "unexpected processor info type (%"PRIu32") for processor information", - (uint32_t) info->Relationship); - break; + "unexpected processor info type (%" PRIu32 + ") for processor information", + (uint32_t)info->Relationship); + break; } - /* Clear the bits in affinity mask, lower the least set bit. */ + /* Clear the bits in affinity mask, lower the least set + * bit. */ group_processors_mask &= (group_processors_mask - 1); } } @@ -603,8 +605,7 @@ static bool parse_relation_cache_info( struct cpuinfo_cache* caches, uint32_t* numbers_of_caches, const uint32_t* global_proc_index_per_group, - PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX info) -{ + PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX info) { static uint32_t l1i_counter = 0; static uint32_t l1d_counter = 0; static uint32_t l2_counter = 0; @@ -612,45 +613,52 @@ static bool parse_relation_cache_info( /* Count cache types for allocation at first. */ if (caches == NULL) { - switch(info->Cache.Level) { + switch (info->Cache.Level) { case 1: switch (info->Cache.Type) { case CacheInstruction: numbers_of_caches[cpuinfo_cache_level_1i]++; - break; + break; case CacheData: numbers_of_caches[cpuinfo_cache_level_1d]++; - break; + break; case CacheUnified: - break; + break; case CacheTrace: - break; + break; default: - break; + break; } - break; + break; case 2: numbers_of_caches[cpuinfo_cache_level_2]++; - break; + break; case 3: numbers_of_caches[cpuinfo_cache_level_3]++; - break; + break; } return true; } struct cpuinfo_cache* l1i_base = caches; struct cpuinfo_cache* l1d_base = l1i_base + numbers_of_caches[cpuinfo_cache_level_1i]; - struct cpuinfo_cache* l2_base = l1d_base + numbers_of_caches[cpuinfo_cache_level_1d]; - struct cpuinfo_cache* l3_base = l2_base + numbers_of_caches[cpuinfo_cache_level_2]; + struct cpuinfo_cache* l2_base = l1d_base + numbers_of_caches[cpuinfo_cache_level_1d]; + struct cpuinfo_cache* l3_base = l2_base + numbers_of_caches[cpuinfo_cache_level_2]; cpuinfo_log_debug( - "info->Cache.GroupCount:%"PRIu32", info->Cache.GroupMask:%"PRIu32"," - "info->Cache.Level:%"PRIu32", info->Cache.Associativity:%"PRIu32"," - "info->Cache.LineSize:%"PRIu32"," - "info->Cache.CacheSize:%"PRIu32", info->Cache.Type:%"PRIu32"", - info->Cache.GroupCount, (unsigned int)info->Cache.GroupMask.Mask, - info->Cache.Level, info->Cache.Associativity, info->Cache.LineSize, - info->Cache.CacheSize, info->Cache.Type); + "info->Cache.GroupCount:%" PRIu32 ", info->Cache.GroupMask:%" PRIu32 + "," + "info->Cache.Level:%" PRIu32 ", info->Cache.Associativity:%" PRIu32 + "," + "info->Cache.LineSize:%" PRIu32 + "," + "info->Cache.CacheSize:%" PRIu32 ", info->Cache.Type:%" PRIu32 "", + info->Cache.GroupCount, + (unsigned int)info->Cache.GroupMask.Mask, + info->Cache.Level, + info->Cache.Associativity, + info->Cache.LineSize, + info->Cache.CacheSize, + info->Cache.Type); struct cpuinfo_cache* current_cache = NULL; switch (info->Cache.Level) { @@ -659,27 +667,27 @@ static bool parse_relation_cache_info( case CacheInstruction: current_cache = l1i_base + l1i_counter; l1i_counter++; - break; + break; case CacheData: current_cache = l1d_base + l1d_counter; l1d_counter++; - break; + break; case CacheUnified: - break; + break; case CacheTrace: - break; + break; default: - break; + break; } - break; + break; case 2: current_cache = l2_base + l2_counter; l2_counter++; - break; + break; case 3: current_cache = l3_base + l3_counter; l3_counter++; - break; + break; } current_cache->size = info->Cache.CacheSize; current_cache->line_size = info->Cache.LineSize; @@ -688,28 +696,28 @@ static bool parse_relation_cache_info( * so we set partitions to 1 and calculate the expected sets. */ current_cache->partitions = 1; - current_cache->sets = - current_cache->size / current_cache->line_size / current_cache->associativity; + current_cache->sets = current_cache->size / current_cache->line_size / current_cache->associativity; if (info->Cache.Type == CacheUnified) { current_cache->flags = CPUINFO_CACHE_UNIFIED; } for (uint32_t i = 0; i < info->Cache.GroupCount; i++) { - /* Zero GroupCount is valid, GroupMask still can store bits set. */ + /* Zero GroupCount is valid, GroupMask still can store bits set. + */ const uint32_t group_id = info->Cache.GroupMasks[i].Group; - /* Bitmask representing processors in this group belonging to this package */ + /* Bitmask representing processors in this group belonging to + * this package + */ KAFFINITY group_processors_mask = info->Cache.GroupMasks[i].Mask; while (group_processors_mask != 0) { - const uint32_t processor_id_in_group = - low_index_from_kaffinity(group_processors_mask); + const uint32_t processor_id_in_group = low_index_from_kaffinity(group_processors_mask); const uint32_t processor_global_index = global_proc_index_per_group[group_id] + processor_id_in_group; - store_cache_info_per_processor( - processors, processor_global_index, - info, current_cache); + store_cache_info_per_processor(processors, processor_global_index, info, current_cache); - /* Clear the bits in affinity mask, lower the least set bit. */ + /* Clear the bits in affinity mask, lower the least set + * bit. */ group_processors_mask &= (group_processors_mask - 1); } } @@ -721,18 +729,15 @@ static void store_package_info_per_processor( const uint32_t processor_global_index, const uint32_t package_id, const uint32_t group_id, - const uint32_t processor_id_in_group) -{ - processors[processor_global_index].windows_group_id = - (uint16_t) group_id; - processors[processor_global_index].windows_processor_id = - (uint16_t) processor_id_in_group; + const uint32_t processor_id_in_group) { + processors[processor_global_index].windows_group_id = (uint16_t)group_id; + processors[processor_global_index].windows_processor_id = (uint16_t)processor_id_in_group; - /* As we're counting the number of packages now, we haven't allocated memory for - * cpuinfo_packages yet, so we only set the package pointer's offset now. + /* As we're counting the number of packages now, we haven't allocated + * memory for cpuinfo_packages yet, so we only set the package pointer's + * offset now. */ - processors[processor_global_index].package = - (const struct cpuinfo_package*) NULL + package_id; + processors[processor_global_index].package = (const struct cpuinfo_package*)NULL + package_id; } void store_core_info_per_processor( @@ -741,22 +746,22 @@ void store_core_info_per_processor( const uint32_t core_id, PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX core_info, struct cpuinfo_core* cores, - const struct woa_chip_info *chip_info) -{ + const struct woa_chip_info* chip_info) { if (cores) { processors[processor_global_index].core = cores + core_id; cores[core_id].core_id = core_id; get_core_uarch_for_efficiency( - chip_info->chip_name, core_info->Processor.EfficiencyClass, - &(cores[core_id].uarch), &(cores[core_id].frequency)); + chip_info->chip_name, + core_info->Processor.EfficiencyClass, + &(cores[core_id].uarch), + &(cores[core_id].frequency)); /* We don't have cluster information, so we handle it as * fixed 1 to (cluster / cores). * Set the cluster offset ID now, as soon as we have the * cluster base address, we'll set the absolute address. */ - processors[processor_global_index].cluster = - (const struct cpuinfo_cluster*) NULL + core_id; + processors[processor_global_index].cluster = (const struct cpuinfo_cluster*)NULL + core_id; } } @@ -764,36 +769,35 @@ static void store_cache_info_per_processor( struct cpuinfo_processor* processors, const uint32_t processor_global_index, PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX info, - struct cpuinfo_cache* current_cache) -{ + struct cpuinfo_cache* current_cache) { if (current_cache->processor_start > processor_global_index) { current_cache->processor_start = processor_global_index; } current_cache->processor_count++; - switch(info->Cache.Level) { + switch (info->Cache.Level) { case 1: switch (info->Cache.Type) { case CacheInstruction: processors[processor_global_index].cache.l1i = current_cache; - break; + break; case CacheData: processors[processor_global_index].cache.l1d = current_cache; - break; + break; case CacheUnified: - break; + break; case CacheTrace: - break; + break; default: - break; + break; } - break; + break; case 2: processors[processor_global_index].cache.l2 = current_cache; - break; + break; case 3: processors[processor_global_index].cache.l3 = current_cache; - break; + break; } } @@ -806,8 +810,7 @@ static bool connect_packages_cores_clusters_by_processors( struct cpuinfo_core* cores, const uint32_t nr_of_cores, const struct woa_chip_info* chip_info, - enum cpuinfo_vendor vendor) -{ + enum cpuinfo_vendor vendor) { /* Adjust core and package pointers for all logical processors. */ for (uint32_t i = nr_of_processors; i != 0; i--) { const uint32_t processor_id = i - 1; @@ -815,22 +818,21 @@ static bool connect_packages_cores_clusters_by_processors( struct cpuinfo_core* core = (struct cpuinfo_core*)processor->core; - /* We stored the offset of pointers when we haven't allocated memory - * for packages and clusters, so now add offsets to base addresses. + /* We stored the offset of pointers when we haven't allocated + * memory for packages and clusters, so now add offsets to base + * addresses. */ struct cpuinfo_package* package = - (struct cpuinfo_package*) ((uintptr_t) packages + (uintptr_t) processor->package); - if (package < packages || - package >= (packages + nr_of_packages)) { + (struct cpuinfo_package*)((uintptr_t)packages + (uintptr_t)processor->package); + if (package < packages || package >= (packages + nr_of_packages)) { cpuinfo_log_error("invalid package indexing"); return false; } processor->package = package; struct cpuinfo_cluster* cluster = - (struct cpuinfo_cluster*) ((uintptr_t) clusters + (uintptr_t) processor->cluster); - if (cluster < clusters || - cluster >= (clusters + nr_of_cores)) { + (struct cpuinfo_cluster*)((uintptr_t)clusters + (uintptr_t)processor->cluster); + if (cluster < clusters || cluster >= (clusters + nr_of_cores)) { cpuinfo_log_error("invalid cluster indexing"); return false; } @@ -839,30 +841,34 @@ static bool connect_packages_cores_clusters_by_processors( if (chip_info) { size_t converted_chars = 0; if (!WideCharToMultiByte( - CP_UTF8, - WC_ERR_INVALID_CHARS, - chip_info->chip_name_string, - -1, - package->name, - CPUINFO_PACKAGE_NAME_MAX, - NULL, - NULL)) { + CP_UTF8, + WC_ERR_INVALID_CHARS, + chip_info->chip_name_string, + -1, + package->name, + CPUINFO_PACKAGE_NAME_MAX, + NULL, + NULL)) { cpuinfo_log_error("cpu name character conversion error"); return false; }; } - /* Set start indexes and counts per packages / clusters / cores - going backwards */ + /* Set start indexes and counts per packages / clusters / cores + * - going backwards */ - /* This can be overwritten by lower-index processors on the same package. */ + /* This can be overwritten by lower-index processors on the same + * package. */ package->processor_start = processor_id; package->processor_count++; - /* This can be overwritten by lower-index processors on the same cluster. */ + /* This can be overwritten by lower-index processors on the same + * cluster. */ cluster->processor_start = processor_id; cluster->processor_count++; - /* This can be overwritten by lower-index processors on the same core. */ + /* This can be overwritten by lower-index processors on the same + * core. */ core->processor_start = processor_id; core->processor_count++; } @@ -871,14 +877,16 @@ static bool connect_packages_cores_clusters_by_processors( const uint32_t global_core_id = i - 1; struct cpuinfo_core* core = cores + global_core_id; const struct cpuinfo_processor* processor = processors + core->processor_start; - struct cpuinfo_package* package = (struct cpuinfo_package*) processor->package; - struct cpuinfo_cluster* cluster = (struct cpuinfo_cluster*) processor->cluster; + struct cpuinfo_package* package = (struct cpuinfo_package*)processor->package; + struct cpuinfo_cluster* cluster = (struct cpuinfo_cluster*)processor->cluster; core->package = package; core->cluster = cluster; core->vendor = vendor; - /* This can be overwritten by lower-index cores on the same cluster/package. */ + /* This can be overwritten by lower-index cores on the same + * cluster/package. + */ cluster->core_start = global_core_id; cluster->core_count++; package->core_start = global_core_id; @@ -896,6 +904,6 @@ static bool connect_packages_cores_clusters_by_processors( static inline uint32_t low_index_from_kaffinity(KAFFINITY kaffinity) { unsigned long index; - _BitScanForward64(&index, (unsigned __int64) kaffinity); - return (uint32_t) index; + _BitScanForward64(&index, (unsigned __int64)kaffinity); + return (uint32_t)index; } diff --git a/3rdparty/cpuinfo/src/arm/windows/init.c b/3rdparty/cpuinfo/src/arm/windows/init.c index cff89196bf..faa30ef567 100644 --- a/3rdparty/cpuinfo/src/arm/windows/init.c +++ b/3rdparty/cpuinfo/src/arm/windows/init.c @@ -1,7 +1,7 @@ -#include -#include -#include #include +#include +#include +#include #include #include @@ -17,88 +17,64 @@ static struct woa_chip_info* get_system_info_from_registry(void); static struct woa_chip_info woa_chip_unknown = { L"Unknown", woa_chip_name_unknown, - { - { - cpuinfo_vendor_unknown, - cpuinfo_uarch_unknown, - 0 - } - } -}; + {{cpuinfo_vendor_unknown, cpuinfo_uarch_unknown, 0}}}; /* Please add new SoC/chip info here! */ -static struct woa_chip_info woa_chips[] = { +static struct woa_chip_info woa_chips[woa_chip_name_last] = { /* Microsoft SQ1 Kryo 495 4 + 4 cores (3 GHz + 1.80 GHz) */ - { - L"Microsoft SQ1", - woa_chip_name_microsoft_sq_1, - { - { - cpuinfo_vendor_arm, - cpuinfo_uarch_cortex_a55, - 1800000000, - }, - { - cpuinfo_vendor_arm, - cpuinfo_uarch_cortex_a76, - 3000000000, - } - } - }, + [woa_chip_name_microsoft_sq_1] = + {L"Microsoft SQ1", + woa_chip_name_microsoft_sq_1, + {{ + cpuinfo_vendor_arm, + cpuinfo_uarch_cortex_a55, + 1800000000, + }, + { + cpuinfo_vendor_arm, + cpuinfo_uarch_cortex_a76, + 3000000000, + }}}, /* Microsoft SQ2 Kryo 495 4 + 4 cores (3.15 GHz + 2.42 GHz) */ - { - L"Microsoft SQ2", - woa_chip_name_microsoft_sq_2, - { - { - cpuinfo_vendor_arm, - cpuinfo_uarch_cortex_a55, - 2420000000, - }, - { - cpuinfo_vendor_arm, - cpuinfo_uarch_cortex_a76, - 3150000000 - } - } - }, + [woa_chip_name_microsoft_sq_2] = + {L"Microsoft SQ2", + woa_chip_name_microsoft_sq_2, + {{ + cpuinfo_vendor_arm, + cpuinfo_uarch_cortex_a55, + 2420000000, + }, + {cpuinfo_vendor_arm, cpuinfo_uarch_cortex_a76, 3150000000}}}, + /* Snapdragon (TM) 8cx Gen 3 @ 3.0 GHz */ + [woa_chip_name_microsoft_sq_3] = + {L"Snapdragon (TM) 8cx Gen 3", + woa_chip_name_microsoft_sq_3, + {{ + cpuinfo_vendor_arm, + cpuinfo_uarch_cortex_a78, + 2420000000, + }, + {cpuinfo_vendor_arm, cpuinfo_uarch_cortex_x1, 3000000000}}}, /* Microsoft Windows Dev Kit 2023 */ - { - L"Snapdragon Compute Platform", - woa_chip_name_microsoft_sq_3, - { - { - cpuinfo_vendor_arm, - cpuinfo_uarch_cortex_a78, - 2420000000, - }, - { - cpuinfo_vendor_arm, - cpuinfo_uarch_cortex_x1, - 3000000000 - } - } - }, + [woa_chip_name_microsoft_sq_3_devkit] = + {L"Snapdragon Compute Platform", + woa_chip_name_microsoft_sq_3_devkit, + {{ + cpuinfo_vendor_arm, + cpuinfo_uarch_cortex_a78, + 2420000000, + }, + {cpuinfo_vendor_arm, cpuinfo_uarch_cortex_x1, 3000000000}}}, /* Ampere Altra */ - { + [woa_chip_name_ampere_altra] = { L"Ampere(R) Altra(R) Processor", woa_chip_name_ampere_altra, - { - { - cpuinfo_vendor_arm, - cpuinfo_uarch_neoverse_n1, - 3000000000 - } - } - } -}; + {{cpuinfo_vendor_arm, cpuinfo_uarch_neoverse_n1, 3000000000}}}}; -BOOL CALLBACK cpuinfo_arm_windows_init( - PINIT_ONCE init_once, PVOID parameter, PVOID* context) -{ - struct woa_chip_info *chip_info = NULL; +BOOL CALLBACK cpuinfo_arm_windows_init(PINIT_ONCE init_once, PVOID parameter, PVOID* context) { + struct woa_chip_info* chip_info = NULL; enum cpuinfo_vendor vendor = cpuinfo_vendor_unknown; - + set_cpuinfo_isa_fields(); chip_info = get_system_info_from_registry(); @@ -112,15 +88,15 @@ BOOL CALLBACK cpuinfo_arm_windows_init( } bool get_core_uarch_for_efficiency( - enum woa_chip_name chip, BYTE EfficiencyClass, - enum cpuinfo_uarch* uarch, uint64_t* frequency) -{ + enum woa_chip_name chip, + BYTE EfficiencyClass, + enum cpuinfo_uarch* uarch, + uint64_t* frequency) { /* For currently supported WoA chips, the Efficiency class selects * the pre-defined little and big core. * Any further supported SoC's logic should be implemented here. */ - if (uarch && frequency && chip < woa_chip_name_last && - EfficiencyClass < MAX_WOA_VALID_EFFICIENCY_CLASSES) { + if (uarch && frequency && chip < woa_chip_name_last && EfficiencyClass < MAX_WOA_VALID_EFFICIENCY_CLASSES) { *uarch = woa_chips[chip].uarchs[EfficiencyClass].uarch; *frequency = woa_chips[chip].uarchs[EfficiencyClass].frequency; return true; @@ -130,14 +106,11 @@ bool get_core_uarch_for_efficiency( /* Static helper functions */ -static wchar_t* read_registry( - LPCWSTR subkey, - LPCWSTR value) -{ +static wchar_t* read_registry(LPCWSTR subkey, LPCWSTR value) { DWORD key_type = 0; DWORD data_size = 0; const DWORD flags = RRF_RT_REG_SZ; /* Only read strings (REG_SZ) */ - wchar_t *text_buffer = NULL; + wchar_t* text_buffer = NULL; LSTATUS result = 0; HANDLE heap = GetProcessHeap(); @@ -176,8 +149,7 @@ static wchar_t* read_registry( return text_buffer; } -static struct woa_chip_info* get_system_info_from_registry(void) -{ +static struct woa_chip_info* get_system_info_from_registry(void) { wchar_t* text_buffer = NULL; LPCWSTR cpu0_subkey = L"HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\0"; LPCWSTR chip_name_value = L"ProcessorNameString"; @@ -185,23 +157,27 @@ static struct woa_chip_info* get_system_info_from_registry(void) HANDLE heap = GetProcessHeap(); - /* Read processor model name from registry and find in the hard-coded list. */ + /* Read processor model name from registry and find in the hard-coded + * list. */ text_buffer = read_registry(cpu0_subkey, chip_name_value); if (text_buffer == NULL) { cpuinfo_log_error("Registry read error"); return NULL; } - for (uint32_t i = 0; i < (uint32_t) woa_chip_name_last; i++) { + for (uint32_t i = 0; i < (uint32_t)woa_chip_name_last; i++) { size_t compare_length = wcsnlen(woa_chips[i].chip_name_string, CPUINFO_PACKAGE_NAME_MAX); int compare_result = wcsncmp(text_buffer, woa_chips[i].chip_name_string, compare_length); if (compare_result == 0) { - chip_info = woa_chips+i; + chip_info = woa_chips + i; break; } } if (chip_info == NULL) { - /* No match was found, so print a warning and assign the unknown case. */ - cpuinfo_log_error("Unknown chip model name '%ls'.\nPlease add new Windows on Arm SoC/chip support to arm/windows/init.c!", text_buffer); + /* No match was found, so print a warning and assign the unknown + * case. */ + cpuinfo_log_error( + "Unknown chip model name '%ls'.\nPlease add new Windows on Arm SoC/chip support to arm/windows/init.c!", + text_buffer); } else { cpuinfo_log_debug("detected chip model name: %s", chip_info->chip_name_string); } @@ -210,8 +186,7 @@ static struct woa_chip_info* get_system_info_from_registry(void) return chip_info; } -static void set_cpuinfo_isa_fields(void) -{ +static void set_cpuinfo_isa_fields(void) { cpuinfo_isa.atomics = IsProcessorFeaturePresent(PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE) != 0; const bool dotprod = IsProcessorFeaturePresent(PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE) != 0; @@ -220,13 +195,14 @@ static void set_cpuinfo_isa_fields(void) SYSTEM_INFO system_info; GetSystemInfo(&system_info); switch (system_info.wProcessorLevel) { - case 0x803: // Kryo 385 Silver (Snapdragon 850) + case 0x803: // Kryo 385 Silver (Snapdragon 850) cpuinfo_isa.fp16arith = dotprod; cpuinfo_isa.rdm = dotprod; break; default: - // Assume that Dot Product support implies FP16 arithmetics and RDM support. - // ARM manuals don't guarantee that, but it holds in practice. + // Assume that Dot Product support implies FP16 + // arithmetics and RDM support. ARM manuals don't + // guarantee that, but it holds in practice. cpuinfo_isa.fp16arith = dotprod; cpuinfo_isa.rdm = dotprod; break; diff --git a/3rdparty/cpuinfo/src/arm/windows/windows-arm-init.h b/3rdparty/cpuinfo/src/arm/windows/windows-arm-init.h index e327431bd9..b054a29822 100644 --- a/3rdparty/cpuinfo/src/arm/windows/windows-arm-init.h +++ b/3rdparty/cpuinfo/src/arm/windows/windows-arm-init.h @@ -1,15 +1,16 @@ #pragma once /* Efficiency class = 0 means little core, while 1 means big core for now. */ -#define MAX_WOA_VALID_EFFICIENCY_CLASSES 2 +#define MAX_WOA_VALID_EFFICIENCY_CLASSES 2 /* List of known and supported Windows on Arm SoCs/chips. */ enum woa_chip_name { woa_chip_name_microsoft_sq_1 = 0, woa_chip_name_microsoft_sq_2 = 1, woa_chip_name_microsoft_sq_3 = 2, - woa_chip_name_ampere_altra = 3, - woa_chip_name_unknown = 4, + woa_chip_name_microsoft_sq_3_devkit = 3, + woa_chip_name_ampere_altra = 4, + woa_chip_name_unknown = 5, woa_chip_name_last = woa_chip_name_unknown }; @@ -30,9 +31,9 @@ struct woa_chip_info { }; bool get_core_uarch_for_efficiency( - enum woa_chip_name chip, BYTE EfficiencyClass, - enum cpuinfo_uarch* uarch, uint64_t* frequency); + enum woa_chip_name chip, + BYTE EfficiencyClass, + enum cpuinfo_uarch* uarch, + uint64_t* frequency); -bool cpu_info_init_by_logical_sys_info( - const struct woa_chip_info *chip_info, - enum cpuinfo_vendor vendor); +bool cpu_info_init_by_logical_sys_info(const struct woa_chip_info* chip_info, enum cpuinfo_vendor vendor); diff --git a/3rdparty/cpuinfo/src/cache.c b/3rdparty/cpuinfo/src/cache.c index b976b8796f..2eb4b16d58 100644 --- a/3rdparty/cpuinfo/src/cache.c +++ b/3rdparty/cpuinfo/src/cache.c @@ -3,16 +3,15 @@ #include #include - uint32_t cpuinfo_compute_max_cache_size(const struct cpuinfo_processor* processor) { - if (processor->cache.l4 != NULL) { - return processor->cache.l4->size; - } else if (processor->cache.l3 != NULL) { - return processor->cache.l3->size; - } else if (processor->cache.l2 != NULL) { - return processor->cache.l2->size; - } else if (processor->cache.l1d != NULL) { - return processor->cache.l1d->size; - } - return 0; + if (processor->cache.l4 != NULL) { + return processor->cache.l4->size; + } else if (processor->cache.l3 != NULL) { + return processor->cache.l3->size; + } else if (processor->cache.l2 != NULL) { + return processor->cache.l2->size; + } else if (processor->cache.l1d != NULL) { + return processor->cache.l1d->size; + } + return 0; } diff --git a/3rdparty/cpuinfo/src/cpuinfo/common.h b/3rdparty/cpuinfo/src/cpuinfo/common.h index b2b404d742..5aa7c83999 100644 --- a/3rdparty/cpuinfo/src/cpuinfo/common.h +++ b/3rdparty/cpuinfo/src/cpuinfo/common.h @@ -8,33 +8,32 @@ #pragma once - -#define CPUINFO_COUNT_OF(array) (sizeof(array) / sizeof(0[array])) +#define CPUINFO_COUNT_OF(array) (sizeof(array) / sizeof(0 [array])) #if defined(__GNUC__) - #define CPUINFO_LIKELY(condition) (__builtin_expect(!!(condition), 1)) - #define CPUINFO_UNLIKELY(condition) (__builtin_expect(!!(condition), 0)) +#define CPUINFO_LIKELY(condition) (__builtin_expect(!!(condition), 1)) +#define CPUINFO_UNLIKELY(condition) (__builtin_expect(!!(condition), 0)) #else - #define CPUINFO_LIKELY(condition) (!!(condition)) - #define CPUINFO_UNLIKELY(condition) (!!(condition)) +#define CPUINFO_LIKELY(condition) (!!(condition)) +#define CPUINFO_UNLIKELY(condition) (!!(condition)) #endif #ifndef CPUINFO_INTERNAL - #if defined(__ELF__) - #define CPUINFO_INTERNAL __attribute__((__visibility__("internal"))) - #elif defined(__MACH__) - #define CPUINFO_INTERNAL __attribute__((__visibility__("hidden"))) - #else - #define CPUINFO_INTERNAL - #endif +#if defined(__ELF__) +#define CPUINFO_INTERNAL __attribute__((__visibility__("internal"))) +#elif defined(__MACH__) +#define CPUINFO_INTERNAL __attribute__((__visibility__("hidden"))) +#else +#define CPUINFO_INTERNAL +#endif #endif #ifndef CPUINFO_PRIVATE - #if defined(__ELF__) - #define CPUINFO_PRIVATE __attribute__((__visibility__("hidden"))) - #elif defined(__MACH__) - #define CPUINFO_PRIVATE __attribute__((__visibility__("hidden"))) - #else - #define CPUINFO_PRIVATE - #endif +#if defined(__ELF__) +#define CPUINFO_PRIVATE __attribute__((__visibility__("hidden"))) +#elif defined(__MACH__) +#define CPUINFO_PRIVATE __attribute__((__visibility__("hidden"))) +#else +#define CPUINFO_PRIVATE +#endif #endif diff --git a/3rdparty/cpuinfo/src/cpuinfo/internal-api.h b/3rdparty/cpuinfo/src/cpuinfo/internal-api.h index 69a9ec984d..d84b26a89c 100644 --- a/3rdparty/cpuinfo/src/cpuinfo/internal-api.h +++ b/3rdparty/cpuinfo/src/cpuinfo/internal-api.h @@ -1,22 +1,21 @@ #pragma once -#include #include +#include #if defined(_WIN32) || defined(__CYGWIN__) - #include +#include #endif #include #include - enum cpuinfo_cache_level { - cpuinfo_cache_level_1i = 0, - cpuinfo_cache_level_1d = 1, - cpuinfo_cache_level_2 = 2, - cpuinfo_cache_level_3 = 3, - cpuinfo_cache_level_4 = 4, + cpuinfo_cache_level_1i = 0, + cpuinfo_cache_level_1d = 1, + cpuinfo_cache_level_2 = 2, + cpuinfo_cache_level_3 = 3, + cpuinfo_cache_level_4 = 4, cpuinfo_cache_level_max = 5, }; @@ -36,26 +35,27 @@ extern CPUINFO_INTERNAL uint32_t cpuinfo_cache_count[cpuinfo_cache_level_max]; extern CPUINFO_INTERNAL uint32_t cpuinfo_max_cache_size; #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - extern CPUINFO_INTERNAL struct cpuinfo_uarch_info* cpuinfo_uarchs; - extern CPUINFO_INTERNAL uint32_t cpuinfo_uarchs_count; +extern CPUINFO_INTERNAL struct cpuinfo_uarch_info* cpuinfo_uarchs; +extern CPUINFO_INTERNAL uint32_t cpuinfo_uarchs_count; #else - extern CPUINFO_INTERNAL struct cpuinfo_uarch_info cpuinfo_global_uarch; +extern CPUINFO_INTERNAL struct cpuinfo_uarch_info cpuinfo_global_uarch; #endif #ifdef __linux__ - extern CPUINFO_INTERNAL uint32_t cpuinfo_linux_cpu_max; - extern CPUINFO_INTERNAL const struct cpuinfo_processor** cpuinfo_linux_cpu_to_processor_map; - extern CPUINFO_INTERNAL const struct cpuinfo_core** cpuinfo_linux_cpu_to_core_map; +extern CPUINFO_INTERNAL uint32_t cpuinfo_linux_cpu_max; +extern CPUINFO_INTERNAL const struct cpuinfo_processor** cpuinfo_linux_cpu_to_processor_map; +extern CPUINFO_INTERNAL const struct cpuinfo_core** cpuinfo_linux_cpu_to_core_map; #endif CPUINFO_PRIVATE void cpuinfo_x86_mach_init(void); CPUINFO_PRIVATE void cpuinfo_x86_linux_init(void); +CPUINFO_PRIVATE void cpuinfo_x86_freebsd_init(void); #if defined(_WIN32) || defined(__CYGWIN__) - #if CPUINFO_ARCH_ARM64 - CPUINFO_PRIVATE BOOL CALLBACK cpuinfo_arm_windows_init(PINIT_ONCE init_once, PVOID parameter, PVOID* context); - #else - CPUINFO_PRIVATE BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PVOID* context); - #endif +#if CPUINFO_ARCH_ARM64 +CPUINFO_PRIVATE BOOL CALLBACK cpuinfo_arm_windows_init(PINIT_ONCE init_once, PVOID parameter, PVOID* context); +#else +CPUINFO_PRIVATE BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PVOID* context); +#endif #endif CPUINFO_PRIVATE void cpuinfo_arm_mach_init(void); CPUINFO_PRIVATE void cpuinfo_arm_linux_init(void); diff --git a/3rdparty/cpuinfo/src/cpuinfo/log.h b/3rdparty/cpuinfo/src/cpuinfo/log.h index 5bd4305565..52e3475fa9 100644 --- a/3rdparty/cpuinfo/src/cpuinfo/log.h +++ b/3rdparty/cpuinfo/src/cpuinfo/log.h @@ -5,7 +5,7 @@ #include #ifndef CPUINFO_LOG_LEVEL - #error "Undefined CPUINFO_LOG_LEVEL" +#error "Undefined CPUINFO_LOG_LEVEL" #endif #define CPUINFO_LOG_NONE 0 @@ -16,88 +16,87 @@ #define CPUINFO_LOG_DEBUG 5 #ifndef CPUINFO_LOG_DEBUG_PARSERS - #define CPUINFO_LOG_DEBUG_PARSERS 0 +#define CPUINFO_LOG_DEBUG_PARSERS 0 #endif - #ifdef __cplusplus extern "C" { #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_DEBUG - void cpuinfo_vlog_debug(const char* format, va_list args); +void cpuinfo_vlog_debug(const char* format, va_list args); #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_INFO - void cpuinfo_vlog_info(const char* format, va_list args); +void cpuinfo_vlog_info(const char* format, va_list args); #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_WARNING - void cpuinfo_vlog_warning(const char* format, va_list args); +void cpuinfo_vlog_warning(const char* format, va_list args); #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_ERROR - void cpuinfo_vlog_error(const char* format, va_list args); +void cpuinfo_vlog_error(const char* format, va_list args); #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_FATAL - void cpuinfo_vlog_fatal(const char* format, va_list args); +void cpuinfo_vlog_fatal(const char* format, va_list args); #endif #ifdef __cplusplus -} // extern "C" +} // extern "C" #endif #ifndef CPUINFO_LOG_ARGUMENTS_FORMAT - #ifdef __GNUC__ - #define CPUINFO_LOG_ARGUMENTS_FORMAT __attribute__((__format__(__printf__, 1, 2))) - #else - #define CPUINFO_LOG_ARGUMENTS_FORMAT - #endif +#ifdef __GNUC__ +#define CPUINFO_LOG_ARGUMENTS_FORMAT __attribute__((__format__(__printf__, 1, 2))) +#else +#define CPUINFO_LOG_ARGUMENTS_FORMAT +#endif #endif CPUINFO_LOG_ARGUMENTS_FORMAT inline static void cpuinfo_log_debug(const char* format, ...) { - #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_DEBUG - va_list args; - va_start(args, format); - cpuinfo_vlog_debug(format, args); - va_end(args); - #endif +#if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_DEBUG + va_list args; + va_start(args, format); + cpuinfo_vlog_debug(format, args); + va_end(args); +#endif } CPUINFO_LOG_ARGUMENTS_FORMAT inline static void cpuinfo_log_info(const char* format, ...) { - #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_INFO - va_list args; - va_start(args, format); - cpuinfo_vlog_info(format, args); - va_end(args); - #endif +#if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_INFO + va_list args; + va_start(args, format); + cpuinfo_vlog_info(format, args); + va_end(args); +#endif } CPUINFO_LOG_ARGUMENTS_FORMAT inline static void cpuinfo_log_warning(const char* format, ...) { - #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_WARNING - va_list args; - va_start(args, format); - cpuinfo_vlog_warning(format, args); - va_end(args); - #endif +#if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_WARNING + va_list args; + va_start(args, format); + cpuinfo_vlog_warning(format, args); + va_end(args); +#endif } CPUINFO_LOG_ARGUMENTS_FORMAT inline static void cpuinfo_log_error(const char* format, ...) { - #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_ERROR - va_list args; - va_start(args, format); - cpuinfo_vlog_error(format, args); - va_end(args); - #endif +#if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_ERROR + va_list args; + va_start(args, format); + cpuinfo_vlog_error(format, args); + va_end(args); +#endif } CPUINFO_LOG_ARGUMENTS_FORMAT inline static void cpuinfo_log_fatal(const char* format, ...) { - #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_FATAL - va_list args; - va_start(args, format); - cpuinfo_vlog_fatal(format, args); - va_end(args); - #endif +#if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_FATAL + va_list args; + va_start(args, format); + cpuinfo_vlog_fatal(format, args); + va_end(args); +#endif abort(); } \ No newline at end of file diff --git a/3rdparty/cpuinfo/src/cpuinfo/utils.h b/3rdparty/cpuinfo/src/cpuinfo/utils.h index 6cfaca7bb4..6556a6602a 100644 --- a/3rdparty/cpuinfo/src/cpuinfo/utils.h +++ b/3rdparty/cpuinfo/src/cpuinfo/utils.h @@ -5,18 +5,17 @@ #endif #include - inline static uint32_t bit_length(uint32_t n) { const uint32_t n_minus_1 = n - 1; if (n_minus_1 == 0) { return 0; } else { - #ifdef _MSC_VER - unsigned long bsr; - _BitScanReverse(&bsr, n_minus_1); - return bsr + 1; - #else - return 32 - __builtin_clz(n_minus_1); - #endif +#ifdef _MSC_VER + unsigned long bsr; + _BitScanReverse(&bsr, n_minus_1); + return bsr + 1; +#else + return 32 - __builtin_clz(n_minus_1); +#endif } } diff --git a/3rdparty/cpuinfo/src/emscripten/init.c b/3rdparty/cpuinfo/src/emscripten/init.c index ce4bdea2ee..c239324375 100644 --- a/3rdparty/cpuinfo/src/emscripten/init.c +++ b/3rdparty/cpuinfo/src/emscripten/init.c @@ -1,8 +1,8 @@ +#include #include #include #include #include -#include #include @@ -10,10 +10,9 @@ #include #include - static const volatile float infinity = INFINITY; -static struct cpuinfo_package static_package = { }; +static struct cpuinfo_package static_package = {}; static struct cpuinfo_cache static_x86_l3 = { .size = 2 * 1024 * 1024, @@ -37,7 +36,7 @@ void cpuinfo_emscripten_init(void) { if (logical_cores_count <= 0) { logical_cores_count = 1; } - uint32_t processor_count = (uint32_t) logical_cores_count; + uint32_t processor_count = (uint32_t)logical_cores_count; uint32_t core_count = processor_count; uint32_t cluster_count = 1; uint32_t big_cluster_core_count = core_count; @@ -60,41 +59,53 @@ void cpuinfo_emscripten_init(void) { processors = calloc(processor_count, sizeof(struct cpuinfo_processor)); if (processors == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" logical processors", - processor_count * sizeof(struct cpuinfo_processor), processor_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " logical processors", + processor_count * sizeof(struct cpuinfo_processor), + processor_count); goto cleanup; } cores = calloc(processor_count, sizeof(struct cpuinfo_core)); if (cores == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" cores", - processor_count * sizeof(struct cpuinfo_core), processor_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " cores", + processor_count * sizeof(struct cpuinfo_core), + processor_count); goto cleanup; } clusters = calloc(cluster_count, sizeof(struct cpuinfo_cluster)); if (clusters == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" clusters", - cluster_count * sizeof(struct cpuinfo_cluster), cluster_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " clusters", + cluster_count * sizeof(struct cpuinfo_cluster), + cluster_count); goto cleanup; } l1i = calloc(core_count, sizeof(struct cpuinfo_cache)); if (l1i == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1I caches", - core_count * sizeof(struct cpuinfo_cache), core_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1I caches", + core_count * sizeof(struct cpuinfo_cache), + core_count); goto cleanup; } l1d = calloc(core_count, sizeof(struct cpuinfo_cache)); if (l1d == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1D caches", - core_count * sizeof(struct cpuinfo_cache), core_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1D caches", + core_count * sizeof(struct cpuinfo_cache), + core_count); goto cleanup; } l2 = calloc(l2_count, sizeof(struct cpuinfo_cache)); if (l2 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L2 caches", - l2_count * sizeof(struct cpuinfo_cache), l2_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L2 caches", + l2_count * sizeof(struct cpuinfo_cache), + l2_count); goto cleanup; } @@ -109,30 +120,30 @@ void cpuinfo_emscripten_init(void) { for (uint32_t i = 0; i < core_count; i++) { for (uint32_t j = 0; j < processors_per_core; j++) { - processors[i * processors_per_core + j] = (struct cpuinfo_processor) { + processors[i * processors_per_core + j] = (struct cpuinfo_processor){ .smt_id = j, .core = cores + i, - .cluster = clusters + (uint32_t) (i >= big_cluster_core_count), + .cluster = clusters + (uint32_t)(i >= big_cluster_core_count), .package = &static_package, .cache.l1i = l1i + i, .cache.l1d = l1d + i, - .cache.l2 = is_x86 ? l2 + i : l2 + (uint32_t) (i >= big_cluster_core_count), + .cache.l2 = is_x86 ? l2 + i : l2 + (uint32_t)(i >= big_cluster_core_count), .cache.l3 = is_x86 ? &static_x86_l3 : NULL, }; } - cores[i] = (struct cpuinfo_core) { + cores[i] = (struct cpuinfo_core){ .processor_start = i * processors_per_core, .processor_count = processors_per_core, .core_id = i, - .cluster = clusters + (uint32_t) (i >= big_cluster_core_count), + .cluster = clusters + (uint32_t)(i >= big_cluster_core_count), .package = &static_package, .vendor = cpuinfo_vendor_unknown, .uarch = cpuinfo_uarch_unknown, .frequency = 0, }; - l1i[i] = (struct cpuinfo_cache) { + l1i[i] = (struct cpuinfo_cache){ .size = 32 * 1024, .associativity = 4, .sets = 128, @@ -142,7 +153,7 @@ void cpuinfo_emscripten_init(void) { .processor_count = processors_per_core, }; - l1d[i] = (struct cpuinfo_cache) { + l1d[i] = (struct cpuinfo_cache){ .size = 32 * 1024, .associativity = 4, .sets = 128, @@ -153,7 +164,7 @@ void cpuinfo_emscripten_init(void) { }; if (is_x86) { - l2[i] = (struct cpuinfo_cache) { + l2[i] = (struct cpuinfo_cache){ .size = 256 * 1024, .associativity = 8, .sets = 512, @@ -166,7 +177,7 @@ void cpuinfo_emscripten_init(void) { } if (is_x86) { - clusters[0] = (struct cpuinfo_cluster) { + clusters[0] = (struct cpuinfo_cluster){ .processor_start = 0, .processor_count = processor_count, .core_start = 0, @@ -180,7 +191,7 @@ void cpuinfo_emscripten_init(void) { static_x86_l3.processor_count = processor_count; } else { - clusters[0] = (struct cpuinfo_cluster) { + clusters[0] = (struct cpuinfo_cluster){ .processor_start = 0, .processor_count = big_cluster_core_count, .core_start = 0, @@ -192,7 +203,7 @@ void cpuinfo_emscripten_init(void) { .frequency = 0, }; - l2[0] = (struct cpuinfo_cache) { + l2[0] = (struct cpuinfo_cache){ .size = 1024 * 1024, .associativity = 8, .sets = 2048, @@ -203,7 +214,7 @@ void cpuinfo_emscripten_init(void) { }; if (cluster_count > 1) { - l2[1] = (struct cpuinfo_cache) { + l2[1] = (struct cpuinfo_cache){ .size = 256 * 1024, .associativity = 8, .sets = 512, @@ -213,7 +224,7 @@ void cpuinfo_emscripten_init(void) { .processor_count = processor_count - big_cluster_core_count, }; - clusters[1] = (struct cpuinfo_cluster) { + clusters[1] = (struct cpuinfo_cluster){ .processor_start = big_cluster_core_count, .processor_count = processor_count - big_cluster_core_count, .core_start = big_cluster_core_count, @@ -230,9 +241,9 @@ void cpuinfo_emscripten_init(void) { /* Commit changes */ cpuinfo_cache[cpuinfo_cache_level_1i] = l1i; cpuinfo_cache[cpuinfo_cache_level_1d] = l1d; - cpuinfo_cache[cpuinfo_cache_level_2] = l2; + cpuinfo_cache[cpuinfo_cache_level_2] = l2; if (is_x86) { - cpuinfo_cache[cpuinfo_cache_level_3] = &static_x86_l3; + cpuinfo_cache[cpuinfo_cache_level_3] = &static_x86_l3; } cpuinfo_processors = processors; @@ -242,12 +253,12 @@ void cpuinfo_emscripten_init(void) { cpuinfo_cache_count[cpuinfo_cache_level_1i] = processor_count; cpuinfo_cache_count[cpuinfo_cache_level_1d] = processor_count; - cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; + cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; if (is_x86) { - cpuinfo_cache_count[cpuinfo_cache_level_3] = 1; + cpuinfo_cache_count[cpuinfo_cache_level_3] = 1; } - cpuinfo_global_uarch = (struct cpuinfo_uarch_info) { + cpuinfo_global_uarch = (struct cpuinfo_uarch_info){ .uarch = cpuinfo_uarch_unknown, .processor_count = processor_count, .core_count = core_count, diff --git a/3rdparty/cpuinfo/src/freebsd/api.h b/3rdparty/cpuinfo/src/freebsd/api.h new file mode 100644 index 0000000000..d3774370cd --- /dev/null +++ b/3rdparty/cpuinfo/src/freebsd/api.h @@ -0,0 +1,12 @@ +#pragma once + +#include + +struct cpuinfo_freebsd_topology { + uint32_t packages; + uint32_t cores; + uint32_t threads; + uint32_t threads_per_core; +}; + +struct cpuinfo_freebsd_topology cpuinfo_freebsd_detect_topology(void); diff --git a/3rdparty/cpuinfo/src/freebsd/topology.c b/3rdparty/cpuinfo/src/freebsd/topology.c new file mode 100644 index 0000000000..da941e9cb2 --- /dev/null +++ b/3rdparty/cpuinfo/src/freebsd/topology.c @@ -0,0 +1,104 @@ +#include +#include +#include + +#include +#include + +#include +#include + +static int sysctl_int(const char* name) { + int value = 0; + size_t value_size = sizeof(value); + if (sysctlbyname(name, &value, &value_size, NULL, 0) != 0) { + cpuinfo_log_error("sysctlbyname(\"%s\") failed: %s", name, strerror(errno)); + } else if (value <= 0) { + cpuinfo_log_error("sysctlbyname(\"%s\") returned invalid value %d %zu", name, value, value_size); + value = 0; + } + return value; +} + +static char* sysctl_str(const char* name) { + size_t value_size = 0; + if (sysctlbyname(name, NULL, &value_size, NULL, 0) != 0) { + cpuinfo_log_error("sysctlbyname(\"%s\") failed: %s", name, strerror(errno)); + } else if (value_size <= 0) { + cpuinfo_log_error("sysctlbyname(\"%s\") returned invalid value size %zu", name, value_size); + } + value_size += 1; + char* value = calloc(value_size, 1); + if (!value) { + cpuinfo_log_error("calloc %zu bytes failed", value_size); + return NULL; + } + if (sysctlbyname(name, value, &value_size, NULL, 0) != 0) { + cpuinfo_log_error("sysctlbyname(\"%s\") failed: %s", name, strerror(errno)); + free(value); + return NULL; + } + return value; +} + +struct cpuinfo_freebsd_topology cpuinfo_freebsd_detect_topology(void) { + struct cpuinfo_freebsd_topology topology = { + .packages = 0, + .cores = 0, + .threads_per_core = 0, + .threads = 0, + }; + char* topology_spec = sysctl_str("kern.sched.topology_spec"); + if (!topology_spec) { + return topology; + } + const char* group_tag = ""; + char* p = strstr(topology_spec, group_tag); + while (p) { + const char* cpu_tag = "cpu count=\""; + char* q = strstr(p, cpu_tag); + if (q) { + p = q + strlen(cpu_tag); + topology.packages += atoi(p); + } else { + break; + } + } + if (topology.packages == 0) { + const char* group_tag = " +#include #elif !defined(__EMSCRIPTEN__) || defined(__EMSCRIPTEN_PTHREADS__) - #include +#include #endif #include @@ -9,59 +9,59 @@ #include #ifdef __APPLE__ - #include "TargetConditionals.h" +#include "TargetConditionals.h" #endif - #if defined(_WIN32) || defined(__CYGWIN__) - static INIT_ONCE init_guard = INIT_ONCE_STATIC_INIT; +static INIT_ONCE init_guard = INIT_ONCE_STATIC_INIT; #elif !defined(__EMSCRIPTEN__) || defined(__EMSCRIPTEN_PTHREADS__) - static pthread_once_t init_guard = PTHREAD_ONCE_INIT; +static pthread_once_t init_guard = PTHREAD_ONCE_INIT; #else - static bool init_guard = false; +static bool init_guard = false; #endif bool CPUINFO_ABI cpuinfo_initialize(void) { #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - #if defined(__MACH__) && defined(__APPLE__) - pthread_once(&init_guard, &cpuinfo_x86_mach_init); - #elif defined(__linux__) - pthread_once(&init_guard, &cpuinfo_x86_linux_init); - #elif defined(_WIN32) || defined(__CYGWIN__) - InitOnceExecuteOnce(&init_guard, &cpuinfo_x86_windows_init, NULL, NULL); - #else - cpuinfo_log_error("operating system is not supported in cpuinfo"); - #endif +#if defined(__MACH__) && defined(__APPLE__) + pthread_once(&init_guard, &cpuinfo_x86_mach_init); +#elif defined(__FreeBSD__) + pthread_once(&init_guard, &cpuinfo_x86_freebsd_init); +#elif defined(__linux__) + pthread_once(&init_guard, &cpuinfo_x86_linux_init); +#elif defined(_WIN32) || defined(__CYGWIN__) + InitOnceExecuteOnce(&init_guard, &cpuinfo_x86_windows_init, NULL, NULL); +#else + cpuinfo_log_error("operating system is not supported in cpuinfo"); +#endif #elif CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - #if defined(__linux__) - pthread_once(&init_guard, &cpuinfo_arm_linux_init); - #elif defined(__MACH__) && defined(__APPLE__) - pthread_once(&init_guard, &cpuinfo_arm_mach_init); - #elif defined(_WIN32) - InitOnceExecuteOnce(&init_guard, &cpuinfo_arm_windows_init, NULL, NULL); - #else - cpuinfo_log_error("operating system is not supported in cpuinfo"); - #endif +#if defined(__linux__) + pthread_once(&init_guard, &cpuinfo_arm_linux_init); +#elif defined(__MACH__) && defined(__APPLE__) + pthread_once(&init_guard, &cpuinfo_arm_mach_init); +#elif defined(_WIN32) + InitOnceExecuteOnce(&init_guard, &cpuinfo_arm_windows_init, NULL, NULL); +#else + cpuinfo_log_error("operating system is not supported in cpuinfo"); +#endif #elif CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - #if defined(__linux__) - pthread_once(&init_guard, &cpuinfo_riscv_linux_init); - #else - cpuinfo_log_error("operating system is not supported in cpuinfo"); - #endif +#if defined(__linux__) + pthread_once(&init_guard, &cpuinfo_riscv_linux_init); +#else + cpuinfo_log_error("operating system is not supported in cpuinfo"); +#endif #elif CPUINFO_ARCH_ASMJS || CPUINFO_ARCH_WASM || CPUINFO_ARCH_WASMSIMD - #if defined(__EMSCRIPTEN_PTHREADS__) - pthread_once(&init_guard, &cpuinfo_emscripten_init); - #else - if (!init_guard) { - cpuinfo_emscripten_init(); - } - init_guard = true; - #endif +#if defined(__EMSCRIPTEN_PTHREADS__) + pthread_once(&init_guard, &cpuinfo_emscripten_init); +#else + if (!init_guard) { + cpuinfo_emscripten_init(); + } + init_guard = true; +#endif #else cpuinfo_log_error("processor architecture is not supported in cpuinfo"); #endif return cpuinfo_is_initialized; } -void CPUINFO_ABI cpuinfo_deinitialize(void) { -} +void CPUINFO_ABI cpuinfo_deinitialize(void) {} diff --git a/3rdparty/cpuinfo/src/linux/api.h b/3rdparty/cpuinfo/src/linux/api.h index d33cbd7dc7..0966bd5748 100644 --- a/3rdparty/cpuinfo/src/linux/api.h +++ b/3rdparty/cpuinfo/src/linux/api.h @@ -1,35 +1,45 @@ #pragma once #include -#include #include +#include #include #include - -#define CPUINFO_LINUX_FLAG_PRESENT UINT32_C(0x00000001) -#define CPUINFO_LINUX_FLAG_POSSIBLE UINT32_C(0x00000002) -#define CPUINFO_LINUX_FLAG_MAX_FREQUENCY UINT32_C(0x00000004) -#define CPUINFO_LINUX_FLAG_MIN_FREQUENCY UINT32_C(0x00000008) -#define CPUINFO_LINUX_FLAG_SMT_ID UINT32_C(0x00000010) -#define CPUINFO_LINUX_FLAG_CORE_ID UINT32_C(0x00000020) -#define CPUINFO_LINUX_FLAG_PACKAGE_ID UINT32_C(0x00000040) -#define CPUINFO_LINUX_FLAG_APIC_ID UINT32_C(0x00000080) -#define CPUINFO_LINUX_FLAG_SMT_CLUSTER UINT32_C(0x00000100) -#define CPUINFO_LINUX_FLAG_CORE_CLUSTER UINT32_C(0x00000200) -#define CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER UINT32_C(0x00000400) -#define CPUINFO_LINUX_FLAG_PROC_CPUINFO UINT32_C(0x00000800) -#define CPUINFO_LINUX_FLAG_VALID UINT32_C(0x00001000) -#define CPUINFO_LINUX_FLAG_CUR_FREQUENCY UINT32_C(0x00002000) -#define CPUINFO_LINUX_FLAG_CLUSTER_CLUSTER UINT32_C(0x00004000) +#define CPUINFO_LINUX_FLAG_PRESENT UINT32_C(0x00000001) +#define CPUINFO_LINUX_FLAG_POSSIBLE UINT32_C(0x00000002) +#define CPUINFO_LINUX_FLAG_MAX_FREQUENCY UINT32_C(0x00000004) +#define CPUINFO_LINUX_FLAG_MIN_FREQUENCY UINT32_C(0x00000008) +#define CPUINFO_LINUX_FLAG_SMT_ID UINT32_C(0x00000010) +#define CPUINFO_LINUX_FLAG_CORE_ID UINT32_C(0x00000020) +#define CPUINFO_LINUX_FLAG_PACKAGE_ID UINT32_C(0x00000040) +#define CPUINFO_LINUX_FLAG_APIC_ID UINT32_C(0x00000080) +#define CPUINFO_LINUX_FLAG_SMT_CLUSTER UINT32_C(0x00000100) +#define CPUINFO_LINUX_FLAG_CORE_CLUSTER UINT32_C(0x00000200) +#define CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER UINT32_C(0x00000400) +#define CPUINFO_LINUX_FLAG_PROC_CPUINFO UINT32_C(0x00000800) +#define CPUINFO_LINUX_FLAG_VALID UINT32_C(0x00001000) +#define CPUINFO_LINUX_FLAG_CUR_FREQUENCY UINT32_C(0x00002000) +#define CPUINFO_LINUX_FLAG_CLUSTER_CLUSTER UINT32_C(0x00004000) typedef bool (*cpuinfo_cpulist_callback)(uint32_t, uint32_t, void*); -CPUINFO_INTERNAL bool cpuinfo_linux_parse_cpulist(const char* filename, cpuinfo_cpulist_callback callback, void* context); -typedef bool (*cpuinfo_smallfile_callback)(const char*, const char*, void*); -CPUINFO_INTERNAL bool cpuinfo_linux_parse_small_file(const char* filename, size_t buffer_size, cpuinfo_smallfile_callback, void* context); +CPUINFO_INTERNAL bool cpuinfo_linux_parse_cpulist( + const char* filename, + cpuinfo_cpulist_callback callback, + void* context); +typedef bool (*cpuinfo_smallfile_callback)(const char*, const char*, const char*, void*); +CPUINFO_INTERNAL bool cpuinfo_linux_parse_small_file( + const char* filename, + size_t buffer_size, + cpuinfo_smallfile_callback, + void* context); typedef bool (*cpuinfo_line_callback)(const char*, const char*, void*, uint64_t); -CPUINFO_INTERNAL bool cpuinfo_linux_parse_multiline_file(const char* filename, size_t buffer_size, cpuinfo_line_callback, void* context); +CPUINFO_INTERNAL bool cpuinfo_linux_parse_multiline_file( + const char* filename, + size_t buffer_size, + cpuinfo_line_callback, + void* context); CPUINFO_INTERNAL uint32_t cpuinfo_linux_get_max_processors_count(void); CPUINFO_INTERNAL uint32_t cpuinfo_linux_get_max_possible_processor(uint32_t max_processors_count); @@ -37,13 +47,21 @@ CPUINFO_INTERNAL uint32_t cpuinfo_linux_get_max_present_processor(uint32_t max_p CPUINFO_INTERNAL uint32_t cpuinfo_linux_get_processor_cur_frequency(uint32_t processor); CPUINFO_INTERNAL uint32_t cpuinfo_linux_get_processor_min_frequency(uint32_t processor); CPUINFO_INTERNAL uint32_t cpuinfo_linux_get_processor_max_frequency(uint32_t processor); -CPUINFO_INTERNAL bool cpuinfo_linux_get_processor_package_id(uint32_t processor, uint32_t package_id[restrict static 1]); +CPUINFO_INTERNAL bool cpuinfo_linux_get_processor_package_id( + uint32_t processor, + uint32_t package_id[restrict static 1]); CPUINFO_INTERNAL bool cpuinfo_linux_get_processor_core_id(uint32_t processor, uint32_t core_id[restrict static 1]); -CPUINFO_INTERNAL bool cpuinfo_linux_detect_possible_processors(uint32_t max_processors_count, - uint32_t* processor0_flags, uint32_t processor_struct_size, uint32_t possible_flag); -CPUINFO_INTERNAL bool cpuinfo_linux_detect_present_processors(uint32_t max_processors_count, - uint32_t* processor0_flags, uint32_t processor_struct_size, uint32_t present_flag); +CPUINFO_INTERNAL bool cpuinfo_linux_detect_possible_processors( + uint32_t max_processors_count, + uint32_t* processor0_flags, + uint32_t processor_struct_size, + uint32_t possible_flag); +CPUINFO_INTERNAL bool cpuinfo_linux_detect_present_processors( + uint32_t max_processors_count, + uint32_t* processor0_flags, + uint32_t processor_struct_size, + uint32_t present_flag); typedef bool (*cpuinfo_siblings_callback)(uint32_t, uint32_t, uint32_t, void*); CPUINFO_INTERNAL bool cpuinfo_linux_detect_core_siblings( diff --git a/3rdparty/cpuinfo/src/linux/cpulist.c b/3rdparty/cpuinfo/src/linux/cpulist.c index 287198638c..f6c4c291b3 100644 --- a/3rdparty/cpuinfo/src/linux/cpulist.c +++ b/3rdparty/cpuinfo/src/linux/cpulist.c @@ -1,21 +1,20 @@ +#include #include #include #include #include -#include -#include -#include -#include #include #include +#include +#include +#include #if CPUINFO_MOCK - #include +#include #endif -#include #include - +#include /* * Size, in chars, of the on-stack buffer used for parsing cpu lists. @@ -25,7 +24,6 @@ */ #define BUFFER_SIZE 256 - /* Locale-independent */ inline static bool is_whitespace(char c) { switch (c) { @@ -42,7 +40,7 @@ inline static bool is_whitespace(char c) { inline static const char* parse_number(const char* string, const char* end, uint32_t number_ptr[restrict static 1]) { uint32_t number = 0; while (string != end) { - const uint32_t digit = (uint32_t) (*string) - (uint32_t) '0'; + const uint32_t digit = (uint32_t)(*string) - (uint32_t)'0'; if (digit >= 10) { break; } @@ -53,7 +51,11 @@ inline static const char* parse_number(const char* string, const char* end, uint return string; } -inline static bool parse_entry(const char* entry_start, const char* entry_end, cpuinfo_cpulist_callback callback, void* context) { +inline static bool parse_entry( + const char* entry_start, + const char* entry_end, + cpuinfo_cpulist_callback callback, + void* context) { /* Skip whitespace at the beginning of an entry */ for (; entry_start != entry_end; entry_start++) { if (!is_whitespace(*entry_start)) { @@ -67,36 +69,44 @@ inline static bool parse_entry(const char* entry_start, const char* entry_end, c } } - const size_t entry_length = (size_t) (entry_end - entry_start); + const size_t entry_length = (size_t)(entry_end - entry_start); if (entry_length == 0) { cpuinfo_log_warning("unexpected zero-length cpu list entry ignored"); return false; } - #if CPUINFO_LOG_DEBUG_PARSERS - cpuinfo_log_debug("parse cpu list entry \"%.*s\" (%zu chars)", (int) entry_length, entry_start, entry_length); - #endif +#if CPUINFO_LOG_DEBUG_PARSERS + cpuinfo_log_debug("parse cpu list entry \"%.*s\" (%zu chars)", (int)entry_length, entry_start, entry_length); +#endif uint32_t first_cpu, last_cpu; const char* number_end = parse_number(entry_start, entry_end, &first_cpu); if (number_end == entry_start) { /* Failed to parse the number; ignore the entry */ - cpuinfo_log_warning("invalid character '%c' in the cpu list entry \"%.*s\": entry is ignored", - entry_start[0], (int) entry_length, entry_start); + cpuinfo_log_warning( + "invalid character '%c' in the cpu list entry \"%.*s\": entry is ignored", + entry_start[0], + (int)entry_length, + entry_start); return false; } else if (number_end == entry_end) { - /* Completely parsed the entry */ - #if CPUINFO_LOG_DEBUG_PARSERS - cpuinfo_log_debug("cpulist: call callback with list_start = %"PRIu32", list_end = %"PRIu32, - first_cpu, first_cpu + 1); - #endif +/* Completely parsed the entry */ +#if CPUINFO_LOG_DEBUG_PARSERS + cpuinfo_log_debug( + "cpulist: call callback with list_start = %" PRIu32 ", list_end = %" PRIu32, + first_cpu, + first_cpu + 1); +#endif return callback(first_cpu, first_cpu + 1, context); } /* Parse the second part of the entry */ if (*number_end != '-') { - cpuinfo_log_warning("invalid character '%c' in the cpu list entry \"%.*s\": entry is ignored", - *number_end, (int) entry_length, entry_start); + cpuinfo_log_warning( + "invalid character '%c' in the cpu list entry \"%.*s\": entry is ignored", + *number_end, + (int)entry_length, + entry_start); return false; } @@ -104,28 +114,40 @@ inline static bool parse_entry(const char* entry_start, const char* entry_end, c number_end = parse_number(number_start, entry_end, &last_cpu); if (number_end == number_start) { /* Failed to parse the second number; ignore the entry */ - cpuinfo_log_warning("invalid character '%c' in the cpu list entry \"%.*s\": entry is ignored", - *number_start, (int) entry_length, entry_start); + cpuinfo_log_warning( + "invalid character '%c' in the cpu list entry \"%.*s\": entry is ignored", + *number_start, + (int)entry_length, + entry_start); return false; } if (number_end != entry_end) { - /* Partially parsed the entry; ignore unparsed characters and continue with the parsed part */ - cpuinfo_log_warning("ignored invalid characters \"%.*s\" at the end of cpu list entry \"%.*s\"", - (int) (entry_end - number_end), number_start, (int) entry_length, entry_start); + /* Partially parsed the entry; ignore unparsed characters and + * continue with the parsed part */ + cpuinfo_log_warning( + "ignored invalid characters \"%.*s\" at the end of cpu list entry \"%.*s\"", + (int)(entry_end - number_end), + number_start, + (int)entry_length, + entry_start); } if (last_cpu < first_cpu) { - cpuinfo_log_warning("ignored cpu list entry \"%.*s\": invalid range %"PRIu32"-%"PRIu32, - (int) entry_length, entry_start, first_cpu, last_cpu); + cpuinfo_log_warning( + "ignored cpu list entry \"%.*s\": invalid range %" PRIu32 "-%" PRIu32, + (int)entry_length, + entry_start, + first_cpu, + last_cpu); return false; } - /* Parsed both parts of the entry; update CPU set */ - #if CPUINFO_LOG_DEBUG_PARSERS - cpuinfo_log_debug("cpulist: call callback with list_start = %"PRIu32", list_end = %"PRIu32, - first_cpu, last_cpu + 1); - #endif +/* Parsed both parts of the entry; update CPU set */ +#if CPUINFO_LOG_DEBUG_PARSERS + cpuinfo_log_debug( + "cpulist: call callback with list_start = %" PRIu32 ", list_end = %" PRIu32, first_cpu, last_cpu + 1); +#endif return callback(first_cpu, last_cpu + 1, context); } @@ -133,9 +155,9 @@ bool cpuinfo_linux_parse_cpulist(const char* filename, cpuinfo_cpulist_callback bool status = true; int file = -1; char buffer[BUFFER_SIZE]; - #if CPUINFO_LOG_DEBUG_PARSERS - cpuinfo_log_debug("parsing cpu list from file %s", filename); - #endif +#if CPUINFO_LOG_DEBUG_PARSERS + cpuinfo_log_debug("parsing cpu list from file %s", filename); +#endif #if CPUINFO_MOCK file = cpuinfo_mock_open(filename, O_RDONLY); @@ -154,29 +176,32 @@ bool cpuinfo_linux_parse_cpulist(const char* filename, cpuinfo_cpulist_callback ssize_t bytes_read; do { #if CPUINFO_MOCK - bytes_read = cpuinfo_mock_read(file, data_start, (size_t) (buffer_end - data_start)); + bytes_read = cpuinfo_mock_read(file, data_start, (size_t)(buffer_end - data_start)); #else - bytes_read = read(file, data_start, (size_t) (buffer_end - data_start)); + bytes_read = read(file, data_start, (size_t)(buffer_end - data_start)); #endif if (bytes_read < 0) { - cpuinfo_log_info("failed to read file %s at position %zu: %s", filename, position, strerror(errno)); + cpuinfo_log_info( + "failed to read file %s at position %zu: %s", filename, position, strerror(errno)); status = false; goto cleanup; } - position += (size_t) bytes_read; - const char* data_end = data_start + (size_t) bytes_read; + position += (size_t)bytes_read; + const char* data_end = data_start + (size_t)bytes_read; const char* entry_start = buffer; if (bytes_read == 0) { - /* No more data in the file: process the remaining text in the buffer as a single entry */ + /* No more data in the file: process the remaining text + * in the buffer as a single entry */ const char* entry_end = data_end; const bool entry_status = parse_entry(entry_start, entry_end, callback, context); status &= entry_status; } else { const char* entry_end; do { - /* Find the end of the entry, as indicated by a comma (',') */ + /* Find the end of the entry, as indicated by a + * comma (',') */ for (entry_end = entry_start; entry_end != data_end; entry_end++) { if (*entry_end == ',') { break; @@ -184,18 +209,21 @@ bool cpuinfo_linux_parse_cpulist(const char* filename, cpuinfo_cpulist_callback } /* - * If we located separator at the end of the entry, parse it. - * Otherwise, there may be more data at the end; read the file once again. + * If we located separator at the end of the + * entry, parse it. Otherwise, there may be more + * data at the end; read the file once again. */ if (entry_end != data_end) { - const bool entry_status = parse_entry(entry_start, entry_end, callback, context); + const bool entry_status = + parse_entry(entry_start, entry_end, callback, context); status &= entry_status; entry_start = entry_end + 1; } } while (entry_end != data_end); - /* Move remaining partial entry data at the end to the beginning of the buffer */ - const size_t entry_length = (size_t) (entry_end - entry_start); + /* Move remaining partial entry data at the end to the + * beginning of the buffer */ + const size_t entry_length = (size_t)(entry_end - entry_start); memmove(buffer, entry_start, entry_length); data_start = &buffer[entry_length]; } diff --git a/3rdparty/cpuinfo/src/linux/mockfile.c b/3rdparty/cpuinfo/src/linux/mockfile.c index 138acfeb93..dd6ec339d8 100644 --- a/3rdparty/cpuinfo/src/linux/mockfile.c +++ b/3rdparty/cpuinfo/src/linux/mockfile.c @@ -1,30 +1,28 @@ +#include #include +#include #include #include -#include #include -#include -#include -#include -#include #include #include +#include +#include +#include #if !CPUINFO_MOCK - #error This file should be built only in mock mode +#error This file should be built only in mock mode #endif -#include #include #include +#include #include - static struct cpuinfo_mock_file* cpuinfo_mock_files = NULL; static uint32_t cpuinfo_mock_file_count = 0; - void CPUINFO_ABI cpuinfo_mock_filesystem(struct cpuinfo_mock_file* files) { cpuinfo_log_info("filesystem mocking enabled"); uint32_t file_count = 0; @@ -54,7 +52,7 @@ int CPUINFO_ABI cpuinfo_mock_open(const char* path, int oflag) { return -1; } cpuinfo_mock_files[i].offset = 0; - return (int) i; + return (int)i; } } errno = ENOENT; @@ -67,7 +65,7 @@ int CPUINFO_ABI cpuinfo_mock_close(int fd) { return close(fd); } - if ((unsigned int) fd >= cpuinfo_mock_file_count) { + if ((unsigned int)fd >= cpuinfo_mock_file_count) { errno = EBADF; return -1; } @@ -85,7 +83,7 @@ ssize_t CPUINFO_ABI cpuinfo_mock_read(int fd, void* buffer, size_t capacity) { return read(fd, buffer, capacity); } - if ((unsigned int) fd >= cpuinfo_mock_file_count) { + if ((unsigned int)fd >= cpuinfo_mock_file_count) { errno = EBADF; return -1; } @@ -99,7 +97,7 @@ ssize_t CPUINFO_ABI cpuinfo_mock_read(int fd, void* buffer, size_t capacity) { if (count > capacity) { count = capacity; } - memcpy(buffer, (void*) cpuinfo_mock_files[fd].content + offset, count); + memcpy(buffer, (void*)cpuinfo_mock_files[fd].content + offset, count); cpuinfo_mock_files[fd].offset += count; - return (ssize_t) count; + return (ssize_t)count; } diff --git a/3rdparty/cpuinfo/src/linux/multiline.c b/3rdparty/cpuinfo/src/linux/multiline.c index 1feeb9b1c5..00f4583ddc 100644 --- a/3rdparty/cpuinfo/src/linux/multiline.c +++ b/3rdparty/cpuinfo/src/linux/multiline.c @@ -1,27 +1,29 @@ +#include +#include #include #include #include #include -#include -#include -#include -#include -#include #include +#include +#include +#include #if CPUINFO_MOCK - #include +#include #endif -#include #include +#include - -bool cpuinfo_linux_parse_multiline_file(const char* filename, size_t buffer_size, cpuinfo_line_callback callback, void* context) -{ +bool cpuinfo_linux_parse_multiline_file( + const char* filename, + size_t buffer_size, + cpuinfo_line_callback callback, + void* context) { int file = -1; bool status = false; - char* buffer = (char*) alloca(buffer_size); + char* buffer = (char*)alloca(buffer_size); #if CPUINFO_MOCK file = cpuinfo_mock_open(filename, O_RDONLY); @@ -41,22 +43,23 @@ bool cpuinfo_linux_parse_multiline_file(const char* filename, size_t buffer_size ssize_t bytes_read; do { #if CPUINFO_MOCK - bytes_read = cpuinfo_mock_read(file, data_start, (size_t) (buffer_end - data_start)); + bytes_read = cpuinfo_mock_read(file, data_start, (size_t)(buffer_end - data_start)); #else - bytes_read = read(file, data_start, (size_t) (buffer_end - data_start)); + bytes_read = read(file, data_start, (size_t)(buffer_end - data_start)); #endif if (bytes_read < 0) { - cpuinfo_log_info("failed to read file %s at position %zu: %s", - filename, position, strerror(errno)); + cpuinfo_log_info( + "failed to read file %s at position %zu: %s", filename, position, strerror(errno)); goto cleanup; } - position += (size_t) bytes_read; - const char* data_end = data_start + (size_t) bytes_read; + position += (size_t)bytes_read; + const char* data_end = data_start + (size_t)bytes_read; const char* line_start = buffer; if (bytes_read == 0) { - /* No more data in the file: process the remaining text in the buffer as a single entry */ + /* No more data in the file: process the remaining text + * in the buffer as a single entry */ const char* line_end = data_end; if (!callback(line_start, line_end, context, line_number)) { goto cleanup; @@ -64,7 +67,9 @@ bool cpuinfo_linux_parse_multiline_file(const char* filename, size_t buffer_size } else { const char* line_end; do { - /* Find the end of the entry, as indicated by newline character ('\n') */ + /* Find the end of the entry, as indicated by + * newline character ('\n') + */ for (line_end = line_start; line_end != data_end; line_end++) { if (*line_end == '\n') { break; @@ -72,8 +77,9 @@ bool cpuinfo_linux_parse_multiline_file(const char* filename, size_t buffer_size } /* - * If we located separator at the end of the entry, parse it. - * Otherwise, there may be more data at the end; read the file once again. + * If we located separator at the end of the + * entry, parse it. Otherwise, there may be more + * data at the end; read the file once again. */ if (line_end != data_end) { if (!callback(line_start, line_end, context, line_number++)) { @@ -83,8 +89,9 @@ bool cpuinfo_linux_parse_multiline_file(const char* filename, size_t buffer_size } } while (line_end != data_end); - /* Move remaining partial line data at the end to the beginning of the buffer */ - const size_t line_length = (size_t) (line_end - line_start); + /* Move remaining partial line data at the end to the + * beginning of the buffer */ + const size_t line_length = (size_t)(line_end - line_start); memmove(buffer, line_start, line_length); data_start = &buffer[line_length]; } diff --git a/3rdparty/cpuinfo/src/linux/processors.c b/3rdparty/cpuinfo/src/linux/processors.c index 246b4a2eed..b68cd1ccd9 100644 --- a/3rdparty/cpuinfo/src/linux/processors.c +++ b/3rdparty/cpuinfo/src/linux/processors.c @@ -1,31 +1,32 @@ #include #include -#include #include +#include #include #if !defined(__ANDROID__) - /* - * sched.h is only used for CPU_SETSIZE constant. - * Android NDK headers before platform 21 do have this constant in sched.h - */ - #include +/* + * sched.h is only used for CPU_SETSIZE constant. + * Android NDK headers before platform 21 do have this constant in sched.h + */ +#include #endif -#include #include - +#include #define STRINGIFY(token) #token #define KERNEL_MAX_FILENAME "/sys/devices/system/cpu/kernel_max" #define KERNEL_MAX_FILESIZE 32 -#define FREQUENCY_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/cpufreq/cpuinfo_max_freq")) +#define FREQUENCY_FILENAME_SIZE \ + (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/cpufreq/cpuinfo_max_freq")) #define CUR_FREQUENCY_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/cpufreq/cpuinfo_cur_freq" #define MAX_FREQUENCY_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/cpufreq/cpuinfo_max_freq" #define MIN_FREQUENCY_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/cpufreq/cpuinfo_min_freq" #define FREQUENCY_FILESIZE 32 -#define PACKAGE_ID_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/physical_package_id")) +#define PACKAGE_ID_FILENAME_SIZE \ + (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/physical_package_id")) #define PACKAGE_ID_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/topology/physical_package_id" #define PACKAGE_ID_FILESIZE 32 #define CORE_ID_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/core_id")) @@ -34,24 +35,27 @@ #define CORE_CPUS_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/core_cpus_list")) #define CORE_CPUS_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/topology/core_cpus_list" -#define CORE_SIBLINGS_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/core_siblings_list")) +#define CORE_SIBLINGS_FILENAME_SIZE \ + (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/core_siblings_list")) #define CORE_SIBLINGS_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/topology/core_siblings_list" -#define CLUSTER_CPUS_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/cluster_cpus_list")) +#define CLUSTER_CPUS_FILENAME_SIZE \ + (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/cluster_cpus_list")) #define CLUSTER_CPUS_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/topology/cluster_cpus_list" -#define PACKAGE_CPUS_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/package_cpus_list")) +#define PACKAGE_CPUS_FILENAME_SIZE \ + (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/package_cpus_list")) #define PACKAGE_CPUS_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/topology/package_cpus_list" -#define THREAD_SIBLINGS_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/thread_siblings_list")) +#define THREAD_SIBLINGS_FILENAME_SIZE \ + (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/thread_siblings_list")) #define THREAD_SIBLINGS_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/topology/thread_siblings_list" #define POSSIBLE_CPULIST_FILENAME "/sys/devices/system/cpu/possible" #define PRESENT_CPULIST_FILENAME "/sys/devices/system/cpu/present" - inline static const char* parse_number(const char* start, const char* end, uint32_t number_ptr[restrict static 1]) { uint32_t number = 0; const char* parsed = start; for (; parsed != end; parsed++) { - const uint32_t digit = (uint32_t) (uint8_t) (*parsed) - (uint32_t) '0'; + const uint32_t digit = (uint32_t)(uint8_t)(*parsed) - (uint32_t)'0'; if (digit >= 10) { break; } @@ -75,20 +79,20 @@ inline static bool is_whitespace(char c) { } #if defined(__ANDROID__) && !defined(CPU_SETSIZE) - /* - * Android NDK headers before platform 21 do not define CPU_SETSIZE, - * so we hard-code its value, as defined in platform 21 headers - */ - #if defined(__LP64__) - static const uint32_t default_max_processors_count = 1024; - #else - static const uint32_t default_max_processors_count = 32; - #endif +/* + * Android NDK headers before platform 21 do not define CPU_SETSIZE, + * so we hard-code its value, as defined in platform 21 headers + */ +#if defined(__LP64__) +static const uint32_t default_max_processors_count = 1024; #else - static const uint32_t default_max_processors_count = CPU_SETSIZE; +static const uint32_t default_max_processors_count = 32; +#endif +#else +static const uint32_t default_max_processors_count = CPU_SETSIZE; #endif -static bool uint32_parser(const char* text_start, const char* text_end, void* context) { +static bool uint32_parser(const char* filename, const char* text_start, const char* text_end, void* context) { if (text_start == text_end) { cpuinfo_log_error("failed to parse file %s: file is empty", KERNEL_MAX_FILENAME); return false; @@ -97,20 +101,26 @@ static bool uint32_parser(const char* text_start, const char* text_end, void* co uint32_t kernel_max = 0; const char* parsed_end = parse_number(text_start, text_end, &kernel_max); if (parsed_end == text_start) { - cpuinfo_log_error("failed to parse file %s: \"%.*s\" is not an unsigned number", - KERNEL_MAX_FILENAME, (int) (text_end - text_start), text_start); + cpuinfo_log_error( + "failed to parse file %s: \"%.*s\" is not an unsigned number", + filename, + (int)(text_end - text_start), + text_start); return false; } else { for (const char* char_ptr = parsed_end; char_ptr != text_end; char_ptr++) { if (!is_whitespace(*char_ptr)) { - cpuinfo_log_warning("non-whitespace characters \"%.*s\" following number in file %s are ignored", - (int) (text_end - char_ptr), char_ptr, KERNEL_MAX_FILENAME); + cpuinfo_log_warning( + "non-whitespace characters \"%.*s\" following number in file %s are ignored", + (int)(text_end - char_ptr), + char_ptr, + filename); break; } } } - uint32_t* kernel_max_ptr = (uint32_t*) context; + uint32_t* kernel_max_ptr = (uint32_t*)context; *kernel_max_ptr = kernel_max; return true; } @@ -118,133 +128,160 @@ static bool uint32_parser(const char* text_start, const char* text_end, void* co uint32_t cpuinfo_linux_get_max_processors_count(void) { uint32_t kernel_max; if (cpuinfo_linux_parse_small_file(KERNEL_MAX_FILENAME, KERNEL_MAX_FILESIZE, uint32_parser, &kernel_max)) { - cpuinfo_log_debug("parsed kernel_max value of %"PRIu32" from %s", kernel_max, KERNEL_MAX_FILENAME); + cpuinfo_log_debug("parsed kernel_max value of %" PRIu32 " from %s", kernel_max, KERNEL_MAX_FILENAME); if (kernel_max >= default_max_processors_count) { - cpuinfo_log_warning("kernel_max value of %"PRIu32" parsed from %s exceeds platform-default limit %"PRIu32, - kernel_max, KERNEL_MAX_FILENAME, default_max_processors_count - 1); + cpuinfo_log_warning( + "kernel_max value of %" PRIu32 + " parsed from %s exceeds platform-default limit %" PRIu32, + kernel_max, + KERNEL_MAX_FILENAME, + default_max_processors_count - 1); } return kernel_max + 1; } else { - cpuinfo_log_warning("using platform-default max processors count = %"PRIu32, default_max_processors_count); + cpuinfo_log_warning( + "using platform-default max processors count = %" PRIu32, default_max_processors_count); return default_max_processors_count; } } uint32_t cpuinfo_linux_get_processor_cur_frequency(uint32_t processor) { char cur_frequency_filename[FREQUENCY_FILENAME_SIZE]; - const int chars_formatted = snprintf( - cur_frequency_filename, FREQUENCY_FILENAME_SIZE, CUR_FREQUENCY_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= FREQUENCY_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for current frequency of processor %"PRIu32, processor); + const int chars_formatted = + snprintf(cur_frequency_filename, FREQUENCY_FILENAME_SIZE, CUR_FREQUENCY_FILENAME_FORMAT, processor); + if ((unsigned int)chars_formatted >= FREQUENCY_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for current frequency of processor %" PRIu32, processor); return 0; } uint32_t cur_frequency; if (cpuinfo_linux_parse_small_file(cur_frequency_filename, FREQUENCY_FILESIZE, uint32_parser, &cur_frequency)) { - cpuinfo_log_debug("parsed currrent frequency value of %"PRIu32" KHz for logical processor %"PRIu32" from %s", - cur_frequency, processor, cur_frequency_filename); + cpuinfo_log_debug( + "parsed currrent frequency value of %" PRIu32 " KHz for logical processor %" PRIu32 " from %s", + cur_frequency, + processor, + cur_frequency_filename); return cur_frequency; } else { - cpuinfo_log_warning("failed to parse current frequency for processor %"PRIu32" from %s", - processor, cur_frequency_filename); + cpuinfo_log_warning( + "failed to parse current frequency for processor %" PRIu32 " from %s", + processor, + cur_frequency_filename); return 0; } } uint32_t cpuinfo_linux_get_processor_max_frequency(uint32_t processor) { char max_frequency_filename[FREQUENCY_FILENAME_SIZE]; - const int chars_formatted = snprintf( - max_frequency_filename, FREQUENCY_FILENAME_SIZE, MAX_FREQUENCY_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= FREQUENCY_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for max frequency of processor %"PRIu32, processor); + const int chars_formatted = + snprintf(max_frequency_filename, FREQUENCY_FILENAME_SIZE, MAX_FREQUENCY_FILENAME_FORMAT, processor); + if ((unsigned int)chars_formatted >= FREQUENCY_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for max frequency of processor %" PRIu32, processor); return 0; } uint32_t max_frequency; if (cpuinfo_linux_parse_small_file(max_frequency_filename, FREQUENCY_FILESIZE, uint32_parser, &max_frequency)) { - cpuinfo_log_debug("parsed max frequency value of %"PRIu32" KHz for logical processor %"PRIu32" from %s", - max_frequency, processor, max_frequency_filename); + cpuinfo_log_debug( + "parsed max frequency value of %" PRIu32 " KHz for logical processor %" PRIu32 " from %s", + max_frequency, + processor, + max_frequency_filename); return max_frequency; } else { - cpuinfo_log_warning("failed to parse max frequency for processor %"PRIu32" from %s", - processor, max_frequency_filename); + cpuinfo_log_warning( + "failed to parse max frequency for processor %" PRIu32 " from %s", + processor, + max_frequency_filename); return 0; } } uint32_t cpuinfo_linux_get_processor_min_frequency(uint32_t processor) { char min_frequency_filename[FREQUENCY_FILENAME_SIZE]; - const int chars_formatted = snprintf( - min_frequency_filename, FREQUENCY_FILENAME_SIZE, MIN_FREQUENCY_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= FREQUENCY_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for min frequency of processor %"PRIu32, processor); + const int chars_formatted = + snprintf(min_frequency_filename, FREQUENCY_FILENAME_SIZE, MIN_FREQUENCY_FILENAME_FORMAT, processor); + if ((unsigned int)chars_formatted >= FREQUENCY_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for min frequency of processor %" PRIu32, processor); return 0; } uint32_t min_frequency; if (cpuinfo_linux_parse_small_file(min_frequency_filename, FREQUENCY_FILESIZE, uint32_parser, &min_frequency)) { - cpuinfo_log_debug("parsed min frequency value of %"PRIu32" KHz for logical processor %"PRIu32" from %s", - min_frequency, processor, min_frequency_filename); + cpuinfo_log_debug( + "parsed min frequency value of %" PRIu32 " KHz for logical processor %" PRIu32 " from %s", + min_frequency, + processor, + min_frequency_filename); return min_frequency; } else { /* - * This error is less severe than parsing max frequency, because min frequency is only useful for clustering, - * while max frequency is also needed for peak FLOPS calculation. + * This error is less severe than parsing max frequency, because + * min frequency is only useful for clustering, while max + * frequency is also needed for peak FLOPS calculation. */ - cpuinfo_log_info("failed to parse min frequency for processor %"PRIu32" from %s", - processor, min_frequency_filename); + cpuinfo_log_info( + "failed to parse min frequency for processor %" PRIu32 " from %s", + processor, + min_frequency_filename); return 0; } } bool cpuinfo_linux_get_processor_core_id(uint32_t processor, uint32_t core_id_ptr[restrict static 1]) { char core_id_filename[PACKAGE_ID_FILENAME_SIZE]; - const int chars_formatted = snprintf( - core_id_filename, CORE_ID_FILENAME_SIZE, CORE_ID_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= CORE_ID_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for core id of processor %"PRIu32, processor); + const int chars_formatted = + snprintf(core_id_filename, CORE_ID_FILENAME_SIZE, CORE_ID_FILENAME_FORMAT, processor); + if ((unsigned int)chars_formatted >= CORE_ID_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for core id of processor %" PRIu32, processor); return 0; } uint32_t core_id; if (cpuinfo_linux_parse_small_file(core_id_filename, CORE_ID_FILESIZE, uint32_parser, &core_id)) { - cpuinfo_log_debug("parsed core id value of %"PRIu32" for logical processor %"PRIu32" from %s", - core_id, processor, core_id_filename); + cpuinfo_log_debug( + "parsed core id value of %" PRIu32 " for logical processor %" PRIu32 " from %s", + core_id, + processor, + core_id_filename); *core_id_ptr = core_id; return true; } else { - cpuinfo_log_info("failed to parse core id for processor %"PRIu32" from %s", - processor, core_id_filename); + cpuinfo_log_info( + "failed to parse core id for processor %" PRIu32 " from %s", processor, core_id_filename); return false; } } bool cpuinfo_linux_get_processor_package_id(uint32_t processor, uint32_t package_id_ptr[restrict static 1]) { char package_id_filename[PACKAGE_ID_FILENAME_SIZE]; - const int chars_formatted = snprintf( - package_id_filename, PACKAGE_ID_FILENAME_SIZE, PACKAGE_ID_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= PACKAGE_ID_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for package id of processor %"PRIu32, processor); + const int chars_formatted = + snprintf(package_id_filename, PACKAGE_ID_FILENAME_SIZE, PACKAGE_ID_FILENAME_FORMAT, processor); + if ((unsigned int)chars_formatted >= PACKAGE_ID_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for package id of processor %" PRIu32, processor); return 0; } uint32_t package_id; if (cpuinfo_linux_parse_small_file(package_id_filename, PACKAGE_ID_FILESIZE, uint32_parser, &package_id)) { - cpuinfo_log_debug("parsed package id value of %"PRIu32" for logical processor %"PRIu32" from %s", - package_id, processor, package_id_filename); + cpuinfo_log_debug( + "parsed package id value of %" PRIu32 " for logical processor %" PRIu32 " from %s", + package_id, + processor, + package_id_filename); *package_id_ptr = package_id; return true; } else { - cpuinfo_log_info("failed to parse package id for processor %"PRIu32" from %s", - processor, package_id_filename); + cpuinfo_log_info( + "failed to parse package id for processor %" PRIu32 " from %s", processor, package_id_filename); return false; } } static bool max_processor_number_parser(uint32_t processor_list_start, uint32_t processor_list_end, void* context) { - uint32_t* processor_number_ptr = (uint32_t*) context; + uint32_t* processor_number_ptr = (uint32_t*)context; const uint32_t processor_list_last = processor_list_end - 1; if (*processor_number_ptr < processor_list_last) { *processor_number_ptr = processor_list_last; @@ -254,18 +291,21 @@ static bool max_processor_number_parser(uint32_t processor_list_start, uint32_t uint32_t cpuinfo_linux_get_max_possible_processor(uint32_t max_processors_count) { uint32_t max_possible_processor = 0; - if (!cpuinfo_linux_parse_cpulist(POSSIBLE_CPULIST_FILENAME, max_processor_number_parser, &max_possible_processor)) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - cpuinfo_log_error("failed to parse the list of possible processors in %s", POSSIBLE_CPULIST_FILENAME); - #else - cpuinfo_log_warning("failed to parse the list of possible processors in %s", POSSIBLE_CPULIST_FILENAME); - #endif + if (!cpuinfo_linux_parse_cpulist( + POSSIBLE_CPULIST_FILENAME, max_processor_number_parser, &max_possible_processor)) { +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + cpuinfo_log_error("failed to parse the list of possible processors in %s", POSSIBLE_CPULIST_FILENAME); +#else + cpuinfo_log_warning("failed to parse the list of possible processors in %s", POSSIBLE_CPULIST_FILENAME); +#endif return UINT32_MAX; } if (max_possible_processor >= max_processors_count) { cpuinfo_log_warning( - "maximum possible processor number %"PRIu32" exceeds system limit %"PRIu32": truncating to the latter", - max_possible_processor, max_processors_count - 1); + "maximum possible processor number %" PRIu32 " exceeds system limit %" PRIu32 + ": truncating to the latter", + max_possible_processor, + max_processors_count - 1); max_possible_processor = max_processors_count - 1; } return max_possible_processor; @@ -273,18 +313,21 @@ uint32_t cpuinfo_linux_get_max_possible_processor(uint32_t max_processors_count) uint32_t cpuinfo_linux_get_max_present_processor(uint32_t max_processors_count) { uint32_t max_present_processor = 0; - if (!cpuinfo_linux_parse_cpulist(PRESENT_CPULIST_FILENAME, max_processor_number_parser, &max_present_processor)) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - cpuinfo_log_error("failed to parse the list of present processors in %s", PRESENT_CPULIST_FILENAME); - #else - cpuinfo_log_warning("failed to parse the list of present processors in %s", PRESENT_CPULIST_FILENAME); - #endif + if (!cpuinfo_linux_parse_cpulist( + PRESENT_CPULIST_FILENAME, max_processor_number_parser, &max_present_processor)) { +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + cpuinfo_log_error("failed to parse the list of present processors in %s", PRESENT_CPULIST_FILENAME); +#else + cpuinfo_log_warning("failed to parse the list of present processors in %s", PRESENT_CPULIST_FILENAME); +#endif return UINT32_MAX; } if (max_present_processor >= max_processors_count) { cpuinfo_log_warning( - "maximum present processor number %"PRIu32" exceeds system limit %"PRIu32": truncating to the latter", - max_present_processor, max_processors_count - 1); + "maximum present processor number %" PRIu32 " exceeds system limit %" PRIu32 + ": truncating to the latter", + max_present_processor, + max_processors_count - 1); max_present_processor = max_processors_count - 1; } return max_present_processor; @@ -298,22 +341,25 @@ struct detect_processors_context { }; static bool detect_processor_parser(uint32_t processor_list_start, uint32_t processor_list_end, void* context) { - const uint32_t max_processors_count = ((struct detect_processors_context*) context)->max_processors_count; - const uint32_t* processor0_flags = ((struct detect_processors_context*) context)->processor0_flags; - const uint32_t processor_struct_size = ((struct detect_processors_context*) context)->processor_struct_size; - const uint32_t detected_flag = ((struct detect_processors_context*) context)->detected_flag; + const uint32_t max_processors_count = ((struct detect_processors_context*)context)->max_processors_count; + const uint32_t* processor0_flags = ((struct detect_processors_context*)context)->processor0_flags; + const uint32_t processor_struct_size = ((struct detect_processors_context*)context)->processor_struct_size; + const uint32_t detected_flag = ((struct detect_processors_context*)context)->detected_flag; for (uint32_t processor = processor_list_start; processor < processor_list_end; processor++) { if (processor >= max_processors_count) { break; } - *((uint32_t*) ((uintptr_t) processor0_flags + processor_struct_size * processor)) |= detected_flag; + *((uint32_t*)((uintptr_t)processor0_flags + processor_struct_size * processor)) |= detected_flag; } return true; } -bool cpuinfo_linux_detect_possible_processors(uint32_t max_processors_count, - uint32_t* processor0_flags, uint32_t processor_struct_size, uint32_t possible_flag) { +bool cpuinfo_linux_detect_possible_processors( + uint32_t max_processors_count, + uint32_t* processor0_flags, + uint32_t processor_struct_size, + uint32_t possible_flag) { struct detect_processors_context context = { .max_processors_count = max_processors_count, .processor0_flags = processor0_flags, @@ -328,8 +374,11 @@ bool cpuinfo_linux_detect_possible_processors(uint32_t max_processors_count, } } -bool cpuinfo_linux_detect_present_processors(uint32_t max_processors_count, - uint32_t* processor0_flags, uint32_t processor_struct_size, uint32_t present_flag) { +bool cpuinfo_linux_detect_present_processors( + uint32_t max_processors_count, + uint32_t* processor0_flags, + uint32_t processor_struct_size, + uint32_t present_flag) { struct detect_processors_context context = { .max_processors_count = max_processors_count, .processor0_flags = processor0_flags, @@ -353,13 +402,17 @@ struct siblings_context { }; static bool siblings_parser(uint32_t sibling_list_start, uint32_t sibling_list_end, struct siblings_context* context) { - const char* group_name = context->group_name; - const uint32_t max_processors_count = context->max_processors_count; - const uint32_t processor = context->processor; + const char* group_name = context->group_name; + const uint32_t max_processors_count = context->max_processors_count; + const uint32_t processor = context->processor; if (sibling_list_end > max_processors_count) { - cpuinfo_log_warning("ignore %s siblings %"PRIu32"-%"PRIu32" of processor %"PRIu32, - group_name, max_processors_count, sibling_list_end - 1, processor); + cpuinfo_log_warning( + "ignore %s siblings %" PRIu32 "-%" PRIu32 " of processor %" PRIu32, + group_name, + max_processors_count, + sibling_list_end - 1, + processor); sibling_list_end = max_processors_count; } @@ -372,10 +425,10 @@ bool cpuinfo_linux_detect_core_cpus( cpuinfo_siblings_callback callback, void* context) { char core_cpus_filename[CORE_CPUS_FILENAME_SIZE]; - const int chars_formatted = snprintf( - core_cpus_filename, CORE_CPUS_FILENAME_SIZE, CORE_CPUS_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= CORE_CPUS_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for core cpus of processor %"PRIu32, processor); + const int chars_formatted = + snprintf(core_cpus_filename, CORE_CPUS_FILENAME_SIZE, CORE_CPUS_FILENAME_FORMAT, processor); + if ((unsigned int)chars_formatted >= CORE_CPUS_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for core cpus of processor %" PRIu32, processor); return false; } @@ -386,12 +439,14 @@ bool cpuinfo_linux_detect_core_cpus( .callback = callback, .callback_context = context, }; - if (cpuinfo_linux_parse_cpulist(core_cpus_filename, - (cpuinfo_cpulist_callback) siblings_parser, &siblings_context)) { + if (cpuinfo_linux_parse_cpulist( + core_cpus_filename, (cpuinfo_cpulist_callback)siblings_parser, &siblings_context)) { return true; } else { - cpuinfo_log_info("failed to parse the list of core cpus for processor %"PRIu32" from %s", - processor, core_cpus_filename); + cpuinfo_log_info( + "failed to parse the list of core cpus for processor %" PRIu32 " from %s", + processor, + core_cpus_filename); return false; } } @@ -402,10 +457,10 @@ bool cpuinfo_linux_detect_core_siblings( cpuinfo_siblings_callback callback, void* context) { char core_siblings_filename[CORE_SIBLINGS_FILENAME_SIZE]; - const int chars_formatted = snprintf( - core_siblings_filename, CORE_SIBLINGS_FILENAME_SIZE, CORE_SIBLINGS_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= CORE_SIBLINGS_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for core siblings of processor %"PRIu32, processor); + const int chars_formatted = + snprintf(core_siblings_filename, CORE_SIBLINGS_FILENAME_SIZE, CORE_SIBLINGS_FILENAME_FORMAT, processor); + if ((unsigned int)chars_formatted >= CORE_SIBLINGS_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for core siblings of processor %" PRIu32, processor); return false; } @@ -416,12 +471,14 @@ bool cpuinfo_linux_detect_core_siblings( .callback = callback, .callback_context = context, }; - if (cpuinfo_linux_parse_cpulist(core_siblings_filename, - (cpuinfo_cpulist_callback) siblings_parser, &siblings_context)) { + if (cpuinfo_linux_parse_cpulist( + core_siblings_filename, (cpuinfo_cpulist_callback)siblings_parser, &siblings_context)) { return true; } else { - cpuinfo_log_info("failed to parse the list of core siblings for processor %"PRIu32" from %s", - processor, core_siblings_filename); + cpuinfo_log_info( + "failed to parse the list of core siblings for processor %" PRIu32 " from %s", + processor, + core_siblings_filename); return false; } } @@ -434,8 +491,8 @@ bool cpuinfo_linux_detect_thread_siblings( char thread_siblings_filename[THREAD_SIBLINGS_FILENAME_SIZE]; const int chars_formatted = snprintf( thread_siblings_filename, THREAD_SIBLINGS_FILENAME_SIZE, THREAD_SIBLINGS_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= THREAD_SIBLINGS_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for thread siblings of processor %"PRIu32, processor); + if ((unsigned int)chars_formatted >= THREAD_SIBLINGS_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for thread siblings of processor %" PRIu32, processor); return false; } @@ -446,12 +503,14 @@ bool cpuinfo_linux_detect_thread_siblings( .callback = callback, .callback_context = context, }; - if (cpuinfo_linux_parse_cpulist(thread_siblings_filename, - (cpuinfo_cpulist_callback) siblings_parser, &siblings_context)) { + if (cpuinfo_linux_parse_cpulist( + thread_siblings_filename, (cpuinfo_cpulist_callback)siblings_parser, &siblings_context)) { return true; } else { - cpuinfo_log_info("failed to parse the list of thread siblings for processor %"PRIu32" from %s", - processor, thread_siblings_filename); + cpuinfo_log_info( + "failed to parse the list of thread siblings for processor %" PRIu32 " from %s", + processor, + thread_siblings_filename); return false; } } @@ -462,10 +521,10 @@ bool cpuinfo_linux_detect_cluster_cpus( cpuinfo_siblings_callback callback, void* context) { char cluster_cpus_filename[CLUSTER_CPUS_FILENAME_SIZE]; - const int chars_formatted = snprintf( - cluster_cpus_filename, CLUSTER_CPUS_FILENAME_SIZE, CLUSTER_CPUS_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= CLUSTER_CPUS_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for cluster cpus of processor %"PRIu32, processor); + const int chars_formatted = + snprintf(cluster_cpus_filename, CLUSTER_CPUS_FILENAME_SIZE, CLUSTER_CPUS_FILENAME_FORMAT, processor); + if ((unsigned int)chars_formatted >= CLUSTER_CPUS_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for cluster cpus of processor %" PRIu32, processor); return false; } @@ -476,12 +535,14 @@ bool cpuinfo_linux_detect_cluster_cpus( .callback = callback, .callback_context = context, }; - if (cpuinfo_linux_parse_cpulist(cluster_cpus_filename, - (cpuinfo_cpulist_callback) siblings_parser, &siblings_context)) { + if (cpuinfo_linux_parse_cpulist( + cluster_cpus_filename, (cpuinfo_cpulist_callback)siblings_parser, &siblings_context)) { return true; } else { - cpuinfo_log_info("failed to parse the list of cluster cpus for processor %"PRIu32" from %s", - processor, cluster_cpus_filename); + cpuinfo_log_info( + "failed to parse the list of cluster cpus for processor %" PRIu32 " from %s", + processor, + cluster_cpus_filename); return false; } } @@ -492,10 +553,10 @@ bool cpuinfo_linux_detect_package_cpus( cpuinfo_siblings_callback callback, void* context) { char package_cpus_filename[PACKAGE_CPUS_FILENAME_SIZE]; - const int chars_formatted = snprintf( - package_cpus_filename, PACKAGE_CPUS_FILENAME_SIZE, PACKAGE_CPUS_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= PACKAGE_CPUS_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for package cpus of processor %"PRIu32, processor); + const int chars_formatted = + snprintf(package_cpus_filename, PACKAGE_CPUS_FILENAME_SIZE, PACKAGE_CPUS_FILENAME_FORMAT, processor); + if ((unsigned int)chars_formatted >= PACKAGE_CPUS_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for package cpus of processor %" PRIu32, processor); return false; } @@ -506,12 +567,14 @@ bool cpuinfo_linux_detect_package_cpus( .callback = callback, .callback_context = context, }; - if (cpuinfo_linux_parse_cpulist(package_cpus_filename, - (cpuinfo_cpulist_callback) siblings_parser, &siblings_context)) { + if (cpuinfo_linux_parse_cpulist( + package_cpus_filename, (cpuinfo_cpulist_callback)siblings_parser, &siblings_context)) { return true; } else { - cpuinfo_log_info("failed to parse the list of package cpus for processor %"PRIu32" from %s", - processor, package_cpus_filename); + cpuinfo_log_info( + "failed to parse the list of package cpus for processor %" PRIu32 " from %s", + processor, + package_cpus_filename); return false; } } diff --git a/3rdparty/cpuinfo/src/linux/smallfile.c b/3rdparty/cpuinfo/src/linux/smallfile.c index 98cde00e54..6127c4e18b 100644 --- a/3rdparty/cpuinfo/src/linux/smallfile.c +++ b/3rdparty/cpuinfo/src/linux/smallfile.c @@ -1,30 +1,33 @@ +#include +#include #include #include #include #include -#include -#include -#include -#include -#include #include +#include +#include +#include #if CPUINFO_MOCK - #include +#include #endif -#include #include +#include - -bool cpuinfo_linux_parse_small_file(const char* filename, size_t buffer_size, cpuinfo_smallfile_callback callback, void* context) { +bool cpuinfo_linux_parse_small_file( + const char* filename, + size_t buffer_size, + cpuinfo_smallfile_callback callback, + void* context) { int file = -1; bool status = false; - char* buffer = (char*) alloca(buffer_size); + char* buffer = (char*)alloca(buffer_size); - #if CPUINFO_LOG_DEBUG_PARSERS - cpuinfo_log_debug("parsing small file %s", filename); - #endif +#if CPUINFO_LOG_DEBUG_PARSERS + cpuinfo_log_debug("parsing small file %s", filename); +#endif #if CPUINFO_MOCK file = cpuinfo_mock_open(filename, O_RDONLY); @@ -45,17 +48,22 @@ bool cpuinfo_linux_parse_small_file(const char* filename, size_t buffer_size, cp bytes_read = read(file, &buffer[buffer_position], buffer_size - buffer_position); #endif if (bytes_read < 0) { - cpuinfo_log_info("failed to read file %s at position %zu: %s", filename, buffer_position, strerror(errno)); + cpuinfo_log_info( + "failed to read file %s at position %zu: %s", + filename, + buffer_position, + strerror(errno)); goto cleanup; } - buffer_position += (size_t) bytes_read; + buffer_position += (size_t)bytes_read; if (buffer_position >= buffer_size) { - cpuinfo_log_error("failed to read file %s: insufficient buffer of size %zu", filename, buffer_size); + cpuinfo_log_error( + "failed to read file %s: insufficient buffer of size %zu", filename, buffer_size); goto cleanup; } } while (bytes_read != 0); - status = callback(buffer, &buffer[buffer_position], context); + status = callback(filename, buffer, &buffer[buffer_position], context); cleanup: if (file != -1) { diff --git a/3rdparty/cpuinfo/src/log.c b/3rdparty/cpuinfo/src/log.c index bec604eeea..2f85128d12 100644 --- a/3rdparty/cpuinfo/src/log.c +++ b/3rdparty/cpuinfo/src/log.c @@ -1,192 +1,203 @@ #include #include -#include -#include #include +#include +#include #ifdef _WIN32 - #include +#include #else - #include +#include #endif #if defined(__ANDROID__) - #include +#include #endif #if defined(__hexagon__) - #include +#include #endif #ifndef CPUINFO_LOG_TO_STDIO - #if defined(__ANDROID__) - #define CPUINFO_LOG_TO_STDIO 0 - #else - #define CPUINFO_LOG_TO_STDIO 1 - #endif +#if defined(__ANDROID__) +#define CPUINFO_LOG_TO_STDIO 0 +#else +#define CPUINFO_LOG_TO_STDIO 1 +#endif #endif #include - -/* Messages up to this size are formatted entirely on-stack, and don't allocate heap memory */ +/* Messages up to this size are formatted entirely on-stack, and don't allocate + * heap memory */ #define CPUINFO_LOG_STACK_BUFFER_SIZE 1024 #ifdef _WIN32 - #define CPUINFO_LOG_NEWLINE_LENGTH 2 +#define CPUINFO_LOG_NEWLINE_LENGTH 2 - #define CPUINFO_LOG_STDERR STD_ERROR_HANDLE - #define CPUINFO_LOG_STDOUT STD_OUTPUT_HANDLE +#define CPUINFO_LOG_STDERR STD_ERROR_HANDLE +#define CPUINFO_LOG_STDOUT STD_OUTPUT_HANDLE #elif defined(__hexagon__) - #define CPUINFO_LOG_NEWLINE_LENGTH 1 +#define CPUINFO_LOG_NEWLINE_LENGTH 1 - #define CPUINFO_LOG_STDERR 0 - #define CPUINFO_LOG_STDOUT 0 +#define CPUINFO_LOG_STDERR 0 +#define CPUINFO_LOG_STDOUT 0 #else - #define CPUINFO_LOG_NEWLINE_LENGTH 1 +#define CPUINFO_LOG_NEWLINE_LENGTH 1 - #define CPUINFO_LOG_STDERR STDERR_FILENO - #define CPUINFO_LOG_STDOUT STDOUT_FILENO +#define CPUINFO_LOG_STDERR STDERR_FILENO +#define CPUINFO_LOG_STDOUT STDOUT_FILENO #endif #if CPUINFO_LOG_TO_STDIO -static void cpuinfo_vlog(int output_handle, const char* prefix, size_t prefix_length, const char* format, va_list args) { - char stack_buffer[CPUINFO_LOG_STACK_BUFFER_SIZE]; - char* heap_buffer = NULL; - char* out_buffer = &stack_buffer[0]; +static void cpuinfo_vlog( + int output_handle, + const char* prefix, + size_t prefix_length, + const char* format, + va_list args) { + char stack_buffer[CPUINFO_LOG_STACK_BUFFER_SIZE]; + char* heap_buffer = NULL; + char* out_buffer = &stack_buffer[0]; - /* The first call to vsnprintf will clobber args, thus need a copy in case a second vsnprintf call is needed */ - va_list args_copy; - va_copy(args_copy, args); + /* The first call to vsnprintf will clobber args, thus need a copy in + * case a second vsnprintf call is needed */ + va_list args_copy; + va_copy(args_copy, args); - memcpy(stack_buffer, prefix, prefix_length * sizeof(char)); - assert((prefix_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char) <= CPUINFO_LOG_STACK_BUFFER_SIZE); + memcpy(stack_buffer, prefix, prefix_length * sizeof(char)); + assert((prefix_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char) <= CPUINFO_LOG_STACK_BUFFER_SIZE); - const int format_chars = vsnprintf( - &stack_buffer[prefix_length], - CPUINFO_LOG_STACK_BUFFER_SIZE - (prefix_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char), - format, - args); - if (format_chars < 0) { - /* Format error in the message: silently ignore this particular message. */ - goto cleanup; - } - const size_t format_length = (size_t) format_chars; - if ((prefix_length + format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char) > CPUINFO_LOG_STACK_BUFFER_SIZE) { - /* Allocate a buffer on heap, and vsnprintf to this buffer */ - const size_t heap_buffer_size = (prefix_length + format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char); - #if _WIN32 - heap_buffer = HeapAlloc(GetProcessHeap(), 0, heap_buffer_size); - #else - heap_buffer = malloc(heap_buffer_size); - #endif - if (heap_buffer == NULL) { - goto cleanup; - } + const int format_chars = vsnprintf( + &stack_buffer[prefix_length], + CPUINFO_LOG_STACK_BUFFER_SIZE - (prefix_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char), + format, + args); + if (format_chars < 0) { + /* Format error in the message: silently ignore this particular + * message. */ + goto cleanup; + } + const size_t format_length = (size_t)format_chars; + if ((prefix_length + format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char) > + CPUINFO_LOG_STACK_BUFFER_SIZE) { + /* Allocate a buffer on heap, and vsnprintf to this buffer */ + const size_t heap_buffer_size = + (prefix_length + format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char); +#if _WIN32 + heap_buffer = HeapAlloc(GetProcessHeap(), 0, heap_buffer_size); +#else + heap_buffer = malloc(heap_buffer_size); +#endif + if (heap_buffer == NULL) { + goto cleanup; + } - /* Copy pre-formatted prefix into the on-heap buffer */ - memcpy(heap_buffer, prefix, prefix_length * sizeof(char)); - vsnprintf(&heap_buffer[prefix_length], (format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char), format, args_copy); - out_buffer = heap_buffer; - } - #ifdef _WIN32 - out_buffer[prefix_length + format_length] = '\r'; - out_buffer[prefix_length + format_length + 1] = '\n'; + /* Copy pre-formatted prefix into the on-heap buffer */ + memcpy(heap_buffer, prefix, prefix_length * sizeof(char)); + vsnprintf( + &heap_buffer[prefix_length], + (format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char), + format, + args_copy); + out_buffer = heap_buffer; + } +#ifdef _WIN32 + out_buffer[prefix_length + format_length] = '\r'; + out_buffer[prefix_length + format_length + 1] = '\n'; - DWORD bytes_written; - WriteFile( - GetStdHandle((DWORD) output_handle), - out_buffer, (prefix_length + format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char), - &bytes_written, NULL); - #elif defined(__hexagon__) - qurt_printf("%s", out_buffer); - #else - out_buffer[prefix_length + format_length] = '\n'; + DWORD bytes_written; + WriteFile( + GetStdHandle((DWORD)output_handle), + out_buffer, + (prefix_length + format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char), + &bytes_written, + NULL); +#elif defined(__hexagon__) + qurt_printf("%s", out_buffer); +#else + out_buffer[prefix_length + format_length] = '\n'; - ssize_t bytes_written = write(output_handle, out_buffer, (prefix_length + format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char)); - (void) bytes_written; - #endif + ssize_t bytes_written = write( + output_handle, out_buffer, (prefix_length + format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char)); + (void)bytes_written; +#endif cleanup: - #ifdef _WIN32 - HeapFree(GetProcessHeap(), 0, heap_buffer); - #else - free(heap_buffer); - #endif - va_end(args_copy); +#ifdef _WIN32 + HeapFree(GetProcessHeap(), 0, heap_buffer); +#else + free(heap_buffer); +#endif + va_end(args_copy); } #elif defined(__ANDROID__) && CPUINFO_LOG_LEVEL > CPUINFO_LOG_NONE - static const char cpuinfo_module[] = "XNNPACK"; +static const char cpuinfo_module[] = "XNNPACK"; #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_DEBUG - void cpuinfo_vlog_debug(const char* format, va_list args) { - #if CPUINFO_LOG_TO_STDIO - static const char debug_prefix[17] = { - 'D', 'e', 'b', 'u', 'g', ' ', '(', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ')', ':', ' ' - }; - cpuinfo_vlog(CPUINFO_LOG_STDOUT, debug_prefix, 17, format, args); - #elif defined(__ANDROID__) - __android_log_vprint(ANDROID_LOG_DEBUG, cpuinfo_module, format, args); - #else - #error "Platform-specific implementation required" - #endif - } +void cpuinfo_vlog_debug(const char* format, va_list args) { +#if CPUINFO_LOG_TO_STDIO + static const char debug_prefix[17] = { + 'D', 'e', 'b', 'u', 'g', ' ', '(', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ')', ':', ' '}; + cpuinfo_vlog(CPUINFO_LOG_STDOUT, debug_prefix, 17, format, args); +#elif defined(__ANDROID__) + __android_log_vprint(ANDROID_LOG_DEBUG, cpuinfo_module, format, args); +#else +#error "Platform-specific implementation required" +#endif +} #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_INFO - void cpuinfo_vlog_info(const char* format, va_list args) { - #if CPUINFO_LOG_TO_STDIO - static const char info_prefix[16] = { - 'N', 'o', 't', 'e', ' ', '(', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ')', ':', ' ' - }; - cpuinfo_vlog(CPUINFO_LOG_STDOUT, info_prefix, 16, format, args); - #elif defined(__ANDROID__) - __android_log_vprint(ANDROID_LOG_INFO, cpuinfo_module, format, args); - #else - #error "Platform-specific implementation required" - #endif - } +void cpuinfo_vlog_info(const char* format, va_list args) { +#if CPUINFO_LOG_TO_STDIO + static const char info_prefix[16] = { + 'N', 'o', 't', 'e', ' ', '(', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ')', ':', ' '}; + cpuinfo_vlog(CPUINFO_LOG_STDOUT, info_prefix, 16, format, args); +#elif defined(__ANDROID__) + __android_log_vprint(ANDROID_LOG_INFO, cpuinfo_module, format, args); +#else +#error "Platform-specific implementation required" +#endif +} #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_WARNING - void cpuinfo_vlog_warning(const char* format, va_list args) { - #if CPUINFO_LOG_TO_STDIO - static const char warning_prefix[20] = { - 'W', 'a', 'r', 'n', 'i', 'n', 'g', ' ', 'i', 'n', ' ', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ':', ' ' - }; - cpuinfo_vlog(CPUINFO_LOG_STDERR, warning_prefix, 20, format, args); - #elif defined(__ANDROID__) - __android_log_vprint(ANDROID_LOG_WARN, cpuinfo_module, format, args); - #else - #error "Platform-specific implementation required" - #endif - } +void cpuinfo_vlog_warning(const char* format, va_list args) { +#if CPUINFO_LOG_TO_STDIO + static const char warning_prefix[20] = {'W', 'a', 'r', 'n', 'i', 'n', 'g', ' ', 'i', 'n', + ' ', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ':', ' '}; + cpuinfo_vlog(CPUINFO_LOG_STDERR, warning_prefix, 20, format, args); +#elif defined(__ANDROID__) + __android_log_vprint(ANDROID_LOG_WARN, cpuinfo_module, format, args); +#else +#error "Platform-specific implementation required" +#endif +} #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_ERROR - void cpuinfo_vlog_error(const char* format, va_list args) { - #if CPUINFO_LOG_TO_STDIO - static const char error_prefix[18] = { - 'E', 'r', 'r', 'o', 'r', ' ', 'i', 'n', ' ', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ':', ' ' - }; - cpuinfo_vlog(CPUINFO_LOG_STDERR, error_prefix, 18, format, args); - #elif defined(__ANDROID__) - __android_log_vprint(ANDROID_LOG_ERROR, cpuinfo_module, format, args); - #else - #error "Platform-specific implementation required" - #endif - } +void cpuinfo_vlog_error(const char* format, va_list args) { +#if CPUINFO_LOG_TO_STDIO + static const char error_prefix[18] = { + 'E', 'r', 'r', 'o', 'r', ' ', 'i', 'n', ' ', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ':', ' '}; + cpuinfo_vlog(CPUINFO_LOG_STDERR, error_prefix, 18, format, args); +#elif defined(__ANDROID__) + __android_log_vprint(ANDROID_LOG_ERROR, cpuinfo_module, format, args); +#else +#error "Platform-specific implementation required" +#endif +} #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_FATAL - void cpuinfo_vlog_fatal(const char* format, va_list args) { - #if CPUINFO_LOG_TO_STDIO - static const char fatal_prefix[24] = { - 'F', 'a', 't', 'a', 'l', ' ', 'e', 'r', 'r', 'o', 'r', ' ', 'i', 'n', ' ', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ':', ' ' - }; - cpuinfo_vlog(CPUINFO_LOG_STDERR, fatal_prefix, 24, format, args); - #elif defined(__ANDROID__) - __android_log_vprint(ANDROID_LOG_FATAL, cpuinfo_module, format, args); - #else - #error "Platform-specific implementation required" - #endif - } +void cpuinfo_vlog_fatal(const char* format, va_list args) { +#if CPUINFO_LOG_TO_STDIO + static const char fatal_prefix[24] = {'F', 'a', 't', 'a', 'l', ' ', 'e', 'r', 'r', 'o', 'r', ' ', + 'i', 'n', ' ', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ':', ' '}; + cpuinfo_vlog(CPUINFO_LOG_STDERR, fatal_prefix, 24, format, args); +#elif defined(__ANDROID__) + __android_log_vprint(ANDROID_LOG_FATAL, cpuinfo_module, format, args); +#else +#error "Platform-specific implementation required" +#endif +} #endif diff --git a/3rdparty/cpuinfo/src/mach/api.h b/3rdparty/cpuinfo/src/mach/api.h index fdef5bdff5..339aeff431 100644 --- a/3rdparty/cpuinfo/src/mach/api.h +++ b/3rdparty/cpuinfo/src/mach/api.h @@ -4,7 +4,6 @@ #define CPUINFO_MACH_MAX_CACHE_LEVELS 8 - struct cpuinfo_mach_topology { uint32_t packages; uint32_t cores; @@ -12,5 +11,4 @@ struct cpuinfo_mach_topology { uint32_t threads_per_cache[CPUINFO_MACH_MAX_CACHE_LEVELS]; }; - struct cpuinfo_mach_topology cpuinfo_mach_detect_topology(void); diff --git a/3rdparty/cpuinfo/src/mach/topology.c b/3rdparty/cpuinfo/src/mach/topology.c index b56343bb23..53160ce183 100644 --- a/3rdparty/cpuinfo/src/mach/topology.c +++ b/3rdparty/cpuinfo/src/mach/topology.c @@ -1,16 +1,15 @@ -#include #include #include +#include -#include #include +#include #include #include #include - struct cpuinfo_mach_topology cpuinfo_mach_detect_topology(void) { int cores = 1; size_t sizeof_cores = sizeof(cores); @@ -41,12 +40,9 @@ struct cpuinfo_mach_topology cpuinfo_mach_detect_topology(void) { } #endif - cpuinfo_log_debug("mach topology: packages = %d, cores = %d, threads = %d", packages, (int) cores, (int) threads); + cpuinfo_log_debug("mach topology: packages = %d, cores = %d, threads = %d", packages, (int)cores, (int)threads); struct cpuinfo_mach_topology topology = { - .packages = (uint32_t) packages, - .cores = (uint32_t) cores, - .threads = (uint32_t) threads - }; + .packages = (uint32_t)packages, .cores = (uint32_t)cores, .threads = (uint32_t)threads}; #if !TARGET_OS_IPHONE size_t cacheconfig_size = 0; @@ -63,7 +59,7 @@ struct cpuinfo_mach_topology cpuinfo_mach_detect_topology(void) { cache_configs = CPUINFO_MACH_MAX_CACHE_LEVELS; } for (size_t i = 0; i < cache_configs; i++) { - cpuinfo_log_debug("mach hw.cacheconfig[%zu]: %"PRIu64, i, cacheconfig[i]); + cpuinfo_log_debug("mach hw.cacheconfig[%zu]: %" PRIu64, i, cacheconfig[i]); topology.threads_per_cache[i] = cacheconfig[i]; } } diff --git a/3rdparty/cpuinfo/src/riscv/api.h b/3rdparty/cpuinfo/src/riscv/api.h index cd4bf464ff..d4f507b495 100644 --- a/3rdparty/cpuinfo/src/riscv/api.h +++ b/3rdparty/cpuinfo/src/riscv/api.h @@ -8,7 +8,7 @@ /* RISC-V Vendor IDs. */ enum cpuinfo_riscv_chipset_vendor { cpuinfo_riscv_chipset_vendor_unknown = 0, - cpuinfo_riscv_chipset_sifive = 0x489, + cpuinfo_riscv_chipset_vendor_sifive = 0x489, cpuinfo_riscv_chipset_vendor_max, }; @@ -35,8 +35,8 @@ enum cpuinfo_riscv_chipset_impl { * @param[uarch] - Reference to the cpuinfo_uarch to populate. */ CPUINFO_INTERNAL void cpuinfo_riscv_decode_vendor_uarch( - uint32_t vendor_id, - uint32_t arch_id, - uint32_t imp_id, - enum cpuinfo_vendor vendor[restrict static 1], - enum cpuinfo_uarch uarch[restrict static 1]); + uint32_t vendor_id, + uint32_t arch_id, + uint32_t imp_id, + enum cpuinfo_vendor vendor[restrict static 1], + enum cpuinfo_uarch uarch[restrict static 1]); diff --git a/3rdparty/cpuinfo/src/riscv/linux/api.h b/3rdparty/cpuinfo/src/riscv/linux/api.h index 5f1a8cf359..829de84b50 100644 --- a/3rdparty/cpuinfo/src/riscv/linux/api.h +++ b/3rdparty/cpuinfo/src/riscv/linux/api.h @@ -22,23 +22,26 @@ struct cpuinfo_riscv_linux_processor { uint32_t flags; /** - * Minimum processor ID on the cluster which includes this logical processor. - * This value can serve as an ID for the cluster of logical processors: it is the - * same for all logical processors on the same package. + * Minimum processor ID on the cluster which includes this logical + * processor. This value can serve as an ID for the cluster of logical + * processors: it is the same for all logical processors on the same + * package. */ uint32_t cluster_leader_id; /** - * Minimum processor ID on the core which includes this logical processor. - * This value can serve as an ID for the core of logical processors: it - * is the same for all logical processors on the same core. + * Minimum processor ID on the core which includes this logical + * processor. This value can serve as an ID for the core of logical + * processors: it is the same for all logical processors on the same + * core. */ uint32_t core_leader_id; /** - * Minimum processor ID on the package which includes this logical processor. - * This value can serve as an ID for the package of logical processors: it - * is the same for all logical processors on the same package. + * Minimum processor ID on the package which includes this logical + * processor. This value can serve as an ID for the package of logical + * processors: it is the same for all logical processors on the same + * package. */ uint32_t package_leader_id; }; @@ -49,8 +52,7 @@ struct cpuinfo_riscv_linux_processor { * * @param[isa] - Reference to cpuinfo_riscv_isa structure to populate. */ -CPUINFO_INTERNAL void cpuinfo_riscv_linux_decode_isa_from_hwcap( - struct cpuinfo_riscv_isa isa[restrict static 1]); +CPUINFO_INTERNAL void cpuinfo_riscv_linux_decode_isa_from_hwcap(struct cpuinfo_riscv_isa isa[restrict static 1]); /** * Reads `sys_riscv_hwprobe` and determines the processor vendor and diff --git a/3rdparty/cpuinfo/src/riscv/linux/init.c b/3rdparty/cpuinfo/src/riscv/linux/init.c index d1c43c542a..9ab3d6e60c 100644 --- a/3rdparty/cpuinfo/src/riscv/linux/init.c +++ b/3rdparty/cpuinfo/src/riscv/linux/init.c @@ -10,7 +10,7 @@ struct cpuinfo_riscv_isa cpuinfo_isa; /* Helper function to bitmask flags and ensure operator precedence. */ static inline bool bitmask_all(uint32_t flags, uint32_t mask) { - return (flags & mask) == mask; + return (flags & mask) == mask; } static int compare_riscv_linux_processors(const void* a, const void* b) { @@ -18,8 +18,8 @@ static int compare_riscv_linux_processors(const void* a, const void* b) { * For our purposes, it is only relevant that the list is sorted by * micro-architecture, so the nature of ordering is irrelevant. */ - return ((const struct cpuinfo_riscv_linux_processor*)a)->core.uarch - - ((const struct cpuinfo_riscv_linux_processor*)b)->core.uarch; + return ((const struct cpuinfo_riscv_linux_processor*)a)->core.uarch - + ((const struct cpuinfo_riscv_linux_processor*)b)->core.uarch; } /** @@ -37,10 +37,11 @@ static int compare_riscv_linux_processors(const void* a, const void* b) { * E.g. processors[0].core_leader_id = 0. */ -static bool core_cpus_parser(uint32_t processor, - uint32_t core_cpus_start, - uint32_t core_cpus_end, - struct cpuinfo_riscv_linux_processor* processors) { +static bool core_cpus_parser( + uint32_t processor, + uint32_t core_cpus_start, + uint32_t core_cpus_end, + struct cpuinfo_riscv_linux_processor* processors) { uint32_t processor_start = UINT32_MAX; uint32_t processor_count = 0; @@ -70,8 +71,8 @@ static bool core_cpus_parser(uint32_t processor, * * e.g. core_cpu_list=1,10-12 */ - if (!bitmask_all(processors[processor].flags, CPUINFO_LINUX_FLAG_CORE_CLUSTER) - || processors[processor].core.processor_start > processor_start) { + if (!bitmask_all(processors[processor].flags, CPUINFO_LINUX_FLAG_CORE_CLUSTER) || + processors[processor].core.processor_start > processor_start) { processors[processor].core.processor_start = processor_start; processors[processor].core_leader_id = processor_start; } @@ -92,10 +93,11 @@ static bool core_cpus_parser(uint32_t processor, * their 'cluster_leader_id' to their index in the list. * E.g. processors[0].cluster_leader_id = 0. */ -static bool cluster_cpus_parser(uint32_t processor, - uint32_t cluster_cpus_start, - uint32_t cluster_cpus_end, - struct cpuinfo_riscv_linux_processor* processors) { +static bool cluster_cpus_parser( + uint32_t processor, + uint32_t cluster_cpus_start, + uint32_t cluster_cpus_end, + struct cpuinfo_riscv_linux_processor* processors) { uint32_t processor_start = UINT32_MAX; uint32_t processor_count = 0; uint32_t core_count = 0; @@ -133,8 +135,8 @@ static bool cluster_cpus_parser(uint32_t processor, * * e.g. cluster_cpus_list=1,10-12 */ - if (!bitmask_all(processors[processor].flags, CPUINFO_LINUX_FLAG_CLUSTER_CLUSTER) - || processors[processor].cluster.processor_start > processor_start) { + if (!bitmask_all(processors[processor].flags, CPUINFO_LINUX_FLAG_CLUSTER_CLUSTER) || + processors[processor].cluster.processor_start > processor_start) { processors[processor].cluster.processor_start = processor_start; processors[processor].cluster.core_start = processor_start; processors[processor].cluster.cluster_id = processor_start; @@ -160,10 +162,11 @@ static bool cluster_cpus_parser(uint32_t processor, * their 'package_leader_id' to their index in the list. * E.g. processors[0].package_leader_id = 0. */ -static bool package_cpus_parser(uint32_t processor, - uint32_t package_cpus_start, - uint32_t package_cpus_end, - struct cpuinfo_riscv_linux_processor* processors) { +static bool package_cpus_parser( + uint32_t processor, + uint32_t package_cpus_start, + uint32_t package_cpus_end, + struct cpuinfo_riscv_linux_processor* processors) { uint32_t processor_start = UINT32_MAX; uint32_t processor_count = 0; uint32_t cluster_count = 0; @@ -205,8 +208,8 @@ static bool package_cpus_parser(uint32_t processor, * * e.g. package_cpus_list=1,10-12 */ - if (!bitmask_all(processors[processor].flags, CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER) - || processors[processor].package.processor_start > processor_start) { + if (!bitmask_all(processors[processor].flags, CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER) || + processors[processor].package.processor_start > processor_start) { processors[processor].package.processor_start = processor_start; processors[processor].package.cluster_start = processor_start; processors[processor].package.core_start = processor_start; @@ -233,8 +236,9 @@ void cpuinfo_riscv_linux_init(void) { /** * The interesting set of processors are the number of 'present' - * processors on the system. There may be more 'possible' processors, but - * processor information cannot be gathered on non-present processors. + * processors on the system. There may be more 'possible' processors, + * but processor information cannot be gathered on non-present + * processors. * * Note: For SoCs, it is largely the case that all processors are known * at boot and no processors are hotplugged at runtime, so the @@ -244,9 +248,8 @@ void cpuinfo_riscv_linux_init(void) { * processors. It is not a count of the number of processors on the * system. */ - const uint32_t max_processor_id = 1 + - cpuinfo_linux_get_max_present_processor( - cpuinfo_linux_get_max_processors_count()); + const uint32_t max_processor_id = + 1 + cpuinfo_linux_get_max_present_processor(cpuinfo_linux_get_max_processors_count()); if (max_processor_id == 0) { cpuinfo_log_error("failed to discover any processors"); return; @@ -257,35 +260,36 @@ void cpuinfo_riscv_linux_init(void) { * sized to the max processor ID as opposed to the number of 'present' * processors, to leverage pointer math in the common utility functions. */ - riscv_linux_processors = calloc(max_processor_id, - sizeof(struct cpuinfo_riscv_linux_processor)); + riscv_linux_processors = calloc(max_processor_id, sizeof(struct cpuinfo_riscv_linux_processor)); if (riscv_linux_processors == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %"PRIu32" processors.", + cpuinfo_log_error( + "failed to allocate %zu bytes for %" PRIu32 " processors.", max_processor_id * sizeof(struct cpuinfo_riscv_linux_processor), max_processor_id); goto cleanup; - } + } /** * Attempt to detect all processors and apply the corresponding flag to * each processor struct that we find. */ - if (!cpuinfo_linux_detect_present_processors(max_processor_id, - &riscv_linux_processors->flags, - sizeof(struct cpuinfo_riscv_linux_processor), - CPUINFO_LINUX_FLAG_PRESENT | CPUINFO_LINUX_FLAG_VALID)) { + if (!cpuinfo_linux_detect_present_processors( + max_processor_id, + &riscv_linux_processors->flags, + sizeof(struct cpuinfo_riscv_linux_processor), + CPUINFO_LINUX_FLAG_PRESENT | CPUINFO_LINUX_FLAG_VALID)) { cpuinfo_log_error("failed to detect present processors"); goto cleanup; } - /* Populate processor information. */ - for (size_t processor = 0; processor < max_processor_id; processor++) { + /* Populate processor information. */ + for (size_t processor = 0; processor < max_processor_id; processor++) { if (!bitmask_all(riscv_linux_processors[processor].flags, CPUINFO_LINUX_FLAG_VALID)) { continue; - } - /* TODO: Determine if an 'smt_id' is available. */ - riscv_linux_processors[processor].processor.linux_id = processor; - } + } + /* TODO: Determine if an 'smt_id' is available. */ + riscv_linux_processors[processor].processor.linux_id = processor; + } /* Populate core information. */ for (size_t processor = 0; processor < max_processor_id; processor++) { @@ -295,18 +299,16 @@ void cpuinfo_riscv_linux_init(void) { /* Populate processor start and count information. */ if (!cpuinfo_linux_detect_core_cpus( - max_processor_id, - processor, - (cpuinfo_siblings_callback) core_cpus_parser, - riscv_linux_processors)) { + max_processor_id, + processor, + (cpuinfo_siblings_callback)core_cpus_parser, + riscv_linux_processors)) { cpuinfo_log_error("failed to detect core cpus for processor %zu.", processor); goto cleanup; } /* Populate core ID information. */ - if (cpuinfo_linux_get_processor_core_id( - processor, - &riscv_linux_processors[processor].core.core_id)) { + if (cpuinfo_linux_get_processor_core_id(processor, &riscv_linux_processors[processor].core.core_id)) { riscv_linux_processors[processor].flags |= CPUINFO_LINUX_FLAG_CORE_ID; } @@ -316,9 +318,9 @@ void cpuinfo_riscv_linux_init(void) { * the values from the core leader will be honored. */ cpuinfo_riscv_linux_decode_vendor_uarch_from_hwprobe( - processor, - &riscv_linux_processors[processor].core.vendor, - &riscv_linux_processors[processor].core.uarch); + processor, + &riscv_linux_processors[processor].core.vendor, + &riscv_linux_processors[processor].core.uarch); /* Populate frequency information of this core. */ uint32_t frequency = cpuinfo_linux_get_processor_cur_frequency(processor); @@ -334,25 +336,23 @@ void cpuinfo_riscv_linux_init(void) { continue; } if (!cpuinfo_linux_detect_cluster_cpus( - max_processor_id, - processor, - (cpuinfo_siblings_callback) cluster_cpus_parser, - riscv_linux_processors)) { + max_processor_id, + processor, + (cpuinfo_siblings_callback)cluster_cpus_parser, + riscv_linux_processors)) { cpuinfo_log_warning("failed to detect cluster cpus for processor %zu.", processor); goto cleanup; } /** * Populate the vendor, uarch and frequency of this cluster from - * this logical processor. When the 'clusters' list is constructed, - * only the values from the cluster leader will be honored. + * this logical processor. When the 'clusters' list is + * constructed, only the values from the cluster leader will be + * honored. */ - riscv_linux_processors[processor].cluster.vendor = - riscv_linux_processors[processor].core.vendor; - riscv_linux_processors[processor].cluster.uarch = - riscv_linux_processors[processor].core.uarch; - riscv_linux_processors[processor].cluster.frequency = - riscv_linux_processors[processor].core.frequency; + riscv_linux_processors[processor].cluster.vendor = riscv_linux_processors[processor].core.vendor; + riscv_linux_processors[processor].cluster.uarch = riscv_linux_processors[processor].core.uarch; + riscv_linux_processors[processor].cluster.frequency = riscv_linux_processors[processor].core.frequency; } /* Populate package information. */ @@ -361,10 +361,10 @@ void cpuinfo_riscv_linux_init(void) { continue; } if (!cpuinfo_linux_detect_package_cpus( - max_processor_id, - processor, - (cpuinfo_siblings_callback) package_cpus_parser, - riscv_linux_processors)) { + max_processor_id, + processor, + (cpuinfo_siblings_callback)package_cpus_parser, + riscv_linux_processors)) { cpuinfo_log_warning("failed to detect package cpus for processor %zu.", processor); goto cleanup; } @@ -424,45 +424,44 @@ void cpuinfo_riscv_linux_init(void) { * As we've sorted by micro-architecture, when the uarch differs * between two entries, a unique uarch has been observed. */ - if (last_uarch != riscv_linux_processors[processor].core.uarch - || valid_uarchs_count == 0) { + if (last_uarch != riscv_linux_processors[processor].core.uarch || valid_uarchs_count == 0) { valid_uarchs_count++; last_uarch = riscv_linux_processors[processor].core.uarch; } } /* Allocate and populate final public ABI structures. */ - processors = calloc(valid_processors_count, - sizeof(struct cpuinfo_processor)); + processors = calloc(valid_processors_count, sizeof(struct cpuinfo_processor)); if (processors == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %zu processors.", + cpuinfo_log_error( + "failed to allocate %zu bytes for %zu processors.", valid_processors_count * sizeof(struct cpuinfo_processor), valid_processors_count); goto cleanup; } - cores = calloc(valid_cores_count, - sizeof(struct cpuinfo_core)); + cores = calloc(valid_cores_count, sizeof(struct cpuinfo_core)); if (cores == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %zu cores.", + cpuinfo_log_error( + "failed to allocate %zu bytes for %zu cores.", valid_cores_count * sizeof(struct cpuinfo_core), valid_cores_count); goto cleanup; } - clusters = calloc(valid_clusters_count, - sizeof(struct cpuinfo_cluster)); + clusters = calloc(valid_clusters_count, sizeof(struct cpuinfo_cluster)); if (clusters == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %zu clusters.", + cpuinfo_log_error( + "failed to allocate %zu bytes for %zu clusters.", valid_clusters_count * sizeof(struct cpuinfo_cluster), valid_clusters_count); goto cleanup; } - packages = calloc(valid_packages_count, - sizeof(struct cpuinfo_package)); + packages = calloc(valid_packages_count, sizeof(struct cpuinfo_package)); if (packages == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %zu packages.", + cpuinfo_log_error( + "failed to allocate %zu bytes for %zu packages.", valid_packages_count * sizeof(struct cpuinfo_package), valid_packages_count); goto cleanup; @@ -470,36 +469,37 @@ void cpuinfo_riscv_linux_init(void) { uarchs = calloc(valid_uarchs_count, sizeof(struct cpuinfo_uarch_info)); if (uarchs == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %zu packages.", + cpuinfo_log_error( + "failed to allocate %zu bytes for %zu packages.", valid_uarchs_count * sizeof(struct cpuinfo_uarch_info), valid_uarchs_count); goto cleanup; } - linux_cpu_to_processor_map = calloc(max_processor_id, - sizeof(struct cpuinfo_processor*)); + linux_cpu_to_processor_map = calloc(max_processor_id, sizeof(struct cpuinfo_processor*)); if (linux_cpu_to_processor_map == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %"PRIu32" processor map.", - max_processor_id * sizeof(struct cpuinfo_processor*), - max_processor_id); + cpuinfo_log_error( + "failed to allocate %zu bytes for %" PRIu32 " processor map.", + max_processor_id * sizeof(struct cpuinfo_processor*), + max_processor_id); goto cleanup; } - linux_cpu_to_core_map = calloc(max_processor_id, - sizeof(struct cpuinfo_core*)); + linux_cpu_to_core_map = calloc(max_processor_id, sizeof(struct cpuinfo_core*)); if (linux_cpu_to_core_map == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %"PRIu32" core map.", - max_processor_id * sizeof(struct cpuinfo_core*), - max_processor_id); + cpuinfo_log_error( + "failed to allocate %zu bytes for %" PRIu32 " core map.", + max_processor_id * sizeof(struct cpuinfo_core*), + max_processor_id); goto cleanup; } - linux_cpu_to_uarch_index_map = calloc(max_processor_id, - sizeof(struct cpuinfo_uarch_info*)); + linux_cpu_to_uarch_index_map = calloc(max_processor_id, sizeof(struct cpuinfo_uarch_info*)); if (linux_cpu_to_uarch_index_map == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %"PRIu32" uarch map.", - max_processor_id * sizeof(struct cpuinfo_uarch_info*), - max_processor_id); + cpuinfo_log_error( + "failed to allocate %zu bytes for %" PRIu32 " uarch map.", + max_processor_id * sizeof(struct cpuinfo_uarch_info*), + max_processor_id); goto cleanup; } @@ -524,17 +524,15 @@ void cpuinfo_riscv_linux_init(void) { uint32_t linux_id = riscv_linux_processors[processor].processor.linux_id; /* Create uarch entry if this uarch has not been seen before. */ - if (last_uarch != riscv_linux_processors[processor].core.uarch - || valid_uarchs_index == 0) { - uarchs[valid_uarchs_index++].uarch = - riscv_linux_processors[processor].core.uarch; + if (last_uarch != riscv_linux_processors[processor].core.uarch || valid_uarchs_index == 0) { + uarchs[valid_uarchs_index++].uarch = riscv_linux_processors[processor].core.uarch; last_uarch = riscv_linux_processors[processor].core.uarch; } /* Copy cpuinfo_processor information. */ memcpy(&processors[valid_processors_index++], &riscv_linux_processors[processor].processor, - sizeof(struct cpuinfo_processor)); + sizeof(struct cpuinfo_processor)); /* Update uarch processor count. */ uarchs[valid_uarchs_index - 1].processor_count++; @@ -598,7 +596,8 @@ void cpuinfo_riscv_linux_init(void) { cpuinfo_is_initialized = true; - /* Mark all public structures NULL to prevent cleanup from erasing them. */ + /* Mark all public structures NULL to prevent cleanup from erasing them. + */ processors = NULL; cores = NULL; clusters = NULL; diff --git a/3rdparty/cpuinfo/src/riscv/linux/riscv-hw.c b/3rdparty/cpuinfo/src/riscv/linux/riscv-hw.c index ccee848cf4..d737acad14 100644 --- a/3rdparty/cpuinfo/src/riscv/linux/riscv-hw.c +++ b/3rdparty/cpuinfo/src/riscv/linux/riscv-hw.c @@ -1,18 +1,88 @@ +/* + * Only enable the C standard library hwprobe interface on Android for now. + * Patches to add a compatible hwprobe API to glibc are available but not + * merged at the time of writing and so cannot easily be tested. The + * #ifdef __ANDROID__ check will be removed in the future. + */ +#ifdef __ANDROID__ +#ifdef __has_include +#if __has_include() +#define CPUINFO_RISCV_LINUX_HAVE_C_HWPROBE #include +#endif +#endif +#endif + #include #include #include #include +#ifndef CPUINFO_RISCV_LINUX_HAVE_C_HWPROBE + +#include +#include +#include + +struct riscv_hwprobe { + int64_t key; + uint64_t value; +}; + +/* + * The standard C library our binary was compiled with does not support + * hwprobe but the kernel on which we are running might do. The + * constants below are copied from + * /usr/include/riscv64-linux-gnu/asm/hwprobe.h. They allow us to + * invoke the hwprobe syscall directly. We duplicate the constants + * rather than including the kernel hwprobe.h header, as this header + * will only be present if we're building Linux 6.4 or greater. + */ + +#define RISCV_HWPROBE_KEY_MVENDORID 0 +#define RISCV_HWPROBE_KEY_MARCHID 1 +#define RISCV_HWPROBE_KEY_MIMPID 2 +#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 +#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) +#define RISCV_HWPROBE_KEY_IMA_EXT_0 4 +#define RISCV_HWPROBE_IMA_FD (1 << 0) +#define RISCV_HWPROBE_IMA_C (1 << 1) +#define RISCV_HWPROBE_IMA_V (1 << 2) +#define RISCV_HWPROBE_EXT_ZBA (1 << 3) +#define RISCV_HWPROBE_EXT_ZBB (1 << 4) +#define RISCV_HWPROBE_EXT_ZBS (1 << 5) +#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6) +#define RISCV_HWPROBE_KEY_CPUPERF_0 5 +#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) +#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) +#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0) +#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) +#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) +#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) + +#ifndef NR_riscv_hwprobe +#ifndef NR_arch_specific_syscall +#define NR_arch_specific_syscall 244 +#endif +#define NR_riscv_hwprobe (NR_arch_specific_syscall + 14) +#endif +#endif + void cpuinfo_riscv_linux_decode_vendor_uarch_from_hwprobe( - uint32_t processor, - enum cpuinfo_vendor vendor[restrict static 1], - enum cpuinfo_uarch uarch[restrict static 1]) { + uint32_t processor, + enum cpuinfo_vendor vendor[restrict static 1], + enum cpuinfo_uarch uarch[restrict static 1]) { struct riscv_hwprobe pairs[] = { - { .key = RISCV_HWPROBE_KEY_MVENDORID, }, - { .key = RISCV_HWPROBE_KEY_MARCHID, }, - { .key = RISCV_HWPROBE_KEY_MIMPID, }, + { + .key = RISCV_HWPROBE_KEY_MVENDORID, + }, + { + .key = RISCV_HWPROBE_KEY_MARCHID, + }, + { + .key = RISCV_HWPROBE_KEY_MIMPID, + }, }; const size_t pairs_count = sizeof(pairs) / sizeof(struct riscv_hwprobe); @@ -21,17 +91,34 @@ void cpuinfo_riscv_linux_decode_vendor_uarch_from_hwprobe( *uarch = cpuinfo_uarch_unknown; /* Create a CPU set with this processor flagged. */ - const size_t cpu_set_size = processor + 1; - cpu_set_t* cpu_set = CPU_ALLOC(cpu_set_size); - CPU_SET(processor, cpu_set); + const size_t cpu_count = processor + 1; + cpu_set_t* cpu_set = CPU_ALLOC(cpu_count); + if (cpu_set == NULL) { + cpuinfo_log_warning("failed to allocate space for cpu_set"); + return; + } + + const size_t cpu_set_size = CPU_ALLOC_SIZE(cpu_count); + CPU_ZERO_S(cpu_set_size, cpu_set); + CPU_SET_S(processor, cpu_set_size, cpu_set); /* Request all available information from hwprobe. */ - int ret = __riscv_hwprobe(pairs, pairs_count, - cpu_set_size, (unsigned long*)cpu_set, - 0 /* flags */); +#ifndef CPUINFO_RISCV_LINUX_HAVE_C_HWPROBE + /* + * No standard library support for hwprobe. We'll need to invoke the + * syscall directly. See + * + * https://docs.kernel.org/arch/riscv/hwprobe.html + * + * for more details. + */ + int ret = syscall(NR_riscv_hwprobe, pairs, pairs_count, cpu_set_size, (unsigned long*)cpu_set, 0 /* flags */); +#else + int ret = __riscv_hwprobe(pairs, pairs_count, cpu_set_size, (unsigned long*)cpu_set, 0 /* flags */); +#endif if (ret < 0) { cpuinfo_log_warning("failed to get hwprobe information, err: %d", ret); - return; + goto cleanup; } /** @@ -57,6 +144,8 @@ void cpuinfo_riscv_linux_decode_vendor_uarch_from_hwprobe( break; } } - cpuinfo_riscv_decode_vendor_uarch(vendor_id, arch_id, imp_id, - vendor, uarch); + cpuinfo_riscv_decode_vendor_uarch(vendor_id, arch_id, imp_id, vendor, uarch); + +cleanup: + CPU_FREE(cpu_set); } diff --git a/3rdparty/cpuinfo/src/riscv/linux/riscv-isa.c b/3rdparty/cpuinfo/src/riscv/linux/riscv-isa.c index ace451b858..c133965fcc 100644 --- a/3rdparty/cpuinfo/src/riscv/linux/riscv-isa.c +++ b/3rdparty/cpuinfo/src/riscv/linux/riscv-isa.c @@ -8,16 +8,15 @@ * * This must be kept in sync with the upstream kernel header. */ -#define COMPAT_HWCAP_ISA_I (1 << ('I' - 'A')) -#define COMPAT_HWCAP_ISA_M (1 << ('M' - 'A')) -#define COMPAT_HWCAP_ISA_A (1 << ('A' - 'A')) -#define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A')) -#define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) -#define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) -#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A')) +#define COMPAT_HWCAP_ISA_I (1 << ('I' - 'A')) +#define COMPAT_HWCAP_ISA_M (1 << ('M' - 'A')) +#define COMPAT_HWCAP_ISA_A (1 << ('A' - 'A')) +#define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A')) +#define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) +#define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) +#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A')) -void cpuinfo_riscv_linux_decode_isa_from_hwcap( - struct cpuinfo_riscv_isa isa[restrict static 1]) { +void cpuinfo_riscv_linux_decode_isa_from_hwcap(struct cpuinfo_riscv_isa isa[restrict static 1]) { const unsigned long hwcap = getauxval(AT_HWCAP); if (hwcap & COMPAT_HWCAP_ISA_I) { diff --git a/3rdparty/cpuinfo/src/riscv/uarch.c b/3rdparty/cpuinfo/src/riscv/uarch.c index bf93e867d7..83b03c3028 100644 --- a/3rdparty/cpuinfo/src/riscv/uarch.c +++ b/3rdparty/cpuinfo/src/riscv/uarch.c @@ -10,13 +10,13 @@ void cpuinfo_riscv_decode_vendor_uarch( enum cpuinfo_vendor vendor[restrict static 1], enum cpuinfo_uarch uarch[restrict static 1]) { /* The vendor ID is sufficient to determine the cpuinfo_vendor. */ - switch(vendor_id) { - case cpuinfo_riscv_chipset_sifive: + switch (vendor_id) { + case cpuinfo_riscv_chipset_vendor_sifive: *vendor = cpuinfo_vendor_sifive; break; default: *vendor = cpuinfo_vendor_unknown; - cpuinfo_log_warning("unknown vendor ID: %"PRIu32, vendor_id); + cpuinfo_log_warning("unknown vendor ID: %" PRIu32, vendor_id); break; } /** diff --git a/3rdparty/cpuinfo/src/x86/api.h b/3rdparty/cpuinfo/src/x86/api.h index 213c2d8813..1331ed0432 100644 --- a/3rdparty/cpuinfo/src/x86/api.h +++ b/3rdparty/cpuinfo/src/x86/api.h @@ -6,7 +6,6 @@ #include #include - struct cpuid_regs { uint32_t eax; uint32_t ebx; @@ -90,9 +89,12 @@ CPUINFO_INTERNAL enum cpuinfo_uarch cpuinfo_x86_decode_uarch( const struct cpuinfo_x86_model_info* model_info); CPUINFO_INTERNAL struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( - const struct cpuid_regs basic_info, const struct cpuid_regs extended_info, - uint32_t max_base_index, uint32_t max_extended_index, - enum cpuinfo_vendor vendor, enum cpuinfo_uarch uarch); + const struct cpuid_regs basic_info, + const struct cpuid_regs extended_info, + uint32_t max_base_index, + uint32_t max_extended_index, + enum cpuinfo_vendor vendor, + enum cpuinfo_uarch uarch); CPUINFO_INTERNAL void cpuinfo_x86_detect_topology( uint32_t max_base_index, @@ -101,7 +103,8 @@ CPUINFO_INTERNAL void cpuinfo_x86_detect_topology( struct cpuinfo_x86_topology* topology); CPUINFO_INTERNAL void cpuinfo_x86_detect_cache( - uint32_t max_base_index, uint32_t max_extended_index, + uint32_t max_base_index, + uint32_t max_extended_index, bool amd_topology_extensions, enum cpuinfo_vendor vendor, const struct cpuinfo_x86_model_info* model_info, @@ -122,7 +125,8 @@ CPUINFO_INTERNAL void cpuinfo_x86_detect_cache( uint32_t* log2_package_cores_max); CPUINFO_INTERNAL void cpuinfo_x86_decode_cache_descriptor( - uint8_t descriptor, enum cpuinfo_vendor vendor, + uint8_t descriptor, + enum cpuinfo_vendor vendor, const struct cpuinfo_x86_model_info* model_info, struct cpuinfo_x86_caches* cache, struct cpuinfo_tlb* itlb_4KB, @@ -145,13 +149,9 @@ CPUINFO_INTERNAL bool cpuinfo_x86_decode_deterministic_cache_parameters( struct cpuinfo_x86_caches* cache, uint32_t* package_cores_max); -CPUINFO_INTERNAL bool cpuinfo_x86_decode_cache_properties( - struct cpuid_regs regs, - struct cpuinfo_x86_caches* cache); +CPUINFO_INTERNAL bool cpuinfo_x86_decode_cache_properties(struct cpuid_regs regs, struct cpuinfo_x86_caches* cache); -CPUINFO_INTERNAL uint32_t cpuinfo_x86_normalize_brand_string( - const char raw_name[48], - char normalized_name[48]); +CPUINFO_INTERNAL uint32_t cpuinfo_x86_normalize_brand_string(const char raw_name[48], char normalized_name[48]); CPUINFO_INTERNAL uint32_t cpuinfo_x86_format_package_name( enum cpuinfo_vendor vendor, diff --git a/3rdparty/cpuinfo/src/x86/cache/descriptor.c b/3rdparty/cpuinfo/src/x86/cache/descriptor.c index 69d38cc394..93d855aee3 100644 --- a/3rdparty/cpuinfo/src/x86/cache/descriptor.c +++ b/3rdparty/cpuinfo/src/x86/cache/descriptor.c @@ -3,9 +3,9 @@ #include #include - void cpuinfo_x86_decode_cache_descriptor( - uint8_t descriptor, enum cpuinfo_vendor vendor, + uint8_t descriptor, + enum cpuinfo_vendor vendor, const struct cpuinfo_x86_model_info* model_info, struct cpuinfo_x86_caches* cache, struct cpuinfo_tlb* itlb_4KB, @@ -21,13 +21,14 @@ void cpuinfo_x86_decode_cache_descriptor( struct cpuinfo_tlb* stlb2_4KB, struct cpuinfo_tlb* stlb2_2MB, struct cpuinfo_tlb* stlb2_1GB, - uint32_t* prefetch_size) -{ + uint32_t* prefetch_size) { /* * Descriptors are parsed according to: - * - Application Note 485: Intel Processor Indentification and CPUID Instruction, May 2012, Order Number 241618-039 - * - Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 2 (2A, 2B, 2C & 2D): Instruction Set - * Reference, A-Z, December 2016. Order Number: 325383-061US + * - Application Note 485: Intel Processor Indentification and CPUID + * Instruction, May 2012, Order Number 241618-039 + * - Intel 64 and IA-32 Architectures Software Developer’s Manual, + * Volume 2 (2A, 2B, 2C & 2D): Instruction Set Reference, A-Z, December + * 2016. Order Number: 325383-061US * - Cyrix CPU Detection Guide, Preliminary Revision 1.01 * - Geode(TM) GX1 Processor Series: Low Power Integrated x86 Solution */ @@ -35,11 +36,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x01: /* * Intel ISA Reference: - * "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries" - * Application Note 485: - * "Instruction TLB: 4-KB Pages, 4-way set associative, 32 entries" + * "Instruction TLB: 4 KByte pages, 4-way set + * associative, 32 entries" Application Note 485: + * "Instruction TLB: 4-KB Pages, 4-way set + * associative, 32 entries" */ - *itlb_4KB = (struct cpuinfo_tlb) { + *itlb_4KB = (struct cpuinfo_tlb){ .entries = 32, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -48,11 +50,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x02: /* * Intel ISA Reference: - * "Instruction TLB: 4 MByte pages, fully associative, 2 entries" - * Application Note 485: - * "Instruction TLB: 4-MB Pages, fully associative, 2 entries" + * "Instruction TLB: 4 MByte pages, fully + * associative, 2 entries" Application Note 485: + * "Instruction TLB: 4-MB Pages, fully associative, + * 2 entries" */ - *itlb_4MB = (struct cpuinfo_tlb) { + *itlb_4MB = (struct cpuinfo_tlb){ .entries = 2, .associativity = 2, .pages = CPUINFO_PAGE_SIZE_4MB, @@ -61,11 +64,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x03: /* * Intel ISA Reference: - * "Data TLB: 4 KByte pages, 4-way set associative, 64 entries" - * Application Note 485: - * "Data TLB: 4-KB Pages, 4-way set associative, 64 entries" + * "Data TLB: 4 KByte pages, 4-way set associative, + * 64 entries" Application Note 485: "Data TLB: 4-KB + * Pages, 4-way set associative, 64 entries" */ - *dtlb_4KB = (struct cpuinfo_tlb) { + *dtlb_4KB = (struct cpuinfo_tlb){ .entries = 64, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -74,11 +77,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x04: /* * Intel ISA Reference: - * "Data TLB: 4 MByte pages, 4-way set associative, 8 entries" - * Application Note 485: - * "Data TLB: 4-MB Pages, 4-way set associative, 8 entries" + * "Data TLB: 4 MByte pages, 4-way set associative, + * 8 entries" Application Note 485: "Data TLB: 4-MB + * Pages, 4-way set associative, 8 entries" */ - *dtlb_4MB = (struct cpuinfo_tlb) { + *dtlb_4MB = (struct cpuinfo_tlb){ .entries = 8, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4MB, @@ -87,11 +90,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x05: /* * Intel ISA Reference: - * "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries" - * Application Note 485: - * "Data TLB: 4-MB Pages, 4-way set associative, 32 entries" + * "Data TLB1: 4 MByte pages, 4-way set associative, + * 32 entries" Application Note 485: "Data TLB: 4-MB + * Pages, 4-way set associative, 32 entries" */ - *dtlb_4MB = (struct cpuinfo_tlb) { + *dtlb_4MB = (struct cpuinfo_tlb){ .entries = 32, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4MB, @@ -100,11 +103,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x06: /* * Intel ISA Reference: - * "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size" - * Application Note 485: - * "1st-level instruction cache: 8-KB, 4-way set associative, 32-byte line size" + * "1st-level instruction cache: 8 KBytes, 4-way set + * associative, 32 byte line size" Application Note 485: + * "1st-level instruction cache: 8-KB, 4-way set + * associative, 32-byte line size" */ - cache->l1i = (struct cpuinfo_x86_cache) { + cache->l1i = (struct cpuinfo_x86_cache){ .size = 8 * 1024, .associativity = 4, .sets = 64, @@ -115,11 +119,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x08: /* * Intel ISA Reference: - * "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size" - * Application Note 485: - * "1st-level instruction cache: 16-KB, 4-way set associative, 32-byte line size" + * "1st-level instruction cache: 16 KBytes, 4-way + * set associative, 32 byte line size" Application Note + * 485: "1st-level instruction cache: 16-KB, 4-way set + * associative, 32-byte line size" */ - cache->l1i = (struct cpuinfo_x86_cache) { + cache->l1i = (struct cpuinfo_x86_cache){ .size = 16 * 1024, .associativity = 4, .sets = 128, @@ -130,11 +135,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x09: /* * Intel ISA Reference: - * "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size" - * Application Note 485: - * "1st-level Instruction Cache: 32-KB, 4-way set associative, 64-byte line size" + * "1st-level instruction cache: 32KBytes, 4-way set + * associative, 64 byte line size" Application Note 485: + * "1st-level Instruction Cache: 32-KB, 4-way set + * associative, 64-byte line size" */ - cache->l1i = (struct cpuinfo_x86_cache) { + cache->l1i = (struct cpuinfo_x86_cache){ .size = 32 * 1024, .associativity = 4, .sets = 128, @@ -145,11 +151,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x0A: /* * Intel ISA Reference: - * "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size" - * Application Note 485: - * "1st-level data cache: 8-KB, 2-way set associative, 32-byte line size" + * "1st-level data cache: 8 KBytes, 2-way set + * associative, 32 byte line size" Application Note 485: + * "1st-level data cache: 8-KB, 2-way set associative, + * 32-byte line size" */ - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = 8 * 1024, .associativity = 2, .sets = 128, @@ -160,11 +167,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x0B: /* * Intel ISA Reference: - * "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries" - * Application Note 485: - * "Instruction TLB: 4-MB pages, 4-way set associative, 4 entries" + * "Instruction TLB: 4 MByte pages, 4-way set + * associative, 4 entries" Application Note 485: + * "Instruction TLB: 4-MB pages, 4-way set + * associative, 4 entries" */ - *itlb_4MB = (struct cpuinfo_tlb) { + *itlb_4MB = (struct cpuinfo_tlb){ .entries = 4, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4MB, @@ -173,11 +181,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x0C: /* * Intel ISA Reference: - * "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size" - * Application Note 485: - * "1st-level data cache: 16-KB, 4-way set associative, 32-byte line size" + * "1st-level data cache: 16 KBytes, 4-way set + * associative, 32 byte line size" Application Note 485: + * "1st-level data cache: 16-KB, 4-way set associative, + * 32-byte line size" */ - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = 16 * 1024, .associativity = 4, .sets = 128, @@ -188,11 +197,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x0D: /* * Intel ISA Reference: - * "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size" - * Application Note 485: - * "1st-level Data Cache: 16-KB, 4-way set associative, 64-byte line size" + * "1st-level data cache: 16 KBytes, 4-way set + * associative, 64 byte line size" Application Note 485: + * "1st-level Data Cache: 16-KB, 4-way set associative, + * 64-byte line size" */ - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = 16 * 1024, .associativity = 4, .sets = 64, @@ -203,11 +213,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x0E: /* * Intel ISA Reference: - * "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size" - * Application Note 485: - * "1st-level Data Cache: 24-KB, 6-way set associative, 64-byte line size" + * "1st-level data cache: 24 KBytes, 6-way set + * associative, 64 byte line size" Application Note 485: + * "1st-level Data Cache: 24-KB, 6-way set associative, + * 64-byte line size" */ - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = 24 * 1024, .associativity = 6, .sets = 64, @@ -218,9 +229,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x1D: /* * Intel ISA Reference: - * "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size" + * "2nd-level cache: 128 KBytes, 2-way set + * associative, 64 byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 128 * 1024, .associativity = 2, .sets = 1024, @@ -228,14 +240,16 @@ void cpuinfo_x86_decode_cache_descriptor( .line_size = 64, .flags = CPUINFO_CACHE_INCLUSIVE, }; + break; case 0x21: /* * Intel ISA Reference: - * "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size" - * Application Note 485: - * "2nd-level cache: 256-KB, 8-way set associative, 64-byte line size" + * "2nd-level cache: 256 KBytes, 8-way set + * associative, 64 byte line size" Application Note 485: + * "2nd-level cache: 256-KB, 8-way set associative, + * 64-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 256 * 1024, .associativity = 8, .sets = 512, @@ -247,11 +261,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x22: /* * Intel ISA Reference: - * "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector" - * Application Note 485: - * "3rd-level cache: 512-KB, 4-way set associative, sectored cache, 64-byte line size" + * "3rd-level cache: 512 KBytes, 4-way set + * associative, 64 byte line size, 2 lines per sector" + * Application Note 485: "3rd-level cache: 512-KB, 4-way + * set associative, sectored cache, 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 512 * 1024, .associativity = 4, .sets = 2048, @@ -263,11 +278,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x23: /* * Intel ISA Reference: - * "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" - * Application Note 485: - * "3rd-level cache: 1-MB, 8-way set associative, sectored cache, 64-byte line size" + * "3rd-level cache: 1 MBytes, 8-way set + * associative, 64 byte line size, 2 lines per sector" + * Application Note 485: "3rd-level cache: 1-MB, 8-way + * set associative, sectored cache, 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 1024 * 1024, .associativity = 8, .sets = 2048, @@ -279,9 +295,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x24: /* * Intel ISA Reference: - * "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size" + * "2nd-level cache: 1 MBytes, 16-way set + * associative, 64 byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 1024 * 1024, .associativity = 16, .sets = 1024, @@ -293,11 +310,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x25: /* * Intel ISA Reference: - * "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" - * Application Note 485: - * "3rd-level cache: 2-MB, 8-way set associative, sectored cache, 64-byte line size" + * "3rd-level cache: 2 MBytes, 8-way set + * associative, 64 byte line size, 2 lines per sector" + * Application Note 485: "3rd-level cache: 2-MB, 8-way + * set associative, sectored cache, 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 2 * 1024 * 1024, .associativity = 8, .sets = 4096, @@ -309,11 +327,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x29: /* * Intel ISA Reference: - * "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" - * Application Note 485: - * "3rd-level cache: 4-MB, 8-way set associative, sectored cache, 64-byte line size" + * "3rd-level cache: 4 MBytes, 8-way set + * associative, 64 byte line size, 2 lines per sector" + * Application Note 485: "3rd-level cache: 4-MB, 8-way + * set associative, sectored cache, 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 4 * 1024 * 1024, .associativity = 8, .sets = 8192, @@ -325,11 +344,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x2C: /* * Intel ISA Reference: - * "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size" - * Application Note 485: - * "1st-level data cache: 32-KB, 8-way set associative, 64-byte line size" + * "1st-level data cache: 32 KBytes, 8-way set + * associative, 64 byte line size" Application Note 485: + * "1st-level data cache: 32-KB, 8-way set associative, + * 64-byte line size" */ - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = 32 * 1024, .associativity = 8, .sets = 64, @@ -340,11 +360,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x30: /* * Intel ISA Reference: - * "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size" - * Application Note 485: - * "1st-level instruction cache: 32-KB, 8-way set associative, 64-byte line size" + * "1st-level instruction cache: 32 KBytes, 8-way + * set associative, 64 byte line size" Application Note + * 485: "1st-level instruction cache: 32-KB, 8-way set + * associative, 64-byte line size" */ - cache->l1i = (struct cpuinfo_x86_cache) { + cache->l1i = (struct cpuinfo_x86_cache){ .size = 32 * 1024, .associativity = 8, .sets = 64, @@ -354,7 +375,7 @@ void cpuinfo_x86_decode_cache_descriptor( break; case 0x39: /* Where does this come from? */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 128 * 1024, .associativity = 4, .sets = 512, @@ -365,7 +386,7 @@ void cpuinfo_x86_decode_cache_descriptor( break; case 0x3A: /* Where does this come from? */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 192 * 1024, .associativity = 6, .sets = 512, @@ -376,7 +397,7 @@ void cpuinfo_x86_decode_cache_descriptor( break; case 0x3B: /* Where does this come from? */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 128 * 1024, .associativity = 2, .sets = 1024, @@ -387,7 +408,7 @@ void cpuinfo_x86_decode_cache_descriptor( break; case 0x3C: /* Where does this come from? */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 256 * 1024, .associativity = 4, .sets = 1024, @@ -398,7 +419,7 @@ void cpuinfo_x86_decode_cache_descriptor( break; case 0x3D: /* Where does this come from? */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 384 * 1024, .associativity = 6, .sets = 1024, @@ -409,7 +430,7 @@ void cpuinfo_x86_decode_cache_descriptor( break; case 0x3E: /* Where does this come from? */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 512 * 1024, .associativity = 4, .sets = 2048, @@ -421,19 +442,22 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x40: /* * Intel ISA Reference: - * "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" - * Application Note 485: - * "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" + * "No 2nd-level cache or, if processor contains a + * valid 2nd-level cache, no 3rd-level cache" + * Application Note 485: "No 2nd-level cache or, if + * processor contains a valid 2nd-level cache, no + * 3rd-level cache" */ break; case 0x41: /* * Intel ISA Reference: - * "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size" - * Application Note 485: - * "2nd-level cache: 128-KB, 4-way set associative, 32-byte line size" + * "2nd-level cache: 128 KBytes, 4-way set + * associative, 32 byte line size" Application Note 485: + * "2nd-level cache: 128-KB, 4-way set associative, + * 32-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 128 * 1024, .associativity = 4, .sets = 1024, @@ -445,11 +469,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x42: /* * Intel ISA Reference: - * "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size" - * Application Note 485: - * "2nd-level cache: 256-KB, 4-way set associative, 32-byte line size" + * "2nd-level cache: 256 KBytes, 4-way set + * associative, 32 byte line size" Application Note 485: + * "2nd-level cache: 256-KB, 4-way set associative, + * 32-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 256 * 1024, .associativity = 4, .sets = 2048, @@ -461,11 +486,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x43: /* * Intel ISA Reference: - * "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size" - * Application Note 485: - * "2nd-level cache: 512-KB, 4-way set associative, 32-byte line size" + * "2nd-level cache: 512 KBytes, 4-way set + * associative, 32 byte line size" Application Note 485: + * "2nd-level cache: 512-KB, 4-way set associative, + * 32-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 512 * 1024, .associativity = 4, .sets = 4096, @@ -477,11 +503,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x44: /* * Intel ISA Reference: - * "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size" - * Application Note 485: - * "2nd-level cache: 1-MB, 4-way set associative, 32-byte line size" + * "2nd-level cache: 1 MByte, 4-way set associative, + * 32 byte line size" Application Note 485: "2nd-level + * cache: 1-MB, 4-way set associative, 32-byte line + * size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 1024 * 1024, .associativity = 4, .sets = 8192, @@ -493,11 +520,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x45: /* * Intel ISA Reference: - * "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size" - * Application Note 485: - * "2nd-level cache: 2-MB, 4-way set associative, 32-byte line size" + * "2nd-level cache: 2 MByte, 4-way set associative, + * 32 byte line size" Application Note 485: "2nd-level + * cache: 2-MB, 4-way set associative, 32-byte line + * size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 2 * 1024 * 1024, .associativity = 4, .sets = 16384, @@ -509,11 +537,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x46: /* * Intel ISA Reference: - * "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 4-MB, 4-way set associative, 64-byte line size" + * "3rd-level cache: 4 MByte, 4-way set associative, + * 64 byte line size" Application Note 485: "3rd-level + * cache: 4-MB, 4-way set associative, 64-byte line + * size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 4 * 1024 * 1024, .associativity = 4, .sets = 16384, @@ -525,11 +554,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x47: /* * Intel ISA Reference: - * "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 8-MB, 8-way set associative, 64-byte line size" + * "3rd-level cache: 8 MByte, 8-way set associative, + * 64 byte line size" Application Note 485: "3rd-level + * cache: 8-MB, 8-way set associative, 64-byte line + * size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 8 * 1024 * 1024, .associativity = 8, .sets = 16384, @@ -541,11 +571,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x48: /* * Intel ISA Reference: - * "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size" - * Application Note 485: - * "2nd-level cache: 3-MB, 12-way set associative, 64-byte line size, unified on-die" + * "2nd-level cache: 3MByte, 12-way set associative, + * 64 byte line size" Application Note 485: "2nd-level + * cache: 3-MB, 12-way set associative, 64-byte line + * size, unified on-die" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 3 * 1024 * 1024, .associativity = 12, .sets = 4096, @@ -557,15 +588,18 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x49: /* * Intel ISA Reference: - * "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, - * Family 0FH, Model 06H); 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 4-MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, - * Family 0Fh, Model 06h) - * 2nd-level cache: 4-MB, 16-way set associative, 64-byte line size" + * "3rd-level cache: 4MB, 16-way set associative, + * 64-byte line size (Intel Xeon processor MP, Family + * 0FH, Model 06H); 2nd-level cache: 4 MByte, 16-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 4-MB, 16-way set associative, + * 64-byte line size (Intel Xeon processor MP, Family + * 0Fh, Model 06h) 2nd-level cache: 4-MB, 16-way set + * associative, 64-byte line size" */ - if ((vendor == cpuinfo_vendor_intel) && (model_info->model == 0x06) && (model_info->family == 0x0F)) { - cache->l3 = (struct cpuinfo_x86_cache) { + if ((vendor == cpuinfo_vendor_intel) && (model_info->model == 0x06) && + (model_info->family == 0x0F)) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 4 * 1024 * 1024, .associativity = 16, .sets = 4096, @@ -574,7 +608,7 @@ void cpuinfo_x86_decode_cache_descriptor( .flags = CPUINFO_CACHE_INCLUSIVE, }; } else { - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 4 * 1024 * 1024, .associativity = 16, .sets = 4096, @@ -587,11 +621,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x4A: /* * Intel ISA Reference: - * "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 6-MB, 12-way set associative, 64-byte line size" + * "3rd-level cache: 6MByte, 12-way set associative, + * 64 byte line size" Application Note 485: "3rd-level + * cache: 6-MB, 12-way set associative, 64-byte line + * size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 6 * 1024 * 1024, .associativity = 12, .sets = 8192, @@ -603,11 +638,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x4B: /* * Intel ISA Reference: - * "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 8-MB, 16-way set associative, 64-byte line size" + * "3rd-level cache: 8MByte, 16-way set associative, + * 64 byte line size" Application Note 485: "3rd-level + * cache: 8-MB, 16-way set associative, 64-byte line + * size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 8 * 1024 * 1024, .associativity = 16, .sets = 8192, @@ -619,11 +655,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x4C: /* * Intel ISA Reference: - * "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 12-MB, 12-way set associative, 64-byte line size" + * "3rd-level cache: 12MByte, 12-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 12-MB, 12-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 12 * 1024 * 1024, .associativity = 12, .sets = 16384, @@ -635,11 +672,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x4D: /* * Intel ISA Reference: - * "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 16-MB, 16-way set associative, 64-byte line size" + * "3rd-level cache: 16MByte, 16-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 16-MB, 16-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 16 * 1024 * 1024, .associativity = 16, .sets = 16384, @@ -651,11 +689,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x4E: /* * Intel ISA Reference: - * "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size" - * Application Note 485: - * "2nd-level cache: 6-MB, 24-way set associative, 64-byte line size" + * "2nd-level cache: 6MByte, 24-way set associative, + * 64 byte line size" Application Note 485: "2nd-level + * cache: 6-MB, 24-way set associative, 64-byte line + * size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 6 * 1024 * 1024, .associativity = 24, .sets = 4096, @@ -671,9 +710,11 @@ void cpuinfo_x86_decode_cache_descriptor( * Application Note 485: * "Instruction TLB: 4-KB pages, 32 entries" */ - *itlb_4KB = (struct cpuinfo_tlb) { + *itlb_4KB = (struct cpuinfo_tlb){ .entries = 32, - /* Assume full associativity from nearby entries: manual lacks detail */ + /* Assume full associativity from nearby + * entries: manual lacks detail + */ .associativity = 32, .pages = CPUINFO_PAGE_SIZE_4KB, }; @@ -681,11 +722,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x50: /* * Intel ISA Reference: - * "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries" - * Application Note 485: - * "Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 64 entries" + * "Instruction TLB: 4 KByte and 2-MByte or 4-MByte + * pages, 64 entries" Application Note 485: "Instruction + * TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 64 + * entries" */ - *itlb_4KB = *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb) { + *itlb_4KB = *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb){ .entries = 64, .associativity = 64, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, @@ -694,11 +736,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x51: /* * Intel ISA Reference: - * "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries" - * Application Note 485: - * "Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 128 entries" + * "Instruction TLB: 4 KByte and 2-MByte or 4-MByte + * pages, 128 entries" Application Note 485: + * "Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully + * associative, 128 entries" */ - *itlb_4KB = *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb) { + *itlb_4KB = *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb){ .entries = 128, .associativity = 128, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, @@ -707,11 +750,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x52: /* * Intel ISA Reference: - * "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries" - * Application Note 485: - * "Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 256 entries" + * "Instruction TLB: 4 KByte and 2-MByte or 4-MByte + * pages, 256 entries" Application Note 485: + * "Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully + * associative, 256 entries" */ - *itlb_4KB = *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb) { + *itlb_4KB = *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb){ .entries = 256, .associativity = 256, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, @@ -720,11 +764,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x55: /* * Intel ISA Reference: - * "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries" - * Application Note 485: - * "Instruction TLB: 2-MB or 4-MB pages, fully associative, 7 entries" + * "Instruction TLB: 2-MByte or 4-MByte pages, fully + * associative, 7 entries" Application Note 485: + * "Instruction TLB: 2-MB or 4-MB pages, fully + * associative, 7 entries" */ - *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb) { + *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb){ .entries = 7, .associativity = 7, .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, @@ -733,11 +778,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x56: /* * Intel ISA Reference: - * "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" - * Application Note 485: - * "L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries" + * "Data TLB0: 4 MByte pages, 4-way set associative, + * 16 entries" Application Note 485: "L1 Data TLB: 4-MB + * pages, 4-way set associative, 16 entries" */ - *dtlb0_4MB = (struct cpuinfo_tlb) { + *dtlb0_4MB = (struct cpuinfo_tlb){ .entries = 16, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4MB, @@ -746,11 +791,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x57: /* * Intel ISA Reference: - * "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" - * Application Note 485: - * "L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries" + * "Data TLB0: 4 KByte pages, 4-way associative, 16 + * entries" Application Note 485: "L1 Data TLB: 4-KB + * pages, 4-way set associative, 16 entries" */ - *dtlb0_4KB = (struct cpuinfo_tlb) { + *dtlb0_4KB = (struct cpuinfo_tlb){ .entries = 16, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -759,11 +804,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x59: /* * Intel ISA Reference: - * "Data TLB0: 4 KByte pages, fully associative, 16 entries" - * Application Note 485: - * "Data TLB0: 4-KB pages, fully associative, 16 entries" + * "Data TLB0: 4 KByte pages, fully associative, 16 + * entries" Application Note 485: "Data TLB0: 4-KB + * pages, fully associative, 16 entries" */ - *dtlb0_4KB = (struct cpuinfo_tlb) { + *dtlb0_4KB = (struct cpuinfo_tlb){ .entries = 16, .associativity = 16, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -772,11 +817,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x5A: /* * Intel ISA Reference: - * "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" - * Application Note 485: - * "Data TLB0: 2-MB or 4-MB pages, 4-way associative, 32 entries" + * "Data TLB0: 2 MByte or 4 MByte pages, 4-way set + * associative, 32 entries" Application Note 485: "Data + * TLB0: 2-MB or 4-MB pages, 4-way associative, 32 + * entries" */ - *dtlb0_2MB = *dtlb0_4MB = (struct cpuinfo_tlb) { + *dtlb0_2MB = *dtlb0_4MB = (struct cpuinfo_tlb){ .entries = 32, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, @@ -787,9 +833,10 @@ void cpuinfo_x86_decode_cache_descriptor( * Intel ISA Reference: * "Data TLB: 4 KByte and 4 MByte pages, 64 entries" * Application Note 485: - * "Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries" + * "Data TLB: 4-KB or 4-MB pages, fully associative, + * 64 entries" */ - *dtlb_4KB = *dtlb_4MB = (struct cpuinfo_tlb) { + *dtlb_4KB = *dtlb_4MB = (struct cpuinfo_tlb){ .entries = 64, .associativity = 64, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_4MB, @@ -798,11 +845,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x5C: /* * Intel ISA Reference: - * "Data TLB: 4 KByte and 4 MByte pages, 128 entries" - * Application Note 485: - * "Data TLB: 4-KB or 4-MB pages, fully associative, 128 entries" + * "Data TLB: 4 KByte and 4 MByte pages, 128 + * entries" Application Note 485: "Data TLB: 4-KB or + * 4-MB pages, fully associative, 128 entries" */ - *dtlb_4KB = *dtlb_4MB = (struct cpuinfo_tlb) { + *dtlb_4KB = *dtlb_4MB = (struct cpuinfo_tlb){ .entries = 128, .associativity = 128, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_4MB, @@ -811,11 +858,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x5D: /* * Intel ISA Reference: - * "Data TLB: 4 KByte and 4 MByte pages, 256 entries" - * Application Note 485: - * "Data TLB: 4-KB or 4-MB pages, fully associative, 256 entries" + * "Data TLB: 4 KByte and 4 MByte pages, 256 + * entries" Application Note 485: "Data TLB: 4-KB or + * 4-MB pages, fully associative, 256 entries" */ - *dtlb_4KB = *dtlb_4MB = (struct cpuinfo_tlb) { + *dtlb_4KB = *dtlb_4MB = (struct cpuinfo_tlb){ .entries = 256, .associativity = 256, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_4MB, @@ -824,9 +871,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x60: /* * Application Note 485: - * "1st-level data cache: 16-KB, 8-way set associative, sectored cache, 64-byte line size" + * "1st-level data cache: 16-KB, 8-way set + * associative, sectored cache, 64-byte line size" */ - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = 16 * 1024, .associativity = 8, .sets = 32, @@ -837,9 +885,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x61: /* * Intel ISA Reference: - * "Instruction TLB: 4 KByte pages, fully associative, 48 entries" + * "Instruction TLB: 4 KByte pages, fully + * associative, 48 entries" */ - *itlb_4KB = (struct cpuinfo_tlb) { + *itlb_4KB = (struct cpuinfo_tlb){ .entries = 48, .associativity = 48, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -848,15 +897,16 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x63: /* * Intel ISA Reference: - * "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and - * a separate array with 1 GByte pages, 4-way set associative, 4 entries" + * "Data TLB: 2 MByte or 4 MByte pages, 4-way set + * associative, 32 entries and a separate array with 1 + * GByte pages, 4-way set associative, 4 entries" */ - *dtlb_2MB = *dtlb_4MB = (struct cpuinfo_tlb) { + *dtlb_2MB = *dtlb_4MB = (struct cpuinfo_tlb){ .entries = 32, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, }; - *dtlb_1GB = (struct cpuinfo_tlb) { + *dtlb_1GB = (struct cpuinfo_tlb){ .entries = 4, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_1GB, @@ -865,10 +915,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x64: /* * Intel ISA Reference: - * "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" + * "Data TLB: 4 KByte pages, 4-way set associative, + * 512 entries" * */ - *dtlb_4KB = (struct cpuinfo_tlb) { + *dtlb_4KB = (struct cpuinfo_tlb){ .entries = 512, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -877,9 +928,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x66: /* * Application Note 485: - * "1st-level data cache: 8-KB, 4-way set associative, sectored cache, 64-byte line size" + * "1st-level data cache: 8-KB, 4-way set + * associative, sectored cache, 64-byte line size" */ - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = 8 * 1024, .associativity = 4, .sets = 32, @@ -890,9 +942,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x67: /* * Application Note 485: - * "1st-level data cache: 16-KB, 4-way set associative, sectored cache, 64-byte line size" + * "1st-level data cache: 16-KB, 4-way set + * associative, sectored cache, 64-byte line size" */ - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = 16 * 1024, .associativity = 4, .sets = 64, @@ -903,9 +956,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x68: /* * Application Note 485: - * "1st-level data cache: 32-KB, 4 way set associative, sectored cache, 64-byte line size" + * "1st-level data cache: 32-KB, 4 way set + * associative, sectored cache, 64-byte line size" */ - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = 32 * 1024, .associativity = 4, .sets = 128, @@ -916,11 +970,14 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x6A: /* * Intel ISA Reference: - * "uTLB: 4 KByte pages, 8-way set associative, 64 entries" + * "uTLB: 4 KByte pages, 8-way set associative, 64 + * entries" */ - /* uTLB is, an fact, a normal 1-level DTLB on Silvermont & Knoghts Landing */ - *dtlb_4KB = (struct cpuinfo_tlb) { + /* uTLB is, an fact, a normal 1-level DTLB on Silvermont + * & Knoghts Landing + */ + *dtlb_4KB = (struct cpuinfo_tlb){ .entries = 64, .associativity = 8, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -929,9 +986,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x6B: /* * Intel ISA Reference: - * "DTLB: 4 KByte pages, 8-way set associative, 256 entries" + * "DTLB: 4 KByte pages, 8-way set associative, 256 + * entries" */ - *dtlb_4KB = (struct cpuinfo_tlb) { + *dtlb_4KB = (struct cpuinfo_tlb){ .entries = 256, .associativity = 8, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -940,9 +998,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x6C: /* * Intel ISA Reference: - * "DTLB: 2M/4M pages, 8-way set associative, 128 entries" + * "DTLB: 2M/4M pages, 8-way set associative, 128 + * entries" */ - *dtlb_2MB = *dtlb_4MB = (struct cpuinfo_tlb) { + *dtlb_2MB = *dtlb_4MB = (struct cpuinfo_tlb){ .entries = 128, .associativity = 8, .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, @@ -951,9 +1010,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x6D: /* * Intel ISA Reference: - * "DTLB: 1 GByte pages, fully associative, 16 entries" + * "DTLB: 1 GByte pages, fully associative, 16 + * entries" */ - *dtlb_1GB = (struct cpuinfo_tlb) { + *dtlb_1GB = (struct cpuinfo_tlb){ .entries = 16, .associativity = 16, .pages = CPUINFO_PAGE_SIZE_1GB, @@ -965,14 +1025,15 @@ void cpuinfo_x86_decode_cache_descriptor( * "Trace cache: 12 K-uop, 8-way set associative" * Application Note 485: * "Trace cache: 12K-uops, 8-way set associative" - * Cyrix CPU Detection Guide and Geode GX1 Processor Series: - * "TLB, 32 entries, 4-way set associative, 4K-Byte Pages" + * Cyrix CPU Detection Guide and Geode GX1 Processor + * Series: "TLB, 32 entries, 4-way set associative, + * 4K-Byte Pages" */ switch (vendor) { #if CPUINFO_ARCH_X86 case cpuinfo_vendor_cyrix: case cpuinfo_vendor_nsc: - *dtlb_4KB = *itlb_4KB = (struct cpuinfo_tlb) { + *dtlb_4KB = *itlb_4KB = (struct cpuinfo_tlb){ .entries = 32, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -980,7 +1041,7 @@ void cpuinfo_x86_decode_cache_descriptor( break; #endif /* CPUINFO_ARCH_X86 */ default: - cache->trace = (struct cpuinfo_trace_cache) { + cache->trace = (struct cpuinfo_trace_cache){ .uops = 12 * 1024, .associativity = 8, }; @@ -993,7 +1054,7 @@ void cpuinfo_x86_decode_cache_descriptor( * Application Note 485: * "Trace cache: 16K-uops, 8-way set associative" */ - cache->trace = (struct cpuinfo_trace_cache) { + cache->trace = (struct cpuinfo_trace_cache){ .uops = 16 * 1024, .associativity = 8, }; @@ -1005,14 +1066,14 @@ void cpuinfo_x86_decode_cache_descriptor( * Application Note 485: * "Trace cache: 32K-uops, 8-way set associative" */ - cache->trace = (struct cpuinfo_trace_cache) { + cache->trace = (struct cpuinfo_trace_cache){ .uops = 32 * 1024, .associativity = 8, }; break; case 0x73: /* Where does this come from? */ - cache->trace = (struct cpuinfo_trace_cache) { + cache->trace = (struct cpuinfo_trace_cache){ .uops = 64 * 1024, .associativity = 8, }; @@ -1020,11 +1081,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x76: /* * Intel ISA Reference: - * "Instruction TLB: 2M/4M pages, fully associative, 8 entries" - * Application Note 485: - * "Instruction TLB: 2M/4M pages, fully associative, 8 entries" + * "Instruction TLB: 2M/4M pages, fully associative, + * 8 entries" Application Note 485: "Instruction TLB: + * 2M/4M pages, fully associative, 8 entries" */ - *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb) { + *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb){ .entries = 8, .associativity = 8, .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, @@ -1033,11 +1094,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x78: /* * Intel ISA Reference: - * "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size" - * Application Note 485: - * "2nd-level cache: 1-MB, 4-way set associative, 64-byte line size" + * "2nd-level cache: 1 MByte, 4-way set associative, + * 64byte line size" Application Note 485: "2nd-level + * cache: 1-MB, 4-way set associative, 64-byte line + * size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 1024 * 1024, .associativity = 4, .sets = 4096, @@ -1049,11 +1111,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x79: /* * Intel ISA Reference: - * "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" - * Application Note 485: - * "2nd-level cache: 128-KB, 8-way set associative, sectored cache, 64-byte line size" + * "2nd-level cache: 128 KByte, 8-way set + * associative, 64 byte line size, 2 lines per sector" + * Application Note 485: "2nd-level cache: 128-KB, 8-way + * set associative, sectored cache, 64-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 128 * 1024, .associativity = 8, .sets = 256, @@ -1065,11 +1128,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x7A: /* * Intel ISA Reference: - * "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" - * Application Note 485: - * "2nd-level cache: 256-KB, 8-way set associative, sectored cache, 64-byte line size" + * "2nd-level cache: 256 KByte, 8-way set + * associative, 64 byte line size, 2 lines per sector" + * Application Note 485: "2nd-level cache: 256-KB, 8-way + * set associative, sectored cache, 64-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 256 * 1024, .associativity = 8, .sets = 512, @@ -1081,11 +1145,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x7B: /* * Intel ISA Reference: - * "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" - * Application Note 485: - * "2nd-level cache: 512-KB, 8-way set associative, sectored cache, 64-byte line size" + * "2nd-level cache: 512 KByte, 8-way set + * associative, 64 byte line size, 2 lines per sector" + * Application Note 485: "2nd-level cache: 512-KB, 8-way + * set associative, sectored cache, 64-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 512 * 1024, .associativity = 8, .sets = 1024, @@ -1097,11 +1162,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x7C: /* * Intel ISA Reference: - * "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector" - * Application Note 485: - * "2nd-level cache: 1-MB, 8-way set associative, sectored cache, 64-byte line size" + * "2nd-level cache: 1 MByte, 8-way set associative, + * 64 byte line size, 2 lines per sector" Application + * Note 485: "2nd-level cache: 1-MB, 8-way set + * associative, sectored cache, 64-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 1024 * 1024, .associativity = 8, .sets = 2048, @@ -1113,11 +1179,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x7D: /* * Intel ISA Reference: - * "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size" - * Application Note 485: - * "2nd-level cache: 2-MB, 8-way set associative, 64-byte line size" + * "2nd-level cache: 2 MByte, 8-way set associative, + * 64byte line size" Application Note 485: "2nd-level + * cache: 2-MB, 8-way set associative, 64-byte line + * size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 2 * 1024 * 1024, .associativity = 8, .sets = 4096, @@ -1129,11 +1196,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x7F: /* * Intel ISA Reference: - * "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size" - * Application Note 485: - * "2nd-level cache: 512-KB, 2-way set associative, 64-byte line size" + * "2nd-level cache: 512 KByte, 2-way set + * associative, 64-byte line size" Application Note 485: + * "2nd-level cache: 512-KB, 2-way set associative, + * 64-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 512 * 1024, .associativity = 2, .sets = 4096, @@ -1145,17 +1213,18 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x80: /* * Intel ISA Reference: - * "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size" - * Application Note 485: - * "2nd-level cache: 512-KB, 8-way set associative, 64-byte line size" - * Cyrix CPU Detection Guide and Geode GX1 Processor Series: - * "Level 1 Cache, 16K, 4-way set associative, 16 Bytes/Line" + * "2nd-level cache: 512 KByte, 8-way set + * associative, 64-byte line size" Application Note 485: + * "2nd-level cache: 512-KB, 8-way set associative, + * 64-byte line size" Cyrix CPU Detection Guide and + * Geode GX1 Processor Series: "Level 1 Cache, 16K, + * 4-way set associative, 16 Bytes/Line" */ switch (vendor) { #if CPUINFO_ARCH_X86 && !defined(__ANDROID__) case cpuinfo_vendor_cyrix: case cpuinfo_vendor_nsc: - cache->l1i = cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1i = cache->l1d = (struct cpuinfo_x86_cache){ .size = 16 * 1024, .associativity = 4, .sets = 256, @@ -1166,7 +1235,7 @@ void cpuinfo_x86_decode_cache_descriptor( break; #endif /* CPUINFO_ARCH_X86 */ default: - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 512 * 1024, .associativity = 8, .sets = 1024, @@ -1179,11 +1248,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x82: /* * Intel ISA Reference: - * "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size" - * Application Note 485: - * "2nd-level cache: 256-KB, 8-way set associative, 32-byte line size" + * "2nd-level cache: 256 KByte, 8-way set + * associative, 32 byte line size" Application Note 485: + * "2nd-level cache: 256-KB, 8-way set associative, + * 32-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 256 * 1024, .associativity = 4, .sets = 2048, @@ -1195,11 +1265,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x83: /* * Intel ISA Reference: - * "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size" - * Application Note 485: - * "2nd-level cache: 512-KB, 8-way set associative, 32-byte line size" + * "2nd-level cache: 512 KByte, 8-way set + * associative, 32 byte line size" Application Note 485: + * "2nd-level cache: 512-KB, 8-way set associative, + * 32-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 512 * 1024, .associativity = 8, .sets = 2048, @@ -1211,11 +1282,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x84: /* * Intel ISA Reference: - * "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size" - * Application Note 485: - * "2nd-level cache: 1-MB, 8-way set associative, 32-byte line size" + * "2nd-level cache: 1 MByte, 8-way set associative, + * 32 byte line size" Application Note 485: "2nd-level + * cache: 1-MB, 8-way set associative, 32-byte line + * size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 1024 * 1024, .associativity = 8, .sets = 4096, @@ -1227,11 +1299,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x85: /* * Intel ISA Reference: - * "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size" - * Application Note 485: - * "2nd-level cache: 2-MB, 8-way set associative, 32-byte line size" + * "2nd-level cache: 2 MByte, 8-way set associative, + * 32 byte line size" Application Note 485: "2nd-level + * cache: 2-MB, 8-way set associative, 32-byte line + * size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 2 * 1024 * 1024, .associativity = 8, .sets = 8192, @@ -1243,11 +1316,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x86: /* * Intel ISA Reference: - * "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size" - * Application Note 485: - * "2nd-level cache: 512-KB, 4-way set associative, 64-byte line size" + * "2nd-level cache: 512 KByte, 4-way set + * associative, 64 byte line size" Application Note 485: + * "2nd-level cache: 512-KB, 4-way set associative, + * 64-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 512 * 1024, .associativity = 4, .sets = 2048, @@ -1259,11 +1333,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x87: /* * Intel ISA Reference: - * "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size" - * Application Note 485: - * "2nd-level cache: 1-MB, 8-way set associative, 64-byte line size" + * "2nd-level cache: 1 MByte, 8-way set associative, + * 64 byte line size" Application Note 485: "2nd-level + * cache: 1-MB, 8-way set associative, 64-byte line + * size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 1024 * 1024, .associativity = 8, .sets = 2048, @@ -1277,7 +1352,7 @@ void cpuinfo_x86_decode_cache_descriptor( * Intel ISA Reference: * "DTLB: 4k pages, fully associative, 32 entries" */ - *dtlb_4KB = (struct cpuinfo_tlb) { + *dtlb_4KB = (struct cpuinfo_tlb){ .entries = 32, .associativity = 32, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -1286,11 +1361,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xB0: /* * Intel ISA Reference: - * "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries" - * Application Note 485: - * "Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries" + * "Instruction TLB: 4 KByte pages, 4-way set + * associative, 128 entries" Application Note 485: + * "Instruction TLB: 4-KB Pages, 4-way set associative, + * 128 entries" */ - *itlb_4KB = (struct cpuinfo_tlb) { + *itlb_4KB = (struct cpuinfo_tlb){ .entries = 128, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -1299,16 +1375,17 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xB1: /* * Intel ISA Reference: - * "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" - * Application Note 485: - * "Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" + * "Instruction TLB: 2M pages, 4-way, 8 entries or + * 4M pages, 4-way, 4 entries" Application Note 485: + * "Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M + * pages, 4-way, 4 entries" */ - *itlb_2MB = (struct cpuinfo_tlb) { + *itlb_2MB = (struct cpuinfo_tlb){ .entries = 8, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, }; - *itlb_4MB = (struct cpuinfo_tlb) { + *itlb_4MB = (struct cpuinfo_tlb){ .entries = 4, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, @@ -1317,11 +1394,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xB2: /* * Intel ISA Reference: - * "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries" - * Application Note 485: - * "Instruction TLB: 4-KB pages, 4-way set associative, 64 entries" + * "Instruction TLB: 4KByte pages, 4-way set + * associative, 64 entries" Application Note 485: + * "Instruction TLB: 4-KB pages, 4-way set + * associative, 64 entries" */ - *itlb_4KB = (struct cpuinfo_tlb) { + *itlb_4KB = (struct cpuinfo_tlb){ .entries = 64, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -1330,11 +1408,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xB3: /* * Intel ISA Reference: - * "Data TLB: 4 KByte pages, 4-way set associative, 128 entries" - * Application Note 485: - * "Data TLB: 4-KB Pages, 4-way set associative, 128 entries" + * "Data TLB: 4 KByte pages, 4-way set associative, + * 128 entries" Application Note 485: "Data TLB: 4-KB + * Pages, 4-way set associative, 128 entries" */ - *dtlb_4KB = (struct cpuinfo_tlb) { + *dtlb_4KB = (struct cpuinfo_tlb){ .entries = 128, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -1343,11 +1421,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xB4: /* * Intel ISA Reference: - * "Data TLB1: 4 KByte pages, 4-way associative, 256 entries" - * Application Note 485: - * "Data TLB: 4-KB Pages, 4-way set associative, 256 entries" + * "Data TLB1: 4 KByte pages, 4-way associative, 256 + * entries" Application Note 485: "Data TLB: 4-KB Pages, + * 4-way set associative, 256 entries" */ - *dtlb_4KB = (struct cpuinfo_tlb) { + *dtlb_4KB = (struct cpuinfo_tlb){ .entries = 256, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -1356,9 +1434,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xB5: /* * Intel ISA Reference: - * "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries" + * "Instruction TLB: 4KByte pages, 8-way set + * associative, 64 entries" */ - *itlb_4KB = (struct cpuinfo_tlb) { + *itlb_4KB = (struct cpuinfo_tlb){ .entries = 64, .associativity = 8, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -1367,9 +1446,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xB6: /* * Intel ISA Reference: - * "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries" + * "Instruction TLB: 4KByte pages, 8-way set + * associative, 128 entries" */ - *itlb_4KB = (struct cpuinfo_tlb) { + *itlb_4KB = (struct cpuinfo_tlb){ .entries = 128, .associativity = 8, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -1378,11 +1458,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xBA: /* * Intel ISA Reference: - * "Data TLB1: 4 KByte pages, 4-way associative, 64 entries" - * Application Note 485: - * "Data TLB: 4-KB Pages, 4-way set associative, 64 entries" + * "Data TLB1: 4 KByte pages, 4-way associative, 64 + * entries" Application Note 485: "Data TLB: 4-KB Pages, + * 4-way set associative, 64 entries" */ - *itlb_4KB = (struct cpuinfo_tlb) { + *itlb_4KB = (struct cpuinfo_tlb){ .entries = 64, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -1391,11 +1471,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xC0: /* * Intel ISA Reference: - * "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries" - * Application Note 485: - * "Data TLB: 4-KB or 4-MB Pages, 4-way set associative, 8 entries" + * "Data TLB: 4 KByte and 4 MByte pages, 4-way + * associative, 8 entries" Application Note 485: "Data + * TLB: 4-KB or 4-MB Pages, 4-way set associative, 8 + * entries" */ - *itlb_4KB = *itlb_4MB = (struct cpuinfo_tlb) { + *itlb_4KB = *itlb_4MB = (struct cpuinfo_tlb){ .entries = 8, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_4MB, @@ -1404,9 +1485,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xC1: /* * Intel ISA Reference: - * "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" + * "Shared 2nd-Level TLB: 4 KByte/2MByte pages, + * 8-way associative, 1024 entries" */ - *stlb2_4KB = *stlb2_2MB = (struct cpuinfo_tlb) { + *stlb2_4KB = *stlb2_2MB = (struct cpuinfo_tlb){ .entries = 1024, .associativity = 8, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_2MB, @@ -1415,9 +1497,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xC2: /* * Intel ISA Reference: - * "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" + * "DTLB: 4 KByte/2 MByte pages, 4-way associative, + * 16 entries" */ - *dtlb_4KB = *dtlb_2MB = (struct cpuinfo_tlb) { + *dtlb_4KB = *dtlb_2MB = (struct cpuinfo_tlb){ .entries = 16, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_2MB, @@ -1426,15 +1509,16 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xC3: /* * Intel ISA Reference: - * "Shared 2nd-Level TLB: 4 KByte/2 MByte pages, 6-way associative, 1536 entries. - * Also 1GBbyte pages, 4-way, 16 entries." + * "Shared 2nd-Level TLB: 4 KByte/2 MByte pages, + * 6-way associative, 1536 entries. Also 1GBbyte pages, + * 4-way, 16 entries." */ - *stlb2_4KB = *stlb2_2MB = (struct cpuinfo_tlb) { + *stlb2_4KB = *stlb2_2MB = (struct cpuinfo_tlb){ .entries = 1536, .associativity = 6, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_2MB, }; - *stlb2_1GB = (struct cpuinfo_tlb) { + *stlb2_1GB = (struct cpuinfo_tlb){ .entries = 16, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_1GB, @@ -1443,9 +1527,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xC4: /* * Intel ISA Reference: - * "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" + * "DTLB: 2M/4M Byte pages, 4-way associative, 32 + * entries" */ - *dtlb_2MB = *dtlb_4MB = (struct cpuinfo_tlb) { + *dtlb_2MB = *dtlb_4MB = (struct cpuinfo_tlb){ .entries = 32, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, @@ -1454,11 +1539,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xCA: /* * Intel ISA Reference: - * "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" - * Application Note 485: - * "Shared 2nd-level TLB: 4 KB pages, 4-way set associative, 512 entries" + * "Shared 2nd-Level TLB: 4 KByte pages, 4-way + * associative, 512 entries" Application Note 485: + * "Shared 2nd-level TLB: 4 KB pages, 4-way set + * associative, 512 entries" */ - *stlb2_4KB = (struct cpuinfo_tlb) { + *stlb2_4KB = (struct cpuinfo_tlb){ .entries = 512, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -1467,11 +1553,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xD0: /* * Intel ISA Reference: - * "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 512-kB, 4-way set associative, 64-byte line size" + * "3rd-level cache: 512 KByte, 4-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 512-kB, 4-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 512 * 1024, .associativity = 4, .sets = 2048, @@ -1483,11 +1570,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xD1: /* * Intel ISA Reference: - * "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 1-MB, 4-way set associative, 64-byte line size" + * "3rd-level cache: 1 MByte, 4-way set associative, + * 64 byte line size" Application Note 485: "3rd-level + * cache: 1-MB, 4-way set associative, 64-byte line + * size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 1024 * 1024, .associativity = 4, .sets = 4096, @@ -1499,11 +1587,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xD2: /* * Intel ISA Reference: - * "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 2-MB, 4-way set associative, 64-byte line size" + * "3rd-level cache: 2 MByte, 4-way set associative, + * 64 byte line size" Application Note 485: "3rd-level + * cache: 2-MB, 4-way set associative, 64-byte line + * size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 2 * 1024 * 2014, .associativity = 4, .sets = 8192, @@ -1515,11 +1604,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xD6: /* * Intel ISA Reference: - * "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 1-MB, 8-way set associative, 64-byte line size" + * "3rd-level cache: 1 MByte, 8-way set associative, + * 64 byte line size" Application Note 485: "3rd-level + * cache: 1-MB, 8-way set associative, 64-byte line + * size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 1024 * 1024, .associativity = 8, .sets = 2048, @@ -1531,11 +1621,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xD7: /* * Intel ISA Reference: - * "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 2-MB, 8-way set associative, 64-byte line size" + * "3rd-level cache: 2 MByte, 8-way set associative, + * 64 byte line size" Application Note 485: "3rd-level + * cache: 2-MB, 8-way set associative, 64-byte line + * size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 2 * 1024 * 1024, .associativity = 8, .sets = 4096, @@ -1547,11 +1638,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xD8: /* * Intel ISA Reference: - * "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 4-MB, 8-way set associative, 64-byte line size" + * "3rd-level cache: 4 MByte, 8-way set associative, + * 64 byte line size" Application Note 485: "3rd-level + * cache: 4-MB, 8-way set associative, 64-byte line + * size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 4 * 1024 * 1024, .associativity = 8, .sets = 8192, @@ -1563,11 +1655,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xDC: /* * Intel ISA Reference: - * "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 1.5-MB, 12-way set associative, 64-byte line size" + * "3rd-level cache: 1.5 MByte, 12-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 1.5-MB, 12-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 3 * 512 * 1024, .associativity = 12, .sets = 2048, @@ -1579,11 +1672,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xDD: /* * Intel ISA Reference: - * "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 3-MB, 12-way set associative, 64-byte line size" + * "3rd-level cache: 3 MByte, 12-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 3-MB, 12-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 3 * 1024 * 1024, .associativity = 12, .sets = 4096, @@ -1595,11 +1689,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xDE: /* * Intel ISA Reference: - * "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 6-MB, 12-way set associative, 64-byte line size" + * "3rd-level cache: 6 MByte, 12-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 6-MB, 12-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 6 * 1024 * 1024, .associativity = 12, .sets = 8192, @@ -1611,11 +1706,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xE2: /* * Intel ISA Reference: - * "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 2-MB, 16-way set associative, 64-byte line size" + * "3rd-level cache: 2 MByte, 16-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 2-MB, 16-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 2 * 1024 * 1024, .associativity = 16, .sets = 2048, @@ -1627,11 +1723,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xE3: /* * Intel ISA Reference: - * "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 4-MB, 16-way set associative, 64-byte line size" + * "3rd-level cache: 4 MByte, 16-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 4-MB, 16-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 4 * 1024 * 1024, .associativity = 16, .sets = 4096, @@ -1643,11 +1740,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xE4: /* * Intel ISA Reference: - * "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 8-MB, 16-way set associative, 64-byte line size" + * "3rd-level cache: 8 MByte, 16-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 8-MB, 16-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 8 * 1024 * 1024, .associativity = 16, .sets = 8192, @@ -1659,11 +1757,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xEA: /* * Intel ISA Reference: - * "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 12-MB, 24-way set associative, 64-byte line size" + * "3rd-level cache: 12MByte, 24-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 12-MB, 24-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 12 * 1024 * 1024, .associativity = 24, .sets = 8192, @@ -1675,11 +1774,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xEB: /* * Intel ISA Reference: - * "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 18-MB, 24-way set associative, 64-byte line size" + * "3rd-level cache: 18MByte, 24-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 18-MB, 24-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 18 * 1024 * 1024, .associativity = 24, .sets = 12288, @@ -1691,11 +1791,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xEC: /* * Intel ISA Reference: - * "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 24-MB, 24-way set associative, 64-byte line size" + * "3rd-level cache: 24MByte, 24-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 24-MB, 24-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 24 * 1024 * 1024, .associativity = 24, .sets = 16384, diff --git a/3rdparty/cpuinfo/src/x86/cache/deterministic.c b/3rdparty/cpuinfo/src/x86/cache/deterministic.c index befd5029af..f40ee713d1 100644 --- a/3rdparty/cpuinfo/src/x86/cache/deterministic.c +++ b/3rdparty/cpuinfo/src/x86/cache/deterministic.c @@ -1,10 +1,9 @@ #include #include -#include -#include #include - +#include +#include enum cache_type { cache_type_none = 0, @@ -16,8 +15,7 @@ enum cache_type { bool cpuinfo_x86_decode_deterministic_cache_parameters( struct cpuid_regs regs, struct cpuinfo_x86_caches* cache, - uint32_t* package_cores_max) -{ + uint32_t* package_cores_max) { const uint32_t type = regs.eax & UINT32_C(0x1F); if (type == cache_type_none) { return false; @@ -46,112 +44,106 @@ bool cpuinfo_x86_decode_deterministic_cache_parameters( case 1: switch (type) { case cache_type_unified: - cache->l1d = cache->l1i = (struct cpuinfo_x86_cache) { + cache->l1d = cache->l1i = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags | CPUINFO_CACHE_UNIFIED, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; case cache_type_data: - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; case cache_type_instruction: - cache->l1i = (struct cpuinfo_x86_cache) { + cache->l1i = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; } break; case 2: switch (type) { case cache_type_instruction: - cpuinfo_log_warning("unexpected L2 instruction cache reported in leaf 0x00000004 is ignored"); + cpuinfo_log_warning( + "unexpected L2 instruction cache reported in leaf 0x00000004 is ignored"); break; case cache_type_unified: flags |= CPUINFO_CACHE_UNIFIED; case cache_type_data: - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; } break; case 3: switch (type) { case cache_type_instruction: - cpuinfo_log_warning("unexpected L3 instruction cache reported in leaf 0x00000004 is ignored"); + cpuinfo_log_warning( + "unexpected L3 instruction cache reported in leaf 0x00000004 is ignored"); break; case cache_type_unified: flags |= CPUINFO_CACHE_UNIFIED; case cache_type_data: - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; } break; case 4: switch (type) { case cache_type_instruction: - cpuinfo_log_warning("unexpected L4 instruction cache reported in leaf 0x00000004 is ignored"); + cpuinfo_log_warning( + "unexpected L4 instruction cache reported in leaf 0x00000004 is ignored"); break; case cache_type_unified: flags |= CPUINFO_CACHE_UNIFIED; case cache_type_data: - cache->l4 = (struct cpuinfo_x86_cache) { + cache->l4 = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; } break; default: - cpuinfo_log_warning("unexpected L%"PRIu32" cache reported in leaf 0x00000004 is ignored", level); + cpuinfo_log_warning( + "unexpected L%" PRIu32 " cache reported in leaf 0x00000004 is ignored", level); break; } return true; } - -bool cpuinfo_x86_decode_cache_properties( - struct cpuid_regs regs, - struct cpuinfo_x86_caches* cache) -{ +bool cpuinfo_x86_decode_cache_properties(struct cpuid_regs regs, struct cpuinfo_x86_caches* cache) { const uint32_t type = regs.eax & UINT32_C(0x1F); if (type == cache_type_none) { return false; @@ -175,82 +167,80 @@ bool cpuinfo_x86_decode_cache_properties( case 1: switch (type) { case cache_type_unified: - cache->l1d = cache->l1i = (struct cpuinfo_x86_cache) { + cache->l1d = cache->l1i = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags | CPUINFO_CACHE_UNIFIED, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; case cache_type_data: - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; case cache_type_instruction: - cache->l1i = (struct cpuinfo_x86_cache) { + cache->l1i = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; } break; case 2: switch (type) { case cache_type_instruction: - cpuinfo_log_warning("unexpected L2 instruction cache reported in leaf 0x8000001D is ignored"); + cpuinfo_log_warning( + "unexpected L2 instruction cache reported in leaf 0x8000001D is ignored"); break; case cache_type_unified: flags |= CPUINFO_CACHE_UNIFIED; case cache_type_data: - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; } break; case 3: switch (type) { case cache_type_instruction: - cpuinfo_log_warning("unexpected L3 instruction cache reported in leaf 0x8000001D is ignored"); + cpuinfo_log_warning( + "unexpected L3 instruction cache reported in leaf 0x8000001D is ignored"); break; case cache_type_unified: flags |= CPUINFO_CACHE_UNIFIED; case cache_type_data: - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; } break; default: - cpuinfo_log_warning("unexpected L%"PRIu32" cache reported in leaf 0x8000001D is ignored", level); + cpuinfo_log_warning( + "unexpected L%" PRIu32 " cache reported in leaf 0x8000001D is ignored", level); break; } return true; diff --git a/3rdparty/cpuinfo/src/x86/cache/init.c b/3rdparty/cpuinfo/src/x86/cache/init.c index dd1f1ea374..34af90e7f3 100644 --- a/3rdparty/cpuinfo/src/x86/cache/init.c +++ b/3rdparty/cpuinfo/src/x86/cache/init.c @@ -1,11 +1,10 @@ #include #include -#include #include -#include +#include #include - +#include union cpuinfo_x86_cache_descriptors { struct cpuid_regs regs; @@ -20,7 +19,8 @@ enum cache_type { }; void cpuinfo_x86_detect_cache( - uint32_t max_base_index, uint32_t max_extended_index, + uint32_t max_base_index, + uint32_t max_extended_index, bool amd_topology_extensions, enum cpuinfo_vendor vendor, const struct cpuinfo_x86_model_info* model_info, @@ -38,24 +38,34 @@ void cpuinfo_x86_detect_cache( struct cpuinfo_tlb* stlb2_4KB, struct cpuinfo_tlb* stlb2_2MB, struct cpuinfo_tlb* stlb2_1GB, - uint32_t* log2_package_cores_max) -{ + uint32_t* log2_package_cores_max) { if (max_base_index >= 2) { union cpuinfo_x86_cache_descriptors descriptors; descriptors.regs = cpuid(2); - uint32_t iterations = (uint8_t) descriptors.as_bytes[0]; + uint32_t iterations = (uint8_t)descriptors.as_bytes[0]; if (iterations != 0) { -iterate_descriptors: + iterate_descriptors: for (uint32_t i = 1 /* note: not 0 */; i < 16; i++) { const uint8_t descriptor = descriptors.as_bytes[i]; if (descriptor != 0) { cpuinfo_x86_decode_cache_descriptor( - descriptor, vendor, model_info, + descriptor, + vendor, + model_info, cache, - itlb_4KB, itlb_2MB, itlb_4MB, - dtlb0_4KB, dtlb0_2MB, dtlb0_4MB, - dtlb_4KB, dtlb_2MB, dtlb_4MB, dtlb_1GB, - stlb2_4KB, stlb2_2MB, stlb2_1GB, + itlb_4KB, + itlb_2MB, + itlb_4MB, + dtlb0_4KB, + dtlb0_2MB, + dtlb0_4MB, + dtlb_4KB, + dtlb_2MB, + dtlb_4MB, + dtlb_1GB, + stlb2_4KB, + stlb2_2MB, + stlb2_1GB, &cache->prefetch_size); } } @@ -71,8 +81,7 @@ iterate_descriptors: uint32_t package_cores_max = 0; do { leaf4 = cpuidex(4, input_ecx++); - } while (cpuinfo_x86_decode_deterministic_cache_parameters( - leaf4, cache, &package_cores_max)); + } while (cpuinfo_x86_decode_deterministic_cache_parameters(leaf4, cache, &package_cores_max)); if (package_cores_max != 0) { *log2_package_cores_max = bit_length(package_cores_max); } diff --git a/3rdparty/cpuinfo/src/x86/cpuid.h b/3rdparty/cpuinfo/src/x86/cpuid.h index 9e9e013183..0d7cf5cc48 100644 --- a/3rdparty/cpuinfo/src/x86/cpuid.h +++ b/3rdparty/cpuinfo/src/x86/cpuid.h @@ -2,78 +2,76 @@ #include #if defined(__GNUC__) - #include +#include #elif defined(_MSC_VER) - #include +#include #endif #if CPUINFO_MOCK - #include +#include #endif #include - #if defined(__GNUC__) || defined(_MSC_VER) - static inline struct cpuid_regs cpuid(uint32_t eax) { - #if CPUINFO_MOCK - uint32_t regs_array[4]; - cpuinfo_mock_get_cpuid(eax, regs_array); - return (struct cpuid_regs) { - .eax = regs_array[0], - .ebx = regs_array[1], - .ecx = regs_array[2], - .edx = regs_array[3], - }; - #else - struct cpuid_regs regs; - #if defined(__GNUC__) - __cpuid(eax, regs.eax, regs.ebx, regs.ecx, regs.edx); - #else - int regs_array[4]; - __cpuid(regs_array, (int) eax); - regs.eax = regs_array[0]; - regs.ebx = regs_array[1]; - regs.ecx = regs_array[2]; - regs.edx = regs_array[3]; - #endif - return regs; - #endif - } +static inline struct cpuid_regs cpuid(uint32_t eax) { +#if CPUINFO_MOCK + uint32_t regs_array[4]; + cpuinfo_mock_get_cpuid(eax, regs_array); + return (struct cpuid_regs){ + .eax = regs_array[0], + .ebx = regs_array[1], + .ecx = regs_array[2], + .edx = regs_array[3], + }; +#else + struct cpuid_regs regs; +#if defined(__GNUC__) + __cpuid(eax, regs.eax, regs.ebx, regs.ecx, regs.edx); +#else + int regs_array[4]; + __cpuid(regs_array, (int)eax); + regs.eax = regs_array[0]; + regs.ebx = regs_array[1]; + regs.ecx = regs_array[2]; + regs.edx = regs_array[3]; +#endif + return regs; +#endif +} - static inline struct cpuid_regs cpuidex(uint32_t eax, uint32_t ecx) { - #if CPUINFO_MOCK - uint32_t regs_array[4]; - cpuinfo_mock_get_cpuidex(eax, ecx, regs_array); - return (struct cpuid_regs) { - .eax = regs_array[0], - .ebx = regs_array[1], - .ecx = regs_array[2], - .edx = regs_array[3], - }; - #else - struct cpuid_regs regs; - #if defined(__GNUC__) - __cpuid_count(eax, ecx, regs.eax, regs.ebx, regs.ecx, regs.edx); - #else - int regs_array[4]; - __cpuidex(regs_array, (int) eax, (int) ecx); - regs.eax = regs_array[0]; - regs.ebx = regs_array[1]; - regs.ecx = regs_array[2]; - regs.edx = regs_array[3]; - #endif - return regs; - #endif - } +static inline struct cpuid_regs cpuidex(uint32_t eax, uint32_t ecx) { +#if CPUINFO_MOCK + uint32_t regs_array[4]; + cpuinfo_mock_get_cpuidex(eax, ecx, regs_array); + return (struct cpuid_regs){ + .eax = regs_array[0], + .ebx = regs_array[1], + .ecx = regs_array[2], + .edx = regs_array[3], + }; +#else + struct cpuid_regs regs; +#if defined(__GNUC__) + __cpuid_count(eax, ecx, regs.eax, regs.ebx, regs.ecx, regs.edx); +#else + int regs_array[4]; + __cpuidex(regs_array, (int)eax, (int)ecx); + regs.eax = regs_array[0]; + regs.ebx = regs_array[1]; + regs.ecx = regs_array[2]; + regs.edx = regs_array[3]; +#endif + return regs; +#endif +} #endif static inline uint64_t xgetbv(uint32_t ext_ctrl_reg) { - #ifdef _MSC_VER - return (uint64_t)_xgetbv((unsigned int)ext_ctrl_reg); - #else - uint32_t lo, hi; - __asm__(".byte 0x0F, 0x01, 0xD0" : "=a" (lo), "=d" (hi) : "c" (ext_ctrl_reg)); - return ((uint64_t) hi << 32) | (uint64_t) lo; - #endif +#ifdef _MSC_VER + return (uint64_t)_xgetbv((unsigned int)ext_ctrl_reg); +#else + uint32_t lo, hi; + __asm__(".byte 0x0F, 0x01, 0xD0" : "=a"(lo), "=d"(hi) : "c"(ext_ctrl_reg)); + return ((uint64_t)hi << 32) | (uint64_t)lo; +#endif } - diff --git a/3rdparty/cpuinfo/src/x86/freebsd/init.c b/3rdparty/cpuinfo/src/x86/freebsd/init.c new file mode 100644 index 0000000000..c6c6d7533b --- /dev/null +++ b/3rdparty/cpuinfo/src/x86/freebsd/init.c @@ -0,0 +1,382 @@ +#include +#include +#include + +#include +#include +#include +#include +#include + +static inline uint32_t max(uint32_t a, uint32_t b) { + return a > b ? a : b; +} + +static inline uint32_t bit_mask(uint32_t bits) { + return (UINT32_C(1) << bits) - UINT32_C(1); +} + +void cpuinfo_x86_freebsd_init(void) { + struct cpuinfo_processor* processors = NULL; + struct cpuinfo_core* cores = NULL; + struct cpuinfo_cluster* clusters = NULL; + struct cpuinfo_package* packages = NULL; + struct cpuinfo_cache* l1i = NULL; + struct cpuinfo_cache* l1d = NULL; + struct cpuinfo_cache* l2 = NULL; + struct cpuinfo_cache* l3 = NULL; + struct cpuinfo_cache* l4 = NULL; + + struct cpuinfo_freebsd_topology freebsd_topology = cpuinfo_freebsd_detect_topology(); + if (freebsd_topology.packages == 0) { + cpuinfo_log_error("failed to detect topology"); + goto cleanup; + } + processors = calloc(freebsd_topology.threads, sizeof(struct cpuinfo_processor)); + if (processors == NULL) { + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " logical processors", + freebsd_topology.threads * sizeof(struct cpuinfo_processor), + freebsd_topology.threads); + goto cleanup; + } + cores = calloc(freebsd_topology.cores, sizeof(struct cpuinfo_core)); + if (cores == NULL) { + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " cores", + freebsd_topology.cores * sizeof(struct cpuinfo_core), + freebsd_topology.cores); + goto cleanup; + } + /* On x86 a cluster of cores is the biggest group of cores that shares a + * cache. */ + clusters = calloc(freebsd_topology.packages, sizeof(struct cpuinfo_cluster)); + if (clusters == NULL) { + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " core clusters", + freebsd_topology.packages * sizeof(struct cpuinfo_cluster), + freebsd_topology.packages); + goto cleanup; + } + packages = calloc(freebsd_topology.packages, sizeof(struct cpuinfo_package)); + if (packages == NULL) { + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " physical packages", + freebsd_topology.packages * sizeof(struct cpuinfo_package), + freebsd_topology.packages); + goto cleanup; + } + + struct cpuinfo_x86_processor x86_processor; + memset(&x86_processor, 0, sizeof(x86_processor)); + cpuinfo_x86_init_processor(&x86_processor); + char brand_string[48]; + cpuinfo_x86_normalize_brand_string(x86_processor.brand_string, brand_string); + + const uint32_t threads_per_core = freebsd_topology.threads_per_core; + const uint32_t threads_per_package = freebsd_topology.threads / freebsd_topology.packages; + const uint32_t cores_per_package = freebsd_topology.cores / freebsd_topology.packages; + for (uint32_t i = 0; i < freebsd_topology.packages; i++) { + clusters[i] = (struct cpuinfo_cluster){ + .processor_start = i * threads_per_package, + .processor_count = threads_per_package, + .core_start = i * cores_per_package, + .core_count = cores_per_package, + .cluster_id = 0, + .package = packages + i, + .vendor = x86_processor.vendor, + .uarch = x86_processor.uarch, + .cpuid = x86_processor.cpuid, + }; + packages[i].processor_start = i * threads_per_package; + packages[i].processor_count = threads_per_package; + packages[i].core_start = i * cores_per_package; + packages[i].core_count = cores_per_package; + packages[i].cluster_start = i; + packages[i].cluster_count = 1; + cpuinfo_x86_format_package_name(x86_processor.vendor, brand_string, packages[i].name); + } + for (uint32_t i = 0; i < freebsd_topology.cores; i++) { + cores[i] = (struct cpuinfo_core){ + .processor_start = i * threads_per_core, + .processor_count = threads_per_core, + .core_id = i % cores_per_package, + .cluster = clusters + i / cores_per_package, + .package = packages + i / cores_per_package, + .vendor = x86_processor.vendor, + .uarch = x86_processor.uarch, + .cpuid = x86_processor.cpuid, + }; + } + for (uint32_t i = 0; i < freebsd_topology.threads; i++) { + const uint32_t smt_id = i % threads_per_core; + const uint32_t core_id = i / threads_per_core; + const uint32_t package_id = i / threads_per_package; + + /* Reconstruct APIC IDs from topology components */ + const uint32_t thread_bits_mask = bit_mask(x86_processor.topology.thread_bits_length); + const uint32_t core_bits_mask = bit_mask(x86_processor.topology.core_bits_length); + const uint32_t package_bits_offset = + max(x86_processor.topology.thread_bits_offset + x86_processor.topology.thread_bits_length, + x86_processor.topology.core_bits_offset + x86_processor.topology.core_bits_length); + const uint32_t apic_id = ((smt_id & thread_bits_mask) << x86_processor.topology.thread_bits_offset) | + ((core_id & core_bits_mask) << x86_processor.topology.core_bits_offset) | + (package_id << package_bits_offset); + cpuinfo_log_debug("reconstructed APIC ID 0x%08" PRIx32 " for thread %" PRIu32, apic_id, i); + + processors[i].smt_id = smt_id; + processors[i].core = cores + i / threads_per_core; + processors[i].cluster = clusters + i / threads_per_package; + processors[i].package = packages + i / threads_per_package; + processors[i].apic_id = apic_id; + } + + uint32_t threads_per_l1 = 0, l1_count = 0; + if (x86_processor.cache.l1i.size != 0 || x86_processor.cache.l1d.size != 0) { + /* Assume that threads on the same core share L1 */ + threads_per_l1 = freebsd_topology.threads / freebsd_topology.cores; + cpuinfo_log_warning( + "freebsd kernel did not report number of " + "threads sharing L1 cache; assume %" PRIu32, + threads_per_l1); + l1_count = freebsd_topology.threads / threads_per_l1; + cpuinfo_log_debug("detected %" PRIu32 " L1 caches", l1_count); + } + + uint32_t threads_per_l2 = 0, l2_count = 0; + if (x86_processor.cache.l2.size != 0) { + if (x86_processor.cache.l3.size != 0) { + /* This is not a last-level cache; assume that threads + * on the same core share L2 */ + threads_per_l2 = freebsd_topology.threads / freebsd_topology.cores; + } else { + /* This is a last-level cache; assume that threads on + * the same package share L2 */ + threads_per_l2 = freebsd_topology.threads / freebsd_topology.packages; + } + cpuinfo_log_warning( + "freebsd kernel did not report number of " + "threads sharing L2 cache; assume %" PRIu32, + threads_per_l2); + l2_count = freebsd_topology.threads / threads_per_l2; + cpuinfo_log_debug("detected %" PRIu32 " L2 caches", l2_count); + } + + uint32_t threads_per_l3 = 0, l3_count = 0; + if (x86_processor.cache.l3.size != 0) { + /* + * Assume that threads on the same package share L3. + * However, is it not necessarily the last-level cache (there + * may be L4 cache as well) + */ + threads_per_l3 = freebsd_topology.threads / freebsd_topology.packages; + cpuinfo_log_warning( + "freebsd kernel did not report number of " + "threads sharing L3 cache; assume %" PRIu32, + threads_per_l3); + l3_count = freebsd_topology.threads / threads_per_l3; + cpuinfo_log_debug("detected %" PRIu32 " L3 caches", l3_count); + } + + uint32_t threads_per_l4 = 0, l4_count = 0; + if (x86_processor.cache.l4.size != 0) { + /* + * Assume that all threads share this L4. + * As of now, L4 cache exists only on notebook x86 CPUs, which + * are single-package, but multi-socket systems could have + * shared L4 (like on IBM POWER8). + */ + threads_per_l4 = freebsd_topology.threads; + cpuinfo_log_warning( + "freebsd kernel did not report number of " + "threads sharing L4 cache; assume %" PRIu32, + threads_per_l4); + l4_count = freebsd_topology.threads / threads_per_l4; + cpuinfo_log_debug("detected %" PRIu32 " L4 caches", l4_count); + } + + if (x86_processor.cache.l1i.size != 0) { + l1i = calloc(l1_count, sizeof(struct cpuinfo_cache)); + if (l1i == NULL) { + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of " + "%" PRIu32 " L1I caches", + l1_count * sizeof(struct cpuinfo_cache), + l1_count); + return; + } + for (uint32_t c = 0; c < l1_count; c++) { + l1i[c] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l1i.size, + .associativity = x86_processor.cache.l1i.associativity, + .sets = x86_processor.cache.l1i.sets, + .partitions = x86_processor.cache.l1i.partitions, + .line_size = x86_processor.cache.l1i.line_size, + .flags = x86_processor.cache.l1i.flags, + .processor_start = c * threads_per_l1, + .processor_count = threads_per_l1, + }; + } + for (uint32_t t = 0; t < freebsd_topology.threads; t++) { + processors[t].cache.l1i = &l1i[t / threads_per_l1]; + } + } + + if (x86_processor.cache.l1d.size != 0) { + l1d = calloc(l1_count, sizeof(struct cpuinfo_cache)); + if (l1d == NULL) { + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of " + "%" PRIu32 " L1D caches", + l1_count * sizeof(struct cpuinfo_cache), + l1_count); + return; + } + for (uint32_t c = 0; c < l1_count; c++) { + l1d[c] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l1d.size, + .associativity = x86_processor.cache.l1d.associativity, + .sets = x86_processor.cache.l1d.sets, + .partitions = x86_processor.cache.l1d.partitions, + .line_size = x86_processor.cache.l1d.line_size, + .flags = x86_processor.cache.l1d.flags, + .processor_start = c * threads_per_l1, + .processor_count = threads_per_l1, + }; + } + for (uint32_t t = 0; t < freebsd_topology.threads; t++) { + processors[t].cache.l1d = &l1d[t / threads_per_l1]; + } + } + + if (l2_count != 0) { + l2 = calloc(l2_count, sizeof(struct cpuinfo_cache)); + if (l2 == NULL) { + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of " + "%" PRIu32 " L2 caches", + l2_count * sizeof(struct cpuinfo_cache), + l2_count); + return; + } + for (uint32_t c = 0; c < l2_count; c++) { + l2[c] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l2.size, + .associativity = x86_processor.cache.l2.associativity, + .sets = x86_processor.cache.l2.sets, + .partitions = x86_processor.cache.l2.partitions, + .line_size = x86_processor.cache.l2.line_size, + .flags = x86_processor.cache.l2.flags, + .processor_start = c * threads_per_l2, + .processor_count = threads_per_l2, + }; + } + for (uint32_t t = 0; t < freebsd_topology.threads; t++) { + processors[t].cache.l2 = &l2[t / threads_per_l2]; + } + } + + if (l3_count != 0) { + l3 = calloc(l3_count, sizeof(struct cpuinfo_cache)); + if (l3 == NULL) { + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of " + "%" PRIu32 " L3 caches", + l3_count * sizeof(struct cpuinfo_cache), + l3_count); + return; + } + for (uint32_t c = 0; c < l3_count; c++) { + l3[c] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l3.size, + .associativity = x86_processor.cache.l3.associativity, + .sets = x86_processor.cache.l3.sets, + .partitions = x86_processor.cache.l3.partitions, + .line_size = x86_processor.cache.l3.line_size, + .flags = x86_processor.cache.l3.flags, + .processor_start = c * threads_per_l3, + .processor_count = threads_per_l3, + }; + } + for (uint32_t t = 0; t < freebsd_topology.threads; t++) { + processors[t].cache.l3 = &l3[t / threads_per_l3]; + } + } + + if (l4_count != 0) { + l4 = calloc(l4_count, sizeof(struct cpuinfo_cache)); + if (l4 == NULL) { + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of " + "%" PRIu32 " L4 caches", + l4_count * sizeof(struct cpuinfo_cache), + l4_count); + return; + } + for (uint32_t c = 0; c < l4_count; c++) { + l4[c] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l4.size, + .associativity = x86_processor.cache.l4.associativity, + .sets = x86_processor.cache.l4.sets, + .partitions = x86_processor.cache.l4.partitions, + .line_size = x86_processor.cache.l4.line_size, + .flags = x86_processor.cache.l4.flags, + .processor_start = c * threads_per_l4, + .processor_count = threads_per_l4, + }; + } + for (uint32_t t = 0; t < freebsd_topology.threads; t++) { + processors[t].cache.l4 = &l4[t / threads_per_l4]; + } + } + + /* Commit changes */ + cpuinfo_processors = processors; + cpuinfo_cores = cores; + cpuinfo_clusters = clusters; + cpuinfo_packages = packages; + cpuinfo_cache[cpuinfo_cache_level_1i] = l1i; + cpuinfo_cache[cpuinfo_cache_level_1d] = l1d; + cpuinfo_cache[cpuinfo_cache_level_2] = l2; + cpuinfo_cache[cpuinfo_cache_level_3] = l3; + cpuinfo_cache[cpuinfo_cache_level_4] = l4; + + cpuinfo_processors_count = freebsd_topology.threads; + cpuinfo_cores_count = freebsd_topology.cores; + cpuinfo_clusters_count = freebsd_topology.packages; + cpuinfo_packages_count = freebsd_topology.packages; + cpuinfo_cache_count[cpuinfo_cache_level_1i] = l1_count; + cpuinfo_cache_count[cpuinfo_cache_level_1d] = l1_count; + cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; + cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; + cpuinfo_cache_count[cpuinfo_cache_level_4] = l4_count; + cpuinfo_max_cache_size = cpuinfo_compute_max_cache_size(&processors[0]); + + cpuinfo_global_uarch = (struct cpuinfo_uarch_info){ + .uarch = x86_processor.uarch, + .cpuid = x86_processor.cpuid, + .processor_count = freebsd_topology.threads, + .core_count = freebsd_topology.cores, + }; + + __sync_synchronize(); + + cpuinfo_is_initialized = true; + + processors = NULL; + cores = NULL; + clusters = NULL; + packages = NULL; + l1i = l1d = l2 = l3 = l4 = NULL; + +cleanup: + free(processors); + free(cores); + free(clusters); + free(packages); + free(l1i); + free(l1d); + free(l2); + free(l3); + free(l4); +} diff --git a/3rdparty/cpuinfo/src/x86/info.c b/3rdparty/cpuinfo/src/x86/info.c index ceb6b84576..bd761cdb51 100644 --- a/3rdparty/cpuinfo/src/x86/info.c +++ b/3rdparty/cpuinfo/src/x86/info.c @@ -3,17 +3,16 @@ #include #include - struct cpuinfo_x86_model_info cpuinfo_x86_decode_model_info(uint32_t eax) { struct cpuinfo_x86_model_info model_info; - model_info.stepping = eax & 0xF; - model_info.base_model = (eax >> 4) & 0xF; - model_info.base_family = (eax >> 8) & 0xF; - model_info.processor_type = (eax >> 12) & 0x3; - model_info.extended_model = (eax >> 16) & 0xF; + model_info.stepping = eax & 0xF; + model_info.base_model = (eax >> 4) & 0xF; + model_info.base_family = (eax >> 8) & 0xF; + model_info.processor_type = (eax >> 12) & 0x3; + model_info.extended_model = (eax >> 16) & 0xF; model_info.extended_family = (eax >> 20) & 0xFF; model_info.family = model_info.base_family + model_info.extended_family; - model_info.model = model_info.base_model + (model_info.extended_model << 4); + model_info.model = model_info.base_model + (model_info.extended_model << 4); return model_info; } diff --git a/3rdparty/cpuinfo/src/x86/init.c b/3rdparty/cpuinfo/src/x86/init.c index 244359cdda..adc5d361b3 100644 --- a/3rdparty/cpuinfo/src/x86/init.c +++ b/3rdparty/cpuinfo/src/x86/init.c @@ -2,14 +2,13 @@ #include #include -#include -#include -#include -#include #include +#include +#include +#include +#include - -struct cpuinfo_x86_isa cpuinfo_isa = { 0 }; +struct cpuinfo_x86_isa cpuinfo_isa = {0}; CPUINFO_INTERNAL uint32_t cpuinfo_x86_clflush_size = 0; void cpuinfo_x86_init_processor(struct cpuinfo_x86_processor* processor) { @@ -19,30 +18,34 @@ void cpuinfo_x86_init_processor(struct cpuinfo_x86_processor* processor) { cpuinfo_x86_decode_vendor(leaf0.ebx, leaf0.ecx, leaf0.edx); const struct cpuid_regs leaf0x80000000 = cpuid(UINT32_C(0x80000000)); - const uint32_t max_extended_index = - leaf0x80000000.eax >= UINT32_C(0x80000000) ? leaf0x80000000.eax : 0; + const uint32_t max_extended_index = leaf0x80000000.eax >= UINT32_C(0x80000000) ? leaf0x80000000.eax : 0; - const struct cpuid_regs leaf0x80000001 = max_extended_index >= UINT32_C(0x80000001) ? - cpuid(UINT32_C(0x80000001)) : (struct cpuid_regs) { 0, 0, 0, 0 }; + const struct cpuid_regs leaf0x80000001 = max_extended_index >= UINT32_C(0x80000001) + ? cpuid(UINT32_C(0x80000001)) + : (struct cpuid_regs){0, 0, 0, 0}; if (max_base_index >= 1) { const struct cpuid_regs leaf1 = cpuid(1); processor->cpuid = leaf1.eax; const struct cpuinfo_x86_model_info model_info = cpuinfo_x86_decode_model_info(leaf1.eax); - const enum cpuinfo_uarch uarch = processor->uarch = - cpuinfo_x86_decode_uarch(vendor, &model_info); + const enum cpuinfo_uarch uarch = processor->uarch = cpuinfo_x86_decode_uarch(vendor, &model_info); cpuinfo_x86_clflush_size = ((leaf1.ebx >> 8) & UINT32_C(0x000000FF)) * 8; /* * Topology extensions support: - * - AMD: ecx[bit 22] in extended info (reserved bit on Intel CPUs). + * - AMD: ecx[bit 22] in extended info (reserved bit on Intel + * CPUs). */ const bool amd_topology_extensions = !!(leaf0x80000001.ecx & UINT32_C(0x00400000)); cpuinfo_x86_detect_cache( - max_base_index, max_extended_index, amd_topology_extensions, vendor, &model_info, + max_base_index, + max_extended_index, + amd_topology_extensions, + vendor, + &model_info, &processor->cache, &processor->tlb.itlb_4KB, &processor->tlb.itlb_2MB, @@ -61,8 +64,8 @@ void cpuinfo_x86_init_processor(struct cpuinfo_x86_processor* processor) { cpuinfo_x86_detect_topology(max_base_index, max_extended_index, leaf1, &processor->topology); - cpuinfo_isa = cpuinfo_x86_detect_isa(leaf1, leaf0x80000001, - max_base_index, max_extended_index, vendor, uarch); + cpuinfo_isa = cpuinfo_x86_detect_isa( + leaf1, leaf0x80000001, max_base_index, max_extended_index, vendor, uarch); } if (max_extended_index >= UINT32_C(0x80000004)) { struct cpuid_regs brand_string[3]; diff --git a/3rdparty/cpuinfo/src/x86/isa.c b/3rdparty/cpuinfo/src/x86/isa.c index 3f36cee148..bfd5e776b1 100644 --- a/3rdparty/cpuinfo/src/x86/isa.c +++ b/3rdparty/cpuinfo/src/x86/isa.c @@ -1,77 +1,82 @@ #include -#include #include +#include -#include #include - +#include #if CPUINFO_ARCH_X86 - #ifdef _MSC_VER - #pragma pack(push, 2) - #endif - struct fxsave_region { - uint16_t fpu_control_word; - uint16_t fpu_status_word; - uint16_t fpu_tag_word; - uint16_t fpu_opcode; - uint32_t fpu_instruction_pointer_offset; - uint32_t fpu_instruction_pointer_selector; - uint32_t fpu_operand_pointer_offset; - uint32_t fpu_operand_pointer_selector; - uint32_t mxcsr_state; - uint32_t mxcsr_mask; - uint64_t fpu_registers[8 * 2]; - uint64_t xmm_registers[8 * 2]; - uint64_t padding[28]; - } - #ifndef _MSC_VER - __attribute__((__aligned__(16), __packed__)) - #endif - ; /* end of fxsave_region structure */ - #ifdef _MSC_VER - #pragma pack(pop, 2) - #endif +#ifdef _MSC_VER +#pragma pack(push, 2) +#endif +struct fxsave_region { + uint16_t fpu_control_word; + uint16_t fpu_status_word; + uint16_t fpu_tag_word; + uint16_t fpu_opcode; + uint32_t fpu_instruction_pointer_offset; + uint32_t fpu_instruction_pointer_selector; + uint32_t fpu_operand_pointer_offset; + uint32_t fpu_operand_pointer_selector; + uint32_t mxcsr_state; + uint32_t mxcsr_mask; + uint64_t fpu_registers[8 * 2]; + uint64_t xmm_registers[8 * 2]; + uint64_t padding[28]; +} +#ifndef _MSC_VER +__attribute__((__aligned__(16), __packed__)) +#endif +; /* end of fxsave_region structure */ +#ifdef _MSC_VER +#pragma pack(pop, 2) +#endif #endif - struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( - const struct cpuid_regs basic_info, const struct cpuid_regs extended_info, - uint32_t max_base_index, uint32_t max_extended_index, - enum cpuinfo_vendor vendor, enum cpuinfo_uarch uarch) -{ - struct cpuinfo_x86_isa isa = { 0 }; + const struct cpuid_regs basic_info, + const struct cpuid_regs extended_info, + uint32_t max_base_index, + uint32_t max_extended_index, + enum cpuinfo_vendor vendor, + enum cpuinfo_uarch uarch) { + struct cpuinfo_x86_isa isa = {0}; const struct cpuid_regs structured_feature_info0 = - (max_base_index >= 7) ? cpuidex(7, 0) : (struct cpuid_regs) { 0, 0, 0, 0}; + (max_base_index >= 7) ? cpuidex(7, 0) : (struct cpuid_regs){0, 0, 0, 0}; const struct cpuid_regs structured_feature_info1 = - (max_base_index >= 7) ? cpuidex(7, 1) : (struct cpuid_regs) { 0, 0, 0, 0}; + (max_base_index >= 7) ? cpuidex(7, 1) : (struct cpuid_regs){0, 0, 0, 0}; const uint32_t processor_capacity_info_index = UINT32_C(0x80000008); - const struct cpuid_regs processor_capacity_info = - (max_extended_index >= processor_capacity_info_index) ? - cpuid(processor_capacity_info_index) : (struct cpuid_regs) { 0, 0, 0, 0 }; + const struct cpuid_regs processor_capacity_info = (max_extended_index >= processor_capacity_info_index) + ? cpuid(processor_capacity_info_index) + : (struct cpuid_regs){0, 0, 0, 0}; bool avx_regs = false, avx512_regs = false, mpx_regs = false; /* - * OSXSAVE: Operating system enabled XSAVE instructions for application use: - * - Intel, AMD: ecx[bit 26] in basic info = XSAVE/XRSTOR instructions supported by a chip. - * - Intel, AMD: ecx[bit 27] in basic info = XSAVE/XRSTOR instructions enabled by OS. + * OSXSAVE: Operating system enabled XSAVE instructions for application + * use: + * - Intel, AMD: ecx[bit 26] in basic info = XSAVE/XRSTOR instructions + * supported by a chip. + * - Intel, AMD: ecx[bit 27] in basic info = XSAVE/XRSTOR instructions + * enabled by OS. */ const uint32_t osxsave_mask = UINT32_C(0x0C000000); if ((basic_info.ecx & osxsave_mask) == osxsave_mask) { uint64_t xcr0_valid_bits = 0; if (max_base_index >= 0xD) { const struct cpuid_regs regs = cpuidex(0xD, 0); - xcr0_valid_bits = ((uint64_t) regs.edx << 32) | regs.eax; + xcr0_valid_bits = ((uint64_t)regs.edx << 32) | regs.eax; } const uint64_t xfeature_enabled_mask = xgetbv(0); /* * AVX registers: - * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 1] for low 128 bits of ymm registers - * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 2] for high 128 bits of ymm registers + * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 1] for low 128 bits + * of ymm registers + * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 2] for high 128 bits + * of ymm registers */ const uint64_t avx_regs_mask = UINT64_C(0x0000000000000006); if ((xcr0_valid_bits & avx_regs_mask) == avx_regs_mask) { @@ -80,11 +85,16 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( /* * AVX512 registers: - * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 1] for low 128 bits of zmm registers - * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 2] for bits 128-255 of zmm registers - * - Intel: XFEATURE_ENABLED_MASK[bit 5] for 8 64-bit OpMask registers (k0-k7) - * - Intel: XFEATURE_ENABLED_MASK[bit 6] for the high 256 bits of the zmm registers zmm0-zmm15 - * - Intel: XFEATURE_ENABLED_MASK[bit 7] for the 512-bit zmm registers zmm16-zmm31 + * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 1] for low 128 bits + * of zmm registers + * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 2] for bits 128-255 + * of zmm registers + * - Intel: XFEATURE_ENABLED_MASK[bit 5] for 8 64-bit OpMask + * registers (k0-k7) + * - Intel: XFEATURE_ENABLED_MASK[bit 6] for the high 256 bits + * of the zmm registers zmm0-zmm15 + * - Intel: XFEATURE_ENABLED_MASK[bit 7] for the 512-bit zmm + * registers zmm16-zmm31 */ const uint64_t avx512_regs_mask = UINT64_C(0x00000000000000E6); if ((xcr0_valid_bits & avx512_regs_mask) == avx512_regs_mask) { @@ -134,7 +144,8 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( /* * CLZERO instruction: - * - AMD: ebx[bit 0] in processor capacity info (reserved bit on Intel CPUs). + * - AMD: ebx[bit 0] in processor capacity info (reserved bit on Intel + * CPUs). */ isa.clzero = !!(processor_capacity_info.ebx & UINT32_C(0x00000001)); @@ -165,7 +176,8 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( /* * FXSAVE/FXRSTOR instructions: * - Intel, AMD: edx[bit 24] in basic info. - * - AMD: edx[bit 24] in extended info (zero bit on Intel CPUs, EMMX bit on Cyrix CPUs). + * - AMD: edx[bit 24] in extended info (zero bit on Intel CPUs, EMMX bit + * on Cyrix CPUs). */ switch (vendor) { #if CPUINFO_ARCH_X86 @@ -230,27 +242,35 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( /* * PREFETCH instruction: - * - AMD: ecx[bit 8] of extended info (one of 3dnow! prefetch instructions). - * On Intel this bit indicates PREFETCHW, but not PREFETCH support. - * - AMD: edx[bit 31] of extended info (implied by 3dnow! support). Reserved bit on Intel CPUs. - * - AMD: edx[bit 30] of extended info (implied by 3dnow!+ support). Reserved bit on Intel CPUs. - * - AMD: edx[bit 29] of extended info (x86-64 support). Does not imply PREFETCH support on non-AMD CPUs!!! + * - AMD: ecx[bit 8] of extended info (one of 3dnow! prefetch + * instructions). On Intel this bit indicates PREFETCHW, but not + * PREFETCH support. + * - AMD: edx[bit 31] of extended info (implied by 3dnow! support). + * Reserved bit on Intel CPUs. + * - AMD: edx[bit 30] of extended info (implied by 3dnow!+ support). + * Reserved bit on Intel CPUs. + * - AMD: edx[bit 29] of extended info (x86-64 support). Does not imply + * PREFETCH support on non-AMD CPUs!!! */ switch (vendor) { case cpuinfo_vendor_intel: /* * Instruction is not documented in the manual, - * and the 3dnow! prefetch CPUID bit indicates PREFETCHW instruction. + * and the 3dnow! prefetch CPUID bit indicates PREFETCHW + * instruction. */ break; case cpuinfo_vendor_amd: case cpuinfo_vendor_hygon: - isa.prefetch = !!((extended_info.ecx & UINT32_C(0x00000100)) | (extended_info.edx & UINT32_C(0xE0000000))); + isa.prefetch = + !!((extended_info.ecx & UINT32_C(0x00000100)) | + (extended_info.edx & UINT32_C(0xE0000000))); break; default: /* - * Conservatively assume, that 3dnow!/3dnow!+ support implies PREFETCH support, but - * 3dnow! prefetch CPUID bit follows Intel spec (PREFETCHW, but not PREFETCH). + * Conservatively assume, that 3dnow!/3dnow!+ support + * implies PREFETCH support, but 3dnow! prefetch CPUID + * bit follows Intel spec (PREFETCHW, but not PREFETCH). */ isa.prefetch = !!(extended_info.edx & UINT32_C(0xC0000000)); break; @@ -258,26 +278,36 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( /* * PREFETCHW instruction: - * - AMD: ecx[bit 8] of extended info (one of 3dnow! prefetch instructions). + * - AMD: ecx[bit 8] of extended info (one of 3dnow! prefetch + * instructions). * - Intel: ecx[bit 8] of extended info (PREFETCHW instruction only). - * - AMD: edx[bit 31] of extended info (implied by 3dnow! support). Reserved bit on Intel CPUs. - * - AMD: edx[bit 30] of extended info (implied by 3dnow!+ support). Reserved bit on Intel CPUs. - * - AMD: edx[bit 29] of extended info (x86-64 support). Does not imply PREFETCHW support on non-AMD CPUs!!! + * - AMD: edx[bit 31] of extended info (implied by 3dnow! support). + * Reserved bit on Intel CPUs. + * - AMD: edx[bit 30] of extended info (implied by 3dnow!+ support). + * Reserved bit on Intel CPUs. + * - AMD: edx[bit 29] of extended info (x86-64 support). Does not imply + * PREFETCHW support on non-AMD CPUs!!! */ switch (vendor) { case cpuinfo_vendor_amd: case cpuinfo_vendor_hygon: - isa.prefetchw = !!((extended_info.ecx & UINT32_C(0x00000100)) | (extended_info.edx & UINT32_C(0xE0000000))); + isa.prefetchw = + !!((extended_info.ecx & UINT32_C(0x00000100)) | + (extended_info.edx & UINT32_C(0xE0000000))); break; default: - /* Assume, that 3dnow!/3dnow!+ support implies PREFETCHW support, not implications from x86-64 support */ - isa.prefetchw = !!((extended_info.ecx & UINT32_C(0x00000100)) | (extended_info.edx & UINT32_C(0xC0000000))); + /* Assume, that 3dnow!/3dnow!+ support implies PREFETCHW + * support, not implications from x86-64 support */ + isa.prefetchw = + !!((extended_info.ecx & UINT32_C(0x00000100)) | + (extended_info.edx & UINT32_C(0xC0000000))); break; } /* * PREFETCHWT1 instruction: - * - Intel: ecx[bit 0] of structured feature info (ecx = 0). Reserved bit on AMD. + * - Intel: ecx[bit 0] of structured feature info (ecx = 0). Reserved + * bit on AMD. */ isa.prefetchwt1 = !!(structured_feature_info0.ecx & UINT32_C(0x00000001)); @@ -311,12 +341,12 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( } else { /* Detect DAZ support from masked MXCSR bits */ if (isa.sse && isa.fxsave) { - struct fxsave_region region = { 0 }; - #ifdef _MSC_VER - _fxsave(®ion); - #else - __asm__ __volatile__ ("fxsave %[region];" : [region] "+m" (region)); - #endif + struct fxsave_region region = {0}; +#ifdef _MSC_VER + _fxsave(®ion); +#else + __asm__ __volatile__("fxsave %[region];" : [region] "+m"(region)); +#endif /* * Denormals-as-zero (DAZ) flag: @@ -333,7 +363,6 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( */ isa.ssse3 = !!(basic_info.ecx & UINT32_C(0x0000200)); - /* * SSE4.1 instructions: * - Intel, AMD: ecx[bit 19] in basic info. @@ -508,6 +537,48 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( */ isa.avx512bf16 = avx512_regs && !!(structured_feature_info1.eax & UINT32_C(0x00000020)); + /* + * AMX_BF16 instructions: + * - Intel: edx[bit 22] in structured feature info (ecx = 0). + */ + isa.amx_bf16 = avx512_regs && !!(structured_feature_info0.edx & UINT32_C(0x00400000)); + + /* + * AMX_TILE instructions: + * - Intel: edx[bit 24] in structured feature info (ecx = 0). + */ + isa.amx_tile = avx512_regs && !!(structured_feature_info0.edx & UINT32_C(0x01000000)); + + /* + * AMX_INT8 instructions: + * - Intel: edx[bit 25] in structured feature info (ecx = 0). + */ + isa.amx_int8 = avx512_regs && !!(structured_feature_info0.edx & UINT32_C(0x02000000)); + + /* + * AMX_FP16 instructions: + * - Intel: eax[bit 21] in structured feature info (ecx = 1). + */ + isa.amx_fp16 = avx512_regs && !!(structured_feature_info1.eax & UINT32_C(0x00200000)); + + /* + * AVX_VNNI_INT8 instructions: + * - Intel: edx[bit 4] in structured feature info (ecx = 1). + */ + isa.avx_vnni_int8 = avx_regs && !!(structured_feature_info1.edx & UINT32_C(0x00000010)); + + /* + * AVX_VNNI_INT16 instructions: + * - Intel: edx[bit 10] in structured feature info (ecx = 1). + */ + isa.avx_vnni_int16 = avx_regs && !!(structured_feature_info1.edx & UINT32_C(0x00000400)); + + /* + * AVX_NE_CONVERT instructions: + * - Intel: edx[bit 5] in structured feature info (ecx = 1). + */ + isa.avx_ne_convert = avx_regs && !!(structured_feature_info1.edx & UINT32_C(0x00000020)); + /* * HLE instructions: * - Intel: ebx[bit 4] in structured feature info (ecx = 0). @@ -569,7 +640,8 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( #if CPUINFO_ARCH_X86_64 /* * Some early x86-64 CPUs lack LAHF & SAHF instructions. - * A special CPU feature bit must be checked to ensure their availability: + * A special CPU feature bit must be checked to ensure their + * availability: * - Intel, AMD: ecx[bit 0] in extended info. */ isa.lahf_sahf = !!(extended_info.ecx & UINT32_C(0x00000001)); @@ -674,40 +746,50 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( /* * Padlock RNG extension: - * - VIA: edx[bit 2] in padlock info = RNG exists on chip flag. - * - VIA: edx[bit 3] in padlock info = RNG enabled by OS. + * - VIA: edx[bit 2] in padlock info = RNG exists on + * chip flag. + * - VIA: edx[bit 3] in padlock info = RNG enabled by + * OS. */ const uint32_t padlock_rng_mask = UINT32_C(0x0000000C); isa.rng = (padlock_info.edx & padlock_rng_mask) == padlock_rng_mask; /* * Padlock ACE extension: - * - VIA: edx[bit 6] in padlock info = ACE exists on chip flag. - * - VIA: edx[bit 7] in padlock info = ACE enabled by OS. + * - VIA: edx[bit 6] in padlock info = ACE exists on + * chip flag. + * - VIA: edx[bit 7] in padlock info = ACE enabled by + * OS. */ const uint32_t padlock_ace_mask = UINT32_C(0x000000C0); isa.ace = (padlock_info.edx & padlock_ace_mask) == padlock_ace_mask; /* * Padlock ACE 2 extension: - * - VIA: edx[bit 8] in padlock info = ACE2 exists on chip flag. - * - VIA: edx[bit 9] in padlock info = ACE 2 enabled by OS. + * - VIA: edx[bit 8] in padlock info = ACE2 exists on + * chip flag. + * - VIA: edx[bit 9] in padlock info = ACE 2 enabled by + * OS. */ const uint32_t padlock_ace2_mask = UINT32_C(0x00000300); isa.ace2 = (padlock_info.edx & padlock_ace2_mask) == padlock_ace2_mask; /* * Padlock PHE extension: - * - VIA: edx[bit 10] in padlock info = PHE exists on chip flag. - * - VIA: edx[bit 11] in padlock info = PHE enabled by OS. + * - VIA: edx[bit 10] in padlock info = PHE exists on + * chip flag. + * - VIA: edx[bit 11] in padlock info = PHE enabled by + * OS. */ const uint32_t padlock_phe_mask = UINT32_C(0x00000C00); isa.phe = (padlock_info.edx & padlock_phe_mask) == padlock_phe_mask; /* * Padlock PMM extension: - * - VIA: edx[bit 12] in padlock info = PMM exists on chip flag. - * - VIA: edx[bit 13] in padlock info = PMM enabled by OS. + * - VIA: edx[bit 12] in padlock info = PMM exists on + * chip flag. + * - VIA: edx[bit 13] in padlock info = PMM enabled by + * OS. */ const uint32_t padlock_pmm_mask = UINT32_C(0x00003000); isa.pmm = (padlock_info.edx & padlock_pmm_mask) == padlock_pmm_mask; diff --git a/3rdparty/cpuinfo/src/x86/linux/api.h b/3rdparty/cpuinfo/src/x86/linux/api.h index 1c9485b19e..26fc5de0bf 100644 --- a/3rdparty/cpuinfo/src/x86/linux/api.h +++ b/3rdparty/cpuinfo/src/x86/linux/api.h @@ -5,9 +5,8 @@ #include #include -#include #include - +#include struct cpuinfo_x86_linux_processor { uint32_t apic_id; diff --git a/3rdparty/cpuinfo/src/x86/linux/cpuinfo.c b/3rdparty/cpuinfo/src/x86/linux/cpuinfo.c index 90ff814351..7df72aba50 100644 --- a/3rdparty/cpuinfo/src/x86/linux/cpuinfo.c +++ b/3rdparty/cpuinfo/src/x86/linux/cpuinfo.c @@ -1,25 +1,21 @@ #include +#include #include #include -#include #include +#include #include #include -#include /* - * Size, in chars, of the on-stack buffer used for parsing lines of /proc/cpuinfo. - * This is also the limit on the length of a single line. + * Size, in chars, of the on-stack buffer used for parsing lines of + * /proc/cpuinfo. This is also the limit on the length of a single line. */ #define BUFFER_SIZE 2048 - -static uint32_t parse_processor_number( - const char* processor_start, - const char* processor_end) -{ - const size_t processor_length = (size_t) (processor_end - processor_start); +static uint32_t parse_processor_number(const char* processor_start, const char* processor_end) { + const size_t processor_length = (size_t)(processor_end - processor_start); if (processor_length == 0) { cpuinfo_log_warning("Processor number in /proc/cpuinfo is ignored: string is empty"); @@ -28,10 +24,12 @@ static uint32_t parse_processor_number( uint32_t processor_number = 0; for (const char* digit_ptr = processor_start; digit_ptr != processor_end; digit_ptr++) { - const uint32_t digit = (uint32_t) (*digit_ptr - '0'); + const uint32_t digit = (uint32_t)(*digit_ptr - '0'); if (digit > 10) { - cpuinfo_log_warning("non-decimal suffix %.*s in /proc/cpuinfo processor number is ignored", - (int) (processor_end - digit_ptr), digit_ptr); + cpuinfo_log_warning( + "non-decimal suffix %.*s in /proc/cpuinfo processor number is ignored", + (int)(processor_end - digit_ptr), + digit_ptr); break; } @@ -50,15 +48,17 @@ static uint32_t parse_processor_number( static void parse_apic_id( const char* apic_start, const char* apic_end, - struct cpuinfo_x86_linux_processor processor[restrict static 1]) -{ + struct cpuinfo_x86_linux_processor processor[restrict static 1]) { uint32_t apic_id = 0; for (const char* digit_ptr = apic_start; digit_ptr != apic_end; digit_ptr++) { const uint32_t digit = *digit_ptr - '0'; if (digit >= 10) { - cpuinfo_log_warning("APIC ID %.*s in /proc/cpuinfo is ignored due to unexpected non-digit character '%c' at offset %zu", - (int) (apic_end - apic_start), apic_start, - *digit_ptr, (size_t) (digit_ptr - apic_start)); + cpuinfo_log_warning( + "APIC ID %.*s in /proc/cpuinfo is ignored due to unexpected non-digit character '%c' at offset %zu", + (int)(apic_end - apic_start), + apic_start, + *digit_ptr, + (size_t)(digit_ptr - apic_start)); return; } @@ -84,8 +84,7 @@ static bool parse_line( const char* line_start, const char* line_end, struct proc_cpuinfo_parser_state state[restrict static 1], - uint64_t line_number) -{ + uint64_t line_number) { /* Empty line. Skip. */ if (line_start == line_end) { return true; @@ -100,8 +99,10 @@ static bool parse_line( } /* Skip line if no ':' separator was found. */ if (separator == line_end) { - cpuinfo_log_info("Line %.*s in /proc/cpuinfo is ignored: key/value separator ':' not found", - (int) (line_end - line_start), line_start); + cpuinfo_log_debug( + "Line %.*s in /proc/cpuinfo is ignored: key/value separator ':' not found", + (int)(line_end - line_start), + line_start); return true; } @@ -114,8 +115,10 @@ static bool parse_line( } /* Skip line if key contains nothing but spaces. */ if (key_end == line_start) { - cpuinfo_log_info("Line %.*s in /proc/cpuinfo is ignored: key contains only spaces", - (int) (line_end - line_start), line_start); + cpuinfo_log_debug( + "Line %.*s in /proc/cpuinfo is ignored: key contains only spaces", + (int)(line_end - line_start), + line_start); return true; } @@ -128,8 +131,10 @@ static bool parse_line( } /* Value part contains nothing but spaces. Skip line. */ if (value_start == line_end) { - cpuinfo_log_info("Line %.*s in /proc/cpuinfo is ignored: value contains only spaces", - (int) (line_end - line_start), line_start); + cpuinfo_log_debug( + "Line %.*s in /proc/cpuinfo is ignored: value contains only spaces", + (int)(line_end - line_start), + line_start); return true; } @@ -141,10 +146,10 @@ static bool parse_line( } } - const uint32_t processor_index = state->processor_index; + const uint32_t processor_index = state->processor_index; const uint32_t max_processors_count = state->max_processors_count; struct cpuinfo_x86_linux_processor* processors = state->processors; - struct cpuinfo_x86_linux_processor* processor = &state->dummy_processor; + struct cpuinfo_x86_linux_processor* processor = &state->dummy_processor; if (processor_index < max_processors_count) { processor = &processors[processor_index]; } @@ -162,20 +167,29 @@ static bool parse_line( if (memcmp(line_start, "processor", key_length) == 0) { const uint32_t new_processor_index = parse_processor_number(value_start, value_end); if (new_processor_index < processor_index) { - /* Strange: decreasing processor number */ + /* Strange: decreasing processor number + */ cpuinfo_log_warning( - "unexpectedly low processor number %"PRIu32" following processor %"PRIu32" in /proc/cpuinfo", - new_processor_index, processor_index); + "unexpectedly low processor number %" PRIu32 + " following processor %" PRIu32 " in /proc/cpuinfo", + new_processor_index, + processor_index); } else if (new_processor_index > processor_index + 1) { - /* Strange, but common: skipped processor $(processor_index + 1) */ - cpuinfo_log_info( - "unexpectedly high processor number %"PRIu32" following processor %"PRIu32" in /proc/cpuinfo", - new_processor_index, processor_index); + /* Strange, but common: skipped + * processor $(processor_index + 1) */ + cpuinfo_log_warning( + "unexpectedly high processor number %" PRIu32 + " following processor %" PRIu32 " in /proc/cpuinfo", + new_processor_index, + processor_index); } if (new_processor_index >= max_processors_count) { /* Log and ignore processor */ - cpuinfo_log_warning("processor %"PRIu32" in /proc/cpuinfo is ignored: index exceeds system limit %"PRIu32, - new_processor_index, max_processors_count - 1); + cpuinfo_log_warning( + "processor %" PRIu32 + " in /proc/cpuinfo is ignored: index exceeds system limit %" PRIu32, + new_processor_index, + max_processors_count - 1); } else { processors[new_processor_index].flags |= CPUINFO_LINUX_FLAG_PROC_CPUINFO; } @@ -187,21 +201,19 @@ static bool parse_line( break; default: unknown: - cpuinfo_log_debug("unknown /proc/cpuinfo key: %.*s", (int) key_length, line_start); - + cpuinfo_log_debug("unknown /proc/cpuinfo key: %.*s", (int)key_length, line_start); } return true; } bool cpuinfo_x86_linux_parse_proc_cpuinfo( uint32_t max_processors_count, - struct cpuinfo_x86_linux_processor processors[restrict static max_processors_count]) -{ + struct cpuinfo_x86_linux_processor processors[restrict static max_processors_count]) { struct proc_cpuinfo_parser_state state = { .processor_index = 0, .max_processors_count = max_processors_count, .processors = processors, }; - return cpuinfo_linux_parse_multiline_file("/proc/cpuinfo", BUFFER_SIZE, - (cpuinfo_line_callback) parse_line, &state); + return cpuinfo_linux_parse_multiline_file( + "/proc/cpuinfo", BUFFER_SIZE, (cpuinfo_line_callback)parse_line, &state); } diff --git a/3rdparty/cpuinfo/src/x86/linux/init.c b/3rdparty/cpuinfo/src/x86/linux/init.c index f5657890e6..d2b2d47514 100644 --- a/3rdparty/cpuinfo/src/x86/linux/init.c +++ b/3rdparty/cpuinfo/src/x86/linux/init.c @@ -1,15 +1,14 @@ -#include #include +#include #include #include #include -#include -#include -#include #include #include - +#include +#include +#include static inline uint32_t bit_mask(uint32_t bits) { return (UINT32_C(1) << bits) - UINT32_C(1); @@ -28,14 +27,14 @@ static inline int cmp(uint32_t a, uint32_t b) { } static int cmp_x86_linux_processor(const void* ptr_a, const void* ptr_b) { - const struct cpuinfo_x86_linux_processor* processor_a = (const struct cpuinfo_x86_linux_processor*) ptr_a; - const struct cpuinfo_x86_linux_processor* processor_b = (const struct cpuinfo_x86_linux_processor*) ptr_b; + const struct cpuinfo_x86_linux_processor* processor_a = (const struct cpuinfo_x86_linux_processor*)ptr_a; + const struct cpuinfo_x86_linux_processor* processor_b = (const struct cpuinfo_x86_linux_processor*)ptr_b; /* Move usable processors towards the start of the array */ const bool usable_a = bitmask_all(processor_a->flags, CPUINFO_LINUX_FLAG_VALID); const bool usable_b = bitmask_all(processor_b->flags, CPUINFO_LINUX_FLAG_VALID); if (usable_a != usable_b) { - return (int) usable_b - (int) usable_a; + return (int)usable_b - (int)usable_a; } /* Compare based on APIC ID (i.e. processor 0 < processor 1) */ @@ -57,12 +56,11 @@ static void cpuinfo_x86_count_objects( uint32_t l1d_count_ptr[restrict static 1], uint32_t l2_count_ptr[restrict static 1], uint32_t l3_count_ptr[restrict static 1], - uint32_t l4_count_ptr[restrict static 1]) -{ + uint32_t l4_count_ptr[restrict static 1]) { const uint32_t core_apic_mask = ~(bit_mask(processor->topology.thread_bits_length) << processor->topology.thread_bits_offset); - const uint32_t package_apic_mask = - core_apic_mask & ~(bit_mask(processor->topology.core_bits_length) << processor->topology.core_bits_offset); + const uint32_t package_apic_mask = core_apic_mask & + ~(bit_mask(processor->topology.core_bits_length) << processor->topology.core_bits_offset); const uint32_t llc_apic_mask = ~bit_mask(llc_apic_bits); const uint32_t cluster_apic_mask = package_apic_mask | llc_apic_mask; @@ -74,7 +72,10 @@ static void cpuinfo_x86_count_objects( for (uint32_t i = 0; i < linux_processors_count; i++) { if (bitmask_all(linux_processors[i].flags, valid_processor_mask)) { const uint32_t apic_id = linux_processors[i].apic_id; - cpuinfo_log_debug("APID ID %"PRIu32": system processor %"PRIu32, apic_id, linux_processors[i].linux_id); + cpuinfo_log_debug( + "APID ID %" PRIu32 ": system processor %" PRIu32, + apic_id, + linux_processors[i].linux_id); /* All bits of APIC ID except thread ID mask */ const uint32_t core_id = apic_id & core_apic_mask; @@ -82,13 +83,15 @@ static void cpuinfo_x86_count_objects( last_core_id = core_id; cores_count++; } - /* All bits of APIC ID except thread ID and core ID masks */ + /* All bits of APIC ID except thread ID and core ID + * masks */ const uint32_t package_id = apic_id & package_apic_mask; if (package_id != last_package_id) { last_package_id = package_id; packages_count++; } - /* Bits of APIC ID which are part of either LLC or package ID mask */ + /* Bits of APIC ID which are part of either LLC or + * package ID mask */ const uint32_t cluster_id = apic_id & cluster_apic_mask; if (cluster_id != last_cluster_id) { last_cluster_id = cluster_id; @@ -136,9 +139,9 @@ static void cpuinfo_x86_count_objects( *packages_count_ptr = packages_count; *l1i_count_ptr = l1i_count; *l1d_count_ptr = l1d_count; - *l2_count_ptr = l2_count; - *l3_count_ptr = l3_count; - *l4_count_ptr = l4_count; + *l2_count_ptr = l2_count; + *l3_count_ptr = l3_count; + *l4_count_ptr = l4_count; } void cpuinfo_x86_linux_init(void) { @@ -156,14 +159,13 @@ void cpuinfo_x86_linux_init(void) { struct cpuinfo_cache* l4 = NULL; const uint32_t max_processors_count = cpuinfo_linux_get_max_processors_count(); - cpuinfo_log_debug("system maximum processors count: %"PRIu32, max_processors_count); + cpuinfo_log_debug("system maximum processors count: %" PRIu32, max_processors_count); - const uint32_t max_possible_processors_count = 1 + - cpuinfo_linux_get_max_possible_processor(max_processors_count); - cpuinfo_log_debug("maximum possible processors count: %"PRIu32, max_possible_processors_count); - const uint32_t max_present_processors_count = 1 + - cpuinfo_linux_get_max_present_processor(max_processors_count); - cpuinfo_log_debug("maximum present processors count: %"PRIu32, max_present_processors_count); + const uint32_t max_possible_processors_count = + 1 + cpuinfo_linux_get_max_possible_processor(max_processors_count); + cpuinfo_log_debug("maximum possible processors count: %" PRIu32, max_possible_processors_count); + const uint32_t max_present_processors_count = 1 + cpuinfo_linux_get_max_present_processor(max_processors_count); + cpuinfo_log_debug("maximum present processors count: %" PRIu32, max_present_processors_count); uint32_t valid_processor_mask = 0; uint32_t x86_linux_processors_count = max_processors_count; @@ -181,7 +183,7 @@ void cpuinfo_x86_linux_init(void) { x86_linux_processors = calloc(x86_linux_processors_count, sizeof(struct cpuinfo_x86_linux_processor)); if (x86_linux_processors == NULL) { cpuinfo_log_error( - "failed to allocate %zu bytes for descriptions of %"PRIu32" x86 logical processors", + "failed to allocate %zu bytes for descriptions of %" PRIu32 " x86 logical processors", x86_linux_processors_count * sizeof(struct cpuinfo_x86_linux_processor), x86_linux_processors_count); return; @@ -189,14 +191,16 @@ void cpuinfo_x86_linux_init(void) { if (max_possible_processors_count != 0) { cpuinfo_linux_detect_possible_processors( - x86_linux_processors_count, &x86_linux_processors->flags, + x86_linux_processors_count, + &x86_linux_processors->flags, sizeof(struct cpuinfo_x86_linux_processor), CPUINFO_LINUX_FLAG_POSSIBLE); } if (max_present_processors_count != 0) { cpuinfo_linux_detect_present_processors( - x86_linux_processors_count, &x86_linux_processors->flags, + x86_linux_processors_count, + &x86_linux_processors->flags, sizeof(struct cpuinfo_x86_linux_processor), CPUINFO_LINUX_FLAG_PRESENT); } @@ -226,13 +230,17 @@ void cpuinfo_x86_linux_init(void) { } } - qsort(x86_linux_processors, x86_linux_processors_count, sizeof(struct cpuinfo_x86_linux_processor), - cmp_x86_linux_processor); + qsort(x86_linux_processors, + x86_linux_processors_count, + sizeof(struct cpuinfo_x86_linux_processor), + cmp_x86_linux_processor); processors = calloc(processors_count, sizeof(struct cpuinfo_processor)); if (processors == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" logical processors", - processors_count * sizeof(struct cpuinfo_processor), processors_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " logical processors", + processors_count * sizeof(struct cpuinfo_processor), + processors_count); goto cleanup; } @@ -249,21 +257,33 @@ void cpuinfo_x86_linux_init(void) { uint32_t packages_count = 0, clusters_count = 0, cores_count = 0; uint32_t l1i_count = 0, l1d_count = 0, l2_count = 0, l3_count = 0, l4_count = 0; cpuinfo_x86_count_objects( - x86_linux_processors_count, x86_linux_processors, &x86_processor, valid_processor_mask, llc_apic_bits, - &cores_count, &clusters_count, &packages_count, &l1i_count, &l1d_count, &l2_count, &l3_count, &l4_count); + x86_linux_processors_count, + x86_linux_processors, + &x86_processor, + valid_processor_mask, + llc_apic_bits, + &cores_count, + &clusters_count, + &packages_count, + &l1i_count, + &l1d_count, + &l2_count, + &l3_count, + &l4_count); - cpuinfo_log_debug("detected %"PRIu32" cores", cores_count); - cpuinfo_log_debug("detected %"PRIu32" clusters", clusters_count); - cpuinfo_log_debug("detected %"PRIu32" packages", packages_count); - cpuinfo_log_debug("detected %"PRIu32" L1I caches", l1i_count); - cpuinfo_log_debug("detected %"PRIu32" L1D caches", l1d_count); - cpuinfo_log_debug("detected %"PRIu32" L2 caches", l2_count); - cpuinfo_log_debug("detected %"PRIu32" L3 caches", l3_count); - cpuinfo_log_debug("detected %"PRIu32" L4 caches", l4_count); + cpuinfo_log_debug("detected %" PRIu32 " cores", cores_count); + cpuinfo_log_debug("detected %" PRIu32 " clusters", clusters_count); + cpuinfo_log_debug("detected %" PRIu32 " packages", packages_count); + cpuinfo_log_debug("detected %" PRIu32 " L1I caches", l1i_count); + cpuinfo_log_debug("detected %" PRIu32 " L1D caches", l1d_count); + cpuinfo_log_debug("detected %" PRIu32 " L2 caches", l2_count); + cpuinfo_log_debug("detected %" PRIu32 " L3 caches", l3_count); + cpuinfo_log_debug("detected %" PRIu32 " L4 caches", l4_count); linux_cpu_to_processor_map = calloc(x86_linux_processors_count, sizeof(struct cpuinfo_processor*)); if (linux_cpu_to_processor_map == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for mapping entries of %"PRIu32" logical processors", + cpuinfo_log_error( + "failed to allocate %zu bytes for mapping entries of %" PRIu32 " logical processors", x86_linux_processors_count * sizeof(struct cpuinfo_processor*), x86_linux_processors_count); goto cleanup; @@ -271,7 +291,8 @@ void cpuinfo_x86_linux_init(void) { linux_cpu_to_core_map = calloc(x86_linux_processors_count, sizeof(struct cpuinfo_core*)); if (linux_cpu_to_core_map == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for mapping entries of %"PRIu32" cores", + cpuinfo_log_error( + "failed to allocate %zu bytes for mapping entries of %" PRIu32 " cores", x86_linux_processors_count * sizeof(struct cpuinfo_core*), x86_linux_processors_count); goto cleanup; @@ -279,75 +300,93 @@ void cpuinfo_x86_linux_init(void) { cores = calloc(cores_count, sizeof(struct cpuinfo_core)); if (cores == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" cores", - cores_count * sizeof(struct cpuinfo_core), cores_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " cores", + cores_count * sizeof(struct cpuinfo_core), + cores_count); goto cleanup; } clusters = calloc(clusters_count, sizeof(struct cpuinfo_cluster)); if (clusters == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" core clusters", - clusters_count * sizeof(struct cpuinfo_cluster), clusters_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " core clusters", + clusters_count * sizeof(struct cpuinfo_cluster), + clusters_count); goto cleanup; } packages = calloc(packages_count, sizeof(struct cpuinfo_package)); if (packages == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" physical packages", - packages_count * sizeof(struct cpuinfo_package), packages_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " physical packages", + packages_count * sizeof(struct cpuinfo_package), + packages_count); goto cleanup; } if (l1i_count != 0) { l1i = calloc(l1i_count, sizeof(struct cpuinfo_cache)); if (l1i == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1I caches", - l1i_count * sizeof(struct cpuinfo_cache), l1i_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1I caches", + l1i_count * sizeof(struct cpuinfo_cache), + l1i_count); goto cleanup; } } if (l1d_count != 0) { l1d = calloc(l1d_count, sizeof(struct cpuinfo_cache)); if (l1d == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1D caches", - l1d_count * sizeof(struct cpuinfo_cache), l1d_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1D caches", + l1d_count * sizeof(struct cpuinfo_cache), + l1d_count); goto cleanup; } } if (l2_count != 0) { l2 = calloc(l2_count, sizeof(struct cpuinfo_cache)); if (l2 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L2 caches", - l2_count * sizeof(struct cpuinfo_cache), l2_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L2 caches", + l2_count * sizeof(struct cpuinfo_cache), + l2_count); goto cleanup; } } if (l3_count != 0) { l3 = calloc(l3_count, sizeof(struct cpuinfo_cache)); if (l3 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L3 caches", - l3_count * sizeof(struct cpuinfo_cache), l3_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L3 caches", + l3_count * sizeof(struct cpuinfo_cache), + l3_count); goto cleanup; } } if (l4_count != 0) { l4 = calloc(l4_count, sizeof(struct cpuinfo_cache)); if (l4 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L4 caches", - l4_count * sizeof(struct cpuinfo_cache), l4_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L4 caches", + l4_count * sizeof(struct cpuinfo_cache), + l4_count); goto cleanup; } } const uint32_t core_apic_mask = ~(bit_mask(x86_processor.topology.thread_bits_length) << x86_processor.topology.thread_bits_offset); - const uint32_t package_apic_mask = - core_apic_mask & ~(bit_mask(x86_processor.topology.core_bits_length) << x86_processor.topology.core_bits_offset); + const uint32_t package_apic_mask = core_apic_mask & + ~(bit_mask(x86_processor.topology.core_bits_length) << x86_processor.topology.core_bits_offset); const uint32_t llc_apic_mask = ~bit_mask(llc_apic_bits); const uint32_t cluster_apic_mask = package_apic_mask | llc_apic_mask; - uint32_t processor_index = UINT32_MAX, core_index = UINT32_MAX, cluster_index = UINT32_MAX, package_index = UINT32_MAX; - uint32_t l1i_index = UINT32_MAX, l1d_index = UINT32_MAX, l2_index = UINT32_MAX, l3_index = UINT32_MAX, l4_index = UINT32_MAX; + uint32_t processor_index = UINT32_MAX, core_index = UINT32_MAX, cluster_index = UINT32_MAX, + package_index = UINT32_MAX; + uint32_t l1i_index = UINT32_MAX, l1d_index = UINT32_MAX, l2_index = UINT32_MAX, l3_index = UINT32_MAX, + l4_index = UINT32_MAX; uint32_t cluster_id = 0, core_id = 0, smt_id = 0; uint32_t last_apic_core_id = UINT32_MAX, last_apic_cluster_id = UINT32_MAX, last_apic_package_id = UINT32_MAX; uint32_t last_l1i_id = UINT32_MAX, last_l1d_id = UINT32_MAX; @@ -365,13 +404,15 @@ void cpuinfo_x86_linux_init(void) { core_id++; smt_id = 0; } - /* Bits of APIC ID which are part of either LLC or package ID mask */ + /* Bits of APIC ID which are part of either LLC or + * package ID mask */ const uint32_t apic_cluster_id = apic_id & cluster_apic_mask; if (apic_cluster_id != last_apic_cluster_id) { cluster_index++; cluster_id++; } - /* All bits of APIC ID except thread ID and core ID masks */ + /* All bits of APIC ID except thread ID and core ID + * masks */ const uint32_t apic_package_id = apic_id & package_apic_mask; if (apic_package_id != last_apic_package_id) { package_index++; @@ -380,16 +421,16 @@ void cpuinfo_x86_linux_init(void) { } /* Initialize logical processor object */ - processors[processor_index].smt_id = smt_id; - processors[processor_index].core = cores + core_index; - processors[processor_index].cluster = clusters + cluster_index; - processors[processor_index].package = packages + package_index; + processors[processor_index].smt_id = smt_id; + processors[processor_index].core = cores + core_index; + processors[processor_index].cluster = clusters + cluster_index; + processors[processor_index].package = packages + package_index; processors[processor_index].linux_id = x86_linux_processors[i].linux_id; - processors[processor_index].apic_id = x86_linux_processors[i].apic_id; + processors[processor_index].apic_id = x86_linux_processors[i].apic_id; if (apid_core_id != last_apic_core_id) { /* new core */ - cores[core_index] = (struct cpuinfo_core) { + cores[core_index] = (struct cpuinfo_core){ .processor_start = processor_index, .processor_count = 1, .core_id = core_id, @@ -420,7 +461,8 @@ void cpuinfo_x86_linux_init(void) { packages[package_index].cluster_count += 1; last_apic_cluster_id = apic_cluster_id; } else { - /* another logical processor on the same cluster */ + /* another logical processor on the same cluster + */ clusters[cluster_index].processor_count++; } @@ -430,10 +472,12 @@ void cpuinfo_x86_linux_init(void) { packages[package_index].processor_count = 1; packages[package_index].core_start = core_index; packages[package_index].cluster_start = cluster_index; - cpuinfo_x86_format_package_name(x86_processor.vendor, brand_string, packages[package_index].name); + cpuinfo_x86_format_package_name( + x86_processor.vendor, brand_string, packages[package_index].name); last_apic_package_id = apic_package_id; } else { - /* another logical processor on the same package */ + /* another logical processor on the same package + */ packages[package_index].processor_count++; } @@ -446,18 +490,19 @@ void cpuinfo_x86_linux_init(void) { if (l1i_id != last_l1i_id) { /* new cache */ last_l1i_id = l1i_id; - l1i[++l1i_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l1i.size, - .associativity = x86_processor.cache.l1i.associativity, - .sets = x86_processor.cache.l1i.sets, - .partitions = x86_processor.cache.l1i.partitions, - .line_size = x86_processor.cache.l1i.line_size, - .flags = x86_processor.cache.l1i.flags, + l1i[++l1i_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l1i.size, + .associativity = x86_processor.cache.l1i.associativity, + .sets = x86_processor.cache.l1i.sets, + .partitions = x86_processor.cache.l1i.partitions, + .line_size = x86_processor.cache.l1i.line_size, + .flags = x86_processor.cache.l1i.flags, .processor_start = processor_index, .processor_count = 1, }; } else { - /* another processor sharing the same cache */ + /* another processor sharing the same + * cache */ l1i[l1i_index].processor_count += 1; } processors[i].cache.l1i = &l1i[l1i_index]; @@ -471,18 +516,19 @@ void cpuinfo_x86_linux_init(void) { if (l1d_id != last_l1d_id) { /* new cache */ last_l1d_id = l1d_id; - l1d[++l1d_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l1d.size, - .associativity = x86_processor.cache.l1d.associativity, - .sets = x86_processor.cache.l1d.sets, - .partitions = x86_processor.cache.l1d.partitions, - .line_size = x86_processor.cache.l1d.line_size, - .flags = x86_processor.cache.l1d.flags, + l1d[++l1d_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l1d.size, + .associativity = x86_processor.cache.l1d.associativity, + .sets = x86_processor.cache.l1d.sets, + .partitions = x86_processor.cache.l1d.partitions, + .line_size = x86_processor.cache.l1d.line_size, + .flags = x86_processor.cache.l1d.flags, .processor_start = processor_index, .processor_count = 1, }; } else { - /* another processor sharing the same cache */ + /* another processor sharing the same + * cache */ l1d[l1d_index].processor_count += 1; } processors[i].cache.l1d = &l1d[l1d_index]; @@ -496,18 +542,19 @@ void cpuinfo_x86_linux_init(void) { if (l2_id != last_l2_id) { /* new cache */ last_l2_id = l2_id; - l2[++l2_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l2.size, - .associativity = x86_processor.cache.l2.associativity, - .sets = x86_processor.cache.l2.sets, - .partitions = x86_processor.cache.l2.partitions, - .line_size = x86_processor.cache.l2.line_size, - .flags = x86_processor.cache.l2.flags, + l2[++l2_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l2.size, + .associativity = x86_processor.cache.l2.associativity, + .sets = x86_processor.cache.l2.sets, + .partitions = x86_processor.cache.l2.partitions, + .line_size = x86_processor.cache.l2.line_size, + .flags = x86_processor.cache.l2.flags, .processor_start = processor_index, .processor_count = 1, }; } else { - /* another processor sharing the same cache */ + /* another processor sharing the same + * cache */ l2[l2_index].processor_count += 1; } processors[i].cache.l2 = &l2[l2_index]; @@ -521,18 +568,19 @@ void cpuinfo_x86_linux_init(void) { if (l3_id != last_l3_id) { /* new cache */ last_l3_id = l3_id; - l3[++l3_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l3.size, - .associativity = x86_processor.cache.l3.associativity, - .sets = x86_processor.cache.l3.sets, - .partitions = x86_processor.cache.l3.partitions, - .line_size = x86_processor.cache.l3.line_size, - .flags = x86_processor.cache.l3.flags, + l3[++l3_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l3.size, + .associativity = x86_processor.cache.l3.associativity, + .sets = x86_processor.cache.l3.sets, + .partitions = x86_processor.cache.l3.partitions, + .line_size = x86_processor.cache.l3.line_size, + .flags = x86_processor.cache.l3.flags, .processor_start = processor_index, .processor_count = 1, }; } else { - /* another processor sharing the same cache */ + /* another processor sharing the same + * cache */ l3[l3_index].processor_count += 1; } processors[i].cache.l3 = &l3[l3_index]; @@ -546,18 +594,19 @@ void cpuinfo_x86_linux_init(void) { if (l4_id != last_l4_id) { /* new cache */ last_l4_id = l4_id; - l4[++l4_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l4.size, - .associativity = x86_processor.cache.l4.associativity, - .sets = x86_processor.cache.l4.sets, - .partitions = x86_processor.cache.l4.partitions, - .line_size = x86_processor.cache.l4.line_size, - .flags = x86_processor.cache.l4.flags, + l4[++l4_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l4.size, + .associativity = x86_processor.cache.l4.associativity, + .sets = x86_processor.cache.l4.sets, + .partitions = x86_processor.cache.l4.partitions, + .line_size = x86_processor.cache.l4.line_size, + .flags = x86_processor.cache.l4.flags, .processor_start = processor_index, .processor_count = 1, }; } else { - /* another processor sharing the same cache */ + /* another processor sharing the same + * cache */ l4[l4_index].processor_count += 1; } processors[i].cache.l4 = &l4[l4_index]; @@ -575,9 +624,9 @@ void cpuinfo_x86_linux_init(void) { cpuinfo_packages = packages; cpuinfo_cache[cpuinfo_cache_level_1i] = l1i; cpuinfo_cache[cpuinfo_cache_level_1d] = l1d; - cpuinfo_cache[cpuinfo_cache_level_2] = l2; - cpuinfo_cache[cpuinfo_cache_level_3] = l3; - cpuinfo_cache[cpuinfo_cache_level_4] = l4; + cpuinfo_cache[cpuinfo_cache_level_2] = l2; + cpuinfo_cache[cpuinfo_cache_level_3] = l3; + cpuinfo_cache[cpuinfo_cache_level_4] = l4; cpuinfo_processors_count = processors_count; cpuinfo_cores_count = cores_count; @@ -585,12 +634,12 @@ void cpuinfo_x86_linux_init(void) { cpuinfo_packages_count = packages_count; cpuinfo_cache_count[cpuinfo_cache_level_1i] = l1i_count; cpuinfo_cache_count[cpuinfo_cache_level_1d] = l1d_count; - cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; - cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; - cpuinfo_cache_count[cpuinfo_cache_level_4] = l4_count; + cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; + cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; + cpuinfo_cache_count[cpuinfo_cache_level_4] = l4_count; cpuinfo_max_cache_size = cpuinfo_compute_max_cache_size(&processors[0]); - cpuinfo_global_uarch = (struct cpuinfo_uarch_info) { + cpuinfo_global_uarch = (struct cpuinfo_uarch_info){ .uarch = x86_processor.uarch, .cpuid = x86_processor.cpuid, .processor_count = processors_count, diff --git a/3rdparty/cpuinfo/src/x86/mach/init.c b/3rdparty/cpuinfo/src/x86/mach/init.c index b44d3adf5a..b8ea6047ac 100644 --- a/3rdparty/cpuinfo/src/x86/mach/init.c +++ b/3rdparty/cpuinfo/src/x86/mach/init.c @@ -3,11 +3,10 @@ #include #include -#include -#include #include #include - +#include +#include static inline uint32_t max(uint32_t a, uint32_t b) { return a > b ? a : b; @@ -31,27 +30,35 @@ void cpuinfo_x86_mach_init(void) { struct cpuinfo_mach_topology mach_topology = cpuinfo_mach_detect_topology(); processors = calloc(mach_topology.threads, sizeof(struct cpuinfo_processor)); if (processors == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" logical processors", - mach_topology.threads * sizeof(struct cpuinfo_processor), mach_topology.threads); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " logical processors", + mach_topology.threads * sizeof(struct cpuinfo_processor), + mach_topology.threads); goto cleanup; } cores = calloc(mach_topology.cores, sizeof(struct cpuinfo_core)); if (cores == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" cores", - mach_topology.cores * sizeof(struct cpuinfo_core), mach_topology.cores); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " cores", + mach_topology.cores * sizeof(struct cpuinfo_core), + mach_topology.cores); goto cleanup; } /* On x86 cluster of cores is a physical package */ clusters = calloc(mach_topology.packages, sizeof(struct cpuinfo_cluster)); if (clusters == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" core clusters", - mach_topology.packages * sizeof(struct cpuinfo_cluster), mach_topology.packages); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " core clusters", + mach_topology.packages * sizeof(struct cpuinfo_cluster), + mach_topology.packages); goto cleanup; } packages = calloc(mach_topology.packages, sizeof(struct cpuinfo_package)); if (packages == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" physical packages", - mach_topology.packages * sizeof(struct cpuinfo_package), mach_topology.packages); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " physical packages", + mach_topology.packages * sizeof(struct cpuinfo_package), + mach_topology.packages); goto cleanup; } @@ -65,7 +72,7 @@ void cpuinfo_x86_mach_init(void) { const uint32_t threads_per_package = mach_topology.threads / mach_topology.packages; const uint32_t cores_per_package = mach_topology.cores / mach_topology.packages; for (uint32_t i = 0; i < mach_topology.packages; i++) { - clusters[i] = (struct cpuinfo_cluster) { + clusters[i] = (struct cpuinfo_cluster){ .processor_start = i * threads_per_package, .processor_count = threads_per_package, .core_start = i * cores_per_package, @@ -85,7 +92,7 @@ void cpuinfo_x86_mach_init(void) { cpuinfo_x86_format_package_name(x86_processor.vendor, brand_string, packages[i].name); } for (uint32_t i = 0; i < mach_topology.cores; i++) { - cores[i] = (struct cpuinfo_core) { + cores[i] = (struct cpuinfo_core){ .processor_start = i * threads_per_core, .processor_count = threads_per_core, .core_id = i % cores_per_package, @@ -103,15 +110,14 @@ void cpuinfo_x86_mach_init(void) { /* Reconstruct APIC IDs from topology components */ const uint32_t thread_bits_mask = bit_mask(x86_processor.topology.thread_bits_length); - const uint32_t core_bits_mask = bit_mask(x86_processor.topology.core_bits_length); - const uint32_t package_bits_offset = max( - x86_processor.topology.thread_bits_offset + x86_processor.topology.thread_bits_length, - x86_processor.topology.core_bits_offset + x86_processor.topology.core_bits_length); - const uint32_t apic_id = - ((smt_id & thread_bits_mask) << x86_processor.topology.thread_bits_offset) | + const uint32_t core_bits_mask = bit_mask(x86_processor.topology.core_bits_length); + const uint32_t package_bits_offset = + max(x86_processor.topology.thread_bits_offset + x86_processor.topology.thread_bits_length, + x86_processor.topology.core_bits_offset + x86_processor.topology.core_bits_length); + const uint32_t apic_id = ((smt_id & thread_bits_mask) << x86_processor.topology.thread_bits_offset) | ((core_id & core_bits_mask) << x86_processor.topology.core_bits_offset) | (package_id << package_bits_offset); - cpuinfo_log_debug("reconstructed APIC ID 0x%08"PRIx32" for thread %"PRIu32, apic_id, i); + cpuinfo_log_debug("reconstructed APIC ID 0x%08" PRIx32 " for thread %" PRIu32, apic_id, i); processors[i].smt_id = smt_id; processors[i].core = cores + i / threads_per_core; @@ -126,11 +132,12 @@ void cpuinfo_x86_mach_init(void) { if (threads_per_l1 == 0) { /* Assume that threads on the same core share L1 */ threads_per_l1 = mach_topology.threads / mach_topology.cores; - cpuinfo_log_warning("Mach kernel did not report number of threads sharing L1 cache; assume %"PRIu32, + cpuinfo_log_warning( + "Mach kernel did not report number of threads sharing L1 cache; assume %" PRIu32, threads_per_l1); } l1_count = mach_topology.threads / threads_per_l1; - cpuinfo_log_debug("detected %"PRIu32" L1 caches", l1_count); + cpuinfo_log_debug("detected %" PRIu32 " L1 caches", l1_count); } uint32_t threads_per_l2 = 0, l2_count = 0; @@ -138,17 +145,20 @@ void cpuinfo_x86_mach_init(void) { threads_per_l2 = mach_topology.threads_per_cache[2]; if (threads_per_l2 == 0) { if (x86_processor.cache.l3.size != 0) { - /* This is not a last-level cache; assume that threads on the same core share L2 */ + /* This is not a last-level cache; assume that + * threads on the same core share L2 */ threads_per_l2 = mach_topology.threads / mach_topology.cores; } else { - /* This is a last-level cache; assume that threads on the same package share L2 */ + /* This is a last-level cache; assume that + * threads on the same package share L2 */ threads_per_l2 = mach_topology.threads / mach_topology.packages; } - cpuinfo_log_warning("Mach kernel did not report number of threads sharing L2 cache; assume %"PRIu32, + cpuinfo_log_warning( + "Mach kernel did not report number of threads sharing L2 cache; assume %" PRIu32, threads_per_l2); } l2_count = mach_topology.threads / threads_per_l2; - cpuinfo_log_debug("detected %"PRIu32" L2 caches", l2_count); + cpuinfo_log_debug("detected %" PRIu32 " L2 caches", l2_count); } uint32_t threads_per_l3 = 0, l3_count = 0; @@ -157,14 +167,16 @@ void cpuinfo_x86_mach_init(void) { if (threads_per_l3 == 0) { /* * Assume that threads on the same package share L3. - * However, is it not necessarily the last-level cache (there may be L4 cache as well) + * However, is it not necessarily the last-level cache + * (there may be L4 cache as well) */ threads_per_l3 = mach_topology.threads / mach_topology.packages; - cpuinfo_log_warning("Mach kernel did not report number of threads sharing L3 cache; assume %"PRIu32, + cpuinfo_log_warning( + "Mach kernel did not report number of threads sharing L3 cache; assume %" PRIu32, threads_per_l3); } l3_count = mach_topology.threads / threads_per_l3; - cpuinfo_log_debug("detected %"PRIu32" L3 caches", l3_count); + cpuinfo_log_debug("detected %" PRIu32 " L3 caches", l3_count); } uint32_t threads_per_l4 = 0, l4_count = 0; @@ -173,32 +185,36 @@ void cpuinfo_x86_mach_init(void) { if (threads_per_l4 == 0) { /* * Assume that all threads share this L4. - * As of now, L4 cache exists only on notebook x86 CPUs, which are single-package, - * but multi-socket systems could have shared L4 (like on IBM POWER8). + * As of now, L4 cache exists only on notebook x86 CPUs, + * which are single-package, but multi-socket systems + * could have shared L4 (like on IBM POWER8). */ threads_per_l4 = mach_topology.threads; - cpuinfo_log_warning("Mach kernel did not report number of threads sharing L4 cache; assume %"PRIu32, + cpuinfo_log_warning( + "Mach kernel did not report number of threads sharing L4 cache; assume %" PRIu32, threads_per_l4); } l4_count = mach_topology.threads / threads_per_l4; - cpuinfo_log_debug("detected %"PRIu32" L4 caches", l4_count); + cpuinfo_log_debug("detected %" PRIu32 " L4 caches", l4_count); } if (x86_processor.cache.l1i.size != 0) { l1i = calloc(l1_count, sizeof(struct cpuinfo_cache)); if (l1i == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1I caches", - l1_count * sizeof(struct cpuinfo_cache), l1_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1I caches", + l1_count * sizeof(struct cpuinfo_cache), + l1_count); return; } for (uint32_t c = 0; c < l1_count; c++) { - l1i[c] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l1i.size, - .associativity = x86_processor.cache.l1i.associativity, - .sets = x86_processor.cache.l1i.sets, - .partitions = x86_processor.cache.l1i.partitions, - .line_size = x86_processor.cache.l1i.line_size, - .flags = x86_processor.cache.l1i.flags, + l1i[c] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l1i.size, + .associativity = x86_processor.cache.l1i.associativity, + .sets = x86_processor.cache.l1i.sets, + .partitions = x86_processor.cache.l1i.partitions, + .line_size = x86_processor.cache.l1i.line_size, + .flags = x86_processor.cache.l1i.flags, .processor_start = c * threads_per_l1, .processor_count = threads_per_l1, }; @@ -211,18 +227,20 @@ void cpuinfo_x86_mach_init(void) { if (x86_processor.cache.l1d.size != 0) { l1d = calloc(l1_count, sizeof(struct cpuinfo_cache)); if (l1d == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1D caches", - l1_count * sizeof(struct cpuinfo_cache), l1_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1D caches", + l1_count * sizeof(struct cpuinfo_cache), + l1_count); return; } for (uint32_t c = 0; c < l1_count; c++) { - l1d[c] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l1d.size, - .associativity = x86_processor.cache.l1d.associativity, - .sets = x86_processor.cache.l1d.sets, - .partitions = x86_processor.cache.l1d.partitions, - .line_size = x86_processor.cache.l1d.line_size, - .flags = x86_processor.cache.l1d.flags, + l1d[c] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l1d.size, + .associativity = x86_processor.cache.l1d.associativity, + .sets = x86_processor.cache.l1d.sets, + .partitions = x86_processor.cache.l1d.partitions, + .line_size = x86_processor.cache.l1d.line_size, + .flags = x86_processor.cache.l1d.flags, .processor_start = c * threads_per_l1, .processor_count = threads_per_l1, }; @@ -235,18 +253,20 @@ void cpuinfo_x86_mach_init(void) { if (l2_count != 0) { l2 = calloc(l2_count, sizeof(struct cpuinfo_cache)); if (l2 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L2 caches", - l2_count * sizeof(struct cpuinfo_cache), l2_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L2 caches", + l2_count * sizeof(struct cpuinfo_cache), + l2_count); return; } for (uint32_t c = 0; c < l2_count; c++) { - l2[c] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l2.size, - .associativity = x86_processor.cache.l2.associativity, - .sets = x86_processor.cache.l2.sets, - .partitions = x86_processor.cache.l2.partitions, - .line_size = x86_processor.cache.l2.line_size, - .flags = x86_processor.cache.l2.flags, + l2[c] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l2.size, + .associativity = x86_processor.cache.l2.associativity, + .sets = x86_processor.cache.l2.sets, + .partitions = x86_processor.cache.l2.partitions, + .line_size = x86_processor.cache.l2.line_size, + .flags = x86_processor.cache.l2.flags, .processor_start = c * threads_per_l2, .processor_count = threads_per_l2, }; @@ -259,18 +279,20 @@ void cpuinfo_x86_mach_init(void) { if (l3_count != 0) { l3 = calloc(l3_count, sizeof(struct cpuinfo_cache)); if (l3 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L3 caches", - l3_count * sizeof(struct cpuinfo_cache), l3_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L3 caches", + l3_count * sizeof(struct cpuinfo_cache), + l3_count); return; } for (uint32_t c = 0; c < l3_count; c++) { - l3[c] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l3.size, - .associativity = x86_processor.cache.l3.associativity, - .sets = x86_processor.cache.l3.sets, - .partitions = x86_processor.cache.l3.partitions, - .line_size = x86_processor.cache.l3.line_size, - .flags = x86_processor.cache.l3.flags, + l3[c] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l3.size, + .associativity = x86_processor.cache.l3.associativity, + .sets = x86_processor.cache.l3.sets, + .partitions = x86_processor.cache.l3.partitions, + .line_size = x86_processor.cache.l3.line_size, + .flags = x86_processor.cache.l3.flags, .processor_start = c * threads_per_l3, .processor_count = threads_per_l3, }; @@ -283,18 +305,20 @@ void cpuinfo_x86_mach_init(void) { if (l4_count != 0) { l4 = calloc(l4_count, sizeof(struct cpuinfo_cache)); if (l4 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L4 caches", - l4_count * sizeof(struct cpuinfo_cache), l4_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L4 caches", + l4_count * sizeof(struct cpuinfo_cache), + l4_count); return; } for (uint32_t c = 0; c < l4_count; c++) { - l4[c] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l4.size, - .associativity = x86_processor.cache.l4.associativity, - .sets = x86_processor.cache.l4.sets, - .partitions = x86_processor.cache.l4.partitions, - .line_size = x86_processor.cache.l4.line_size, - .flags = x86_processor.cache.l4.flags, + l4[c] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l4.size, + .associativity = x86_processor.cache.l4.associativity, + .sets = x86_processor.cache.l4.sets, + .partitions = x86_processor.cache.l4.partitions, + .line_size = x86_processor.cache.l4.line_size, + .flags = x86_processor.cache.l4.flags, .processor_start = c * threads_per_l4, .processor_count = threads_per_l4, }; @@ -311,9 +335,9 @@ void cpuinfo_x86_mach_init(void) { cpuinfo_packages = packages; cpuinfo_cache[cpuinfo_cache_level_1i] = l1i; cpuinfo_cache[cpuinfo_cache_level_1d] = l1d; - cpuinfo_cache[cpuinfo_cache_level_2] = l2; - cpuinfo_cache[cpuinfo_cache_level_3] = l3; - cpuinfo_cache[cpuinfo_cache_level_4] = l4; + cpuinfo_cache[cpuinfo_cache_level_2] = l2; + cpuinfo_cache[cpuinfo_cache_level_3] = l3; + cpuinfo_cache[cpuinfo_cache_level_4] = l4; cpuinfo_processors_count = mach_topology.threads; cpuinfo_cores_count = mach_topology.cores; @@ -321,12 +345,12 @@ void cpuinfo_x86_mach_init(void) { cpuinfo_packages_count = mach_topology.packages; cpuinfo_cache_count[cpuinfo_cache_level_1i] = l1_count; cpuinfo_cache_count[cpuinfo_cache_level_1d] = l1_count; - cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; - cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; - cpuinfo_cache_count[cpuinfo_cache_level_4] = l4_count; + cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; + cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; + cpuinfo_cache_count[cpuinfo_cache_level_4] = l4_count; cpuinfo_max_cache_size = cpuinfo_compute_max_cache_size(&processors[0]); - cpuinfo_global_uarch = (struct cpuinfo_uarch_info) { + cpuinfo_global_uarch = (struct cpuinfo_uarch_info){ .uarch = x86_processor.uarch, .cpuid = x86_processor.cpuid, .processor_count = mach_topology.threads, diff --git a/3rdparty/cpuinfo/src/x86/mockcpuid.c b/3rdparty/cpuinfo/src/x86/mockcpuid.c index 2631f09ba8..0eacfa0b65 100644 --- a/3rdparty/cpuinfo/src/x86/mockcpuid.c +++ b/3rdparty/cpuinfo/src/x86/mockcpuid.c @@ -1,13 +1,12 @@ -#include #include +#include #if !CPUINFO_MOCK - #error This file should be built only in mock mode +#error This file should be built only in mock mode #endif #include - static struct cpuinfo_mock_cpuid* cpuinfo_mock_cpuid_data = NULL; static uint32_t cpuinfo_mock_cpuid_entries = 0; static uint32_t cpuinfo_mock_cpuid_leaf4_iteration = 0; @@ -56,8 +55,7 @@ void CPUINFO_ABI cpuinfo_mock_get_cpuidex(uint32_t eax, uint32_t ecx, uint32_t r if (cpuinfo_mock_cpuid_data != NULL && cpuinfo_mock_cpuid_entries != 0) { for (uint32_t i = 0; i < cpuinfo_mock_cpuid_entries; i++) { if (eax == cpuinfo_mock_cpuid_data[i].input_eax && - ecx == cpuinfo_mock_cpuid_data[i].input_ecx) - { + ecx == cpuinfo_mock_cpuid_data[i].input_ecx) { regs[0] = cpuinfo_mock_cpuid_data[i].eax; regs[1] = cpuinfo_mock_cpuid_data[i].ebx; regs[2] = cpuinfo_mock_cpuid_data[i].ecx; diff --git a/3rdparty/cpuinfo/src/x86/name.c b/3rdparty/cpuinfo/src/x86/name.c index 38c47a3465..76f61368d6 100644 --- a/3rdparty/cpuinfo/src/x86/name.c +++ b/3rdparty/cpuinfo/src/x86/name.c @@ -1,6 +1,6 @@ #include -#include #include +#include #include #include @@ -8,7 +8,6 @@ #include #include - /* The state of the parser to be preserved between parsing different tokens. */ struct parser_state { /* @@ -17,8 +16,9 @@ struct parser_state { */ char* context_model; /* - * Pointer to the start of the previous token if it is a single-uppercase-letter token. - * NULL if previous token is anything different. + * Pointer to the start of the previous token if it is a + * single-uppercase-letter token. NULL if previous token is anything + * different. */ char* context_upper_letter; /* @@ -27,31 +27,36 @@ struct parser_state { */ char* context_dual; /* - * Pointer to the start of the previous token if it is "Core", "Dual-Core", "QuadCore", etc. - * NULL if previous token is anything different. + * Pointer to the start of the previous token if it is "Core", + * "Dual-Core", "QuadCore", etc. NULL if previous token is anything + * different. */ char* context_core; /* - * Pointer to the start of the previous token if it is "Eng" or "Engineering", etc. - * NULL if previous token is anything different. + * Pointer to the start of the previous token if it is "Eng" or + * "Engineering", etc. NULL if previous token is anything different. */ char* context_engineering; /* - * Pointer to the '@' symbol in the brand string (separates frequency specification). - * NULL if there is no '@' symbol. + * Pointer to the '@' symbol in the brand string (separates frequency + * specification). NULL if there is no '@' symbol. */ char* frequency_separator; - /* Indicates whether the brand string (after transformations) contains frequency. */ + /* Indicates whether the brand string (after transformations) contains + * frequency. */ bool frequency_token; - /* Indicates whether the processor is of Xeon family (contains "Xeon" substring). */ + /* Indicates whether the processor is of Xeon family (contains "Xeon" + * substring). */ bool xeon; /* Indicates whether the processor model number was already parsed. */ bool parsed_model_number; - /* Indicates whether the processor is an engineering sample (contains "Engineering Sample" or "Eng Sample" substrings). */ + /* Indicates whether the processor is an engineering sample (contains + * "Engineering Sample" or "Eng Sample" substrings). */ bool engineering_sample; }; -/** @brief Resets information about the previous token. Keeps all other state information. */ +/** @brief Resets information about the previous token. Keeps all other + * state information. */ static void reset_context(struct parser_state* state) { state->context_model = NULL; state->context_upper_letter = NULL; @@ -60,12 +65,17 @@ static void reset_context(struct parser_state* state) { } /** - * @brief Overwrites the supplied string with space characters if it exactly matches the given string. - * @param string The string to be compared against other string, and erased in case of matching. - * @param length The length of the two string to be compared against each other. + * @brief Overwrites the supplied string with space characters if it + * exactly matches the given string. + * @param string The string to be compared against other string, and + * erased in case of matching. + * @param length The length of the two string to be compared against each + * other. * @param target The string to compare against. - * @retval true If the two strings match and the first supplied string was erased (overwritten with space characters). - * @retval false If the two strings are different and the first supplied string remained unchanged. + * @retval true If the two strings match and the first supplied string + * was erased (overwritten with space characters). + * @retval false If the two strings are different and the first supplied + * string remained unchanged. */ static inline bool erase_matching(char* string, size_t length, const char* target) { const bool match = memcmp(string, target, length) == 0; @@ -76,13 +86,15 @@ static inline bool erase_matching(char* string, size_t length, const char* targe } /** - * @brief Checks if the supplied ASCII character is an uppercase latin letter. + * @brief Checks if the supplied ASCII character is an uppercase latin + * letter. * @param character The character to analyse. - * @retval true If the supplied character is an uppercase latin letter ('A' to 'Z'). + * @retval true If the supplied character is an uppercase latin letter + * ('A' to 'Z'). * @retval false If the supplied character is anything different. */ static inline bool is_upper_letter(char character) { - return (uint32_t) (character - 'A') <= (uint32_t)('Z' - 'A'); + return (uint32_t)(character - 'A') <= (uint32_t)('Z' - 'A'); } /** @@ -92,7 +104,7 @@ static inline bool is_upper_letter(char character) { * @retval false If the supplied character is anything different. */ static inline bool is_digit(char character) { - return (uint32_t) (character - '0') < UINT32_C(10); + return (uint32_t)(character - '0') < UINT32_C(10); } static inline bool is_zero_number(const char* token_start, const char* token_end) { @@ -132,7 +144,7 @@ static inline bool is_model_number(const char* token_start, const char* token_en } static inline bool is_frequency(const char* token_start, const char* token_end) { - const size_t token_length = (size_t) (token_end - token_start); + const size_t token_length = (size_t)(token_end - token_start); if (token_length > 3 && token_end[-2] == 'H' && token_end[-1] == 'z') { switch (token_end[-3]) { case 'K': @@ -148,7 +160,7 @@ static inline bool is_frequency(const char* token_start, const char* token_end) * @warning Input and output tokens can overlap */ static inline char* move_token(const char* token_start, const char* token_end, char* output_ptr) { - const size_t token_length = (size_t) (token_end - token_start); + const size_t token_length = (size_t)(token_end - token_start); memmove(output_ptr, token_start, token_length); return output_ptr + token_length; } @@ -157,7 +169,7 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st const struct parser_state previousState = *state; reset_context(state); - size_t token_length = (size_t) (token_end - token_start); + size_t token_length = (size_t)(token_end - token_start); if (state->frequency_separator != NULL) { if (token_start > state->frequency_separator) { @@ -167,7 +179,6 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st } } - /* Early AMD and Cyrix processors have "tm" suffix for trademark, e.g. * "AMD-K6tm w/ multimedia extensions" * "Cyrix MediaGXtm MMXtm Enhanced" @@ -196,11 +207,13 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st switch (token_length) { case 1: /* - * On some Intel processors there is a space between the first letter of - * the name and the number after it, e.g. - * "Intel(R) Core(TM) i7 CPU X 990 @ 3.47GHz" + * On some Intel processors there is a space between the + * first letter of the name and the number after it, + * e.g. "Intel(R) Core(TM) i7 CPU X 990 @ 3.47GHz" * "Intel(R) Core(TM) CPU Q 820 @ 1.73GHz" - * We want to merge these parts together, in reverse order, i.e. "X 990" -> "990X", "820" -> "820Q" + * We want to merge these parts together, in reverse + * order, i.e. "X 990" + * -> "990X", "820" -> "820Q" */ if (is_upper_letter(token_start[0])) { state->context_upper_letter = token_start; @@ -208,15 +221,17 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st } break; case 2: - /* Erase everything after "w/" in "AMD-K6tm w/ multimedia extensions" */ + /* Erase everything after "w/" in "AMD-K6tm w/ + * multimedia extensions" */ if (erase_matching(token_start, token_length, "w/")) { return false; } /* - * Intel Xeon processors since Ivy Bridge use versions, e.g. - * "Intel Xeon E3-1230 v2" - * Some processor branch strings report them as "V", others report as "v". - * Normalize the former (upper-case) to the latter (lower-case) version + * Intel Xeon processors since Ivy Bridge use versions, + * e.g. "Intel Xeon E3-1230 v2" Some processor branch + * strings report them as "V", others report as + * "v". Normalize the former (upper-case) to the + * latter (lower-case) version */ if (token_start[0] == 'V' && is_digit(token_start[1])) { token_start[0] = 'v'; @@ -234,8 +249,9 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st return true; } /* - * Erase everything after "SOC" on AMD System-on-Chips, e.g. - * "AMD GX-212JC SOC with Radeon(TM) R2E Graphics \0" + * Erase everything after "SOC" on AMD System-on-Chips, + * e.g. "AMD GX-212JC SOC with Radeon(TM) R2E Graphics + * \0" */ if (erase_matching(token_start, token_length, "SOC")) { return false; @@ -258,36 +274,41 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st if (erase_matching(token_start, token_length, "VIA")) { return true; } - /* Erase "IDT" in brand string on early Centaur processors, e.g. "IDT WinChip 2-3D" */ + /* Erase "IDT" in brand string on early Centaur + * processors, e.g. "IDT WinChip 2-3D" */ if (erase_matching(token_start, token_length, "IDT")) { return true; } /* * Erase everything starting with "MMX" in - * "Cyrix MediaGXtm MMXtm Enhanced" ("tm" suffix is removed by this point) + * "Cyrix MediaGXtm MMXtm Enhanced" ("tm" suffix is + * removed by this point) */ if (erase_matching(token_start, token_length, "MMX")) { return false; } /* - * Erase everything starting with "APU" on AMD processors, e.g. - * "AMD A10-4600M APU with Radeon(tm) HD Graphics" - * "AMD A10-7850K APU with Radeon(TM) R7 Graphics" - * "AMD A6-6310 APU with AMD Radeon R4 Graphics" + * Erase everything starting with "APU" on AMD + * processors, e.g. "AMD A10-4600M APU with Radeon(tm) + * HD Graphics" "AMD A10-7850K APU with Radeon(TM) R7 + * Graphics" "AMD A6-6310 APU with AMD Radeon R4 + * Graphics" */ if (erase_matching(token_start, token_length, "APU")) { return false; } /* - * Remember to discard string if it contains "Eng Sample", - * e.g. "Eng Sample, ZD302046W4K43_36/30/20_2/8_A" + * Remember to discard string if it contains "Eng + * Sample", e.g. "Eng Sample, + * ZD302046W4K43_36/30/20_2/8_A" */ if (memcmp(token_start, "Eng", token_length) == 0) { state->context_engineering = token_start; } break; case 4: - /* Remember to erase "Dual Core" in "AMD Athlon(tm) 64 X2 Dual Core Processor 3800+" */ + /* Remember to erase "Dual Core" in "AMD Athlon(tm) 64 + * X2 Dual Core Processor 3800+" */ if (memcmp(token_start, "Dual", token_length) == 0) { state->context_dual = token_start; } @@ -295,10 +316,14 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st if (memcmp(token_start, "Xeon", token_length) == 0) { state->xeon = true; } - /* Erase "Dual Core" in "AMD Athlon(tm) 64 X2 Dual Core Processor 3800+" */ + /* Erase "Dual Core" in "AMD Athlon(tm) 64 X2 Dual Core + * Processor 3800+" + */ if (previousState.context_dual != NULL) { if (memcmp(token_start, "Core", token_length) == 0) { - memset(previousState.context_dual, ' ', (size_t) (token_end - previousState.context_dual)); + memset(previousState.context_dual, + ' ', + (size_t)(token_end - previousState.context_dual)); state->context_core = token_end; return true; } @@ -306,30 +331,32 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st break; case 5: /* - * Erase "Intel" in brand string on Intel processors, e.g. - * "Intel(R) Xeon(R) CPU X3210 @ 2.13GHz" - * "Intel(R) Atom(TM) CPU D2700 @ 2.13GHz" - * "Genuine Intel(R) processor 800MHz" + * Erase "Intel" in brand string on Intel processors, + * e.g. "Intel(R) Xeon(R) CPU X3210 @ 2.13GHz" "Intel(R) + * Atom(TM) CPU D2700 @ 2.13GHz" "Genuine Intel(R) + * processor 800MHz" */ if (erase_matching(token_start, token_length, "Intel")) { return true; } /* - * Erase "Cyrix" in brand string on Cyrix processors, e.g. - * "Cyrix MediaGXtm MMXtm Enhanced" + * Erase "Cyrix" in brand string on Cyrix processors, + * e.g. "Cyrix MediaGXtm MMXtm Enhanced" */ if (erase_matching(token_start, token_length, "Cyrix")) { return true; } /* - * Erase everything following "Geode" (but not "Geode" token itself) on Geode processors, e.g. - * "Geode(TM) Integrated Processor by AMD PCS" - * "Geode(TM) Integrated Processor by National Semi" + * Erase everything following "Geode" (but not "Geode" + * token itself) on Geode processors, e.g. "Geode(TM) + * Integrated Processor by AMD PCS" "Geode(TM) + * Integrated Processor by National Semi" */ if (memcmp(token_start, "Geode", token_length) == 0) { return false; } - /* Remember to erase "model unknown" in "AMD Processor model unknown" */ + /* Remember to erase "model unknown" in "AMD Processor + * model unknown" */ if (memcmp(token_start, "model", token_length) == 0) { state->context_model = token_start; return true; @@ -337,29 +364,33 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st break; case 6: /* - * Erase everything starting with "Radeon" or "RADEON" on AMD APUs, e.g. - * "A8-7670K Radeon R7, 10 Compute Cores 4C+6G" - * "FX-8800P Radeon R7, 12 Compute Cores 4C+8G" - * "A12-9800 RADEON R7, 12 COMPUTE CORES 4C+8G" + * Erase everything starting with "Radeon" or "RADEON" + * on AMD APUs, e.g. "A8-7670K Radeon R7, 10 Compute + * Cores 4C+6G" "FX-8800P Radeon R7, 12 Compute Cores + * 4C+8G" "A12-9800 RADEON R7, 12 COMPUTE CORES 4C+8G" * "A9-9410 RADEON R5, 5 COMPUTE CORES 2C+3G" */ - if (erase_matching(token_start, token_length, "Radeon") || erase_matching(token_start, token_length, "RADEON")) { + if (erase_matching(token_start, token_length, "Radeon") || + erase_matching(token_start, token_length, "RADEON")) { return false; } /* - * Erase "Mobile" when it is not part of the processor name, - * e.g. in "AMD Turion(tm) X2 Ultra Dual-Core Mobile ZM-82" + * Erase "Mobile" when it is not part of the processor + * name, e.g. in "AMD Turion(tm) X2 Ultra Dual-Core + * Mobile ZM-82" */ if (previousState.context_core != NULL) { if (erase_matching(token_start, token_length, "Mobile")) { return true; } } - /* Erase "family" in "Intel(R) Pentium(R) III CPU family 1266MHz" */ + /* Erase "family" in "Intel(R) Pentium(R) III CPU family + * 1266MHz" */ if (erase_matching(token_start, token_length, "family")) { return true; } - /* Discard the string if it contains "Engineering Sample" */ + /* Discard the string if it contains "Engineering + * Sample" */ if (previousState.context_engineering != NULL) { if (memcmp(token_start, "Sample", token_length) == 0) { state->engineering_sample = true; @@ -369,8 +400,8 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st break; case 7: /* - * Erase "Geniune" in brand string on Intel engineering samples, e.g. - * "Genuine Intel(R) processor 800MHz" + * Erase "Geniune" in brand string on Intel engineering + * samples, e.g. "Genuine Intel(R) processor 800MHz" * "Genuine Intel(R) CPU @ 2.13GHz" * "Genuine Intel(R) CPU 0000 @ 1.73GHz" */ @@ -378,45 +409,52 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st return true; } /* - * Erase "12-core" in brand string on AMD Threadripper, e.g. - * "AMD Ryzen Threadripper 1920X 12-Core Processor" + * Erase "12-core" in brand string on AMD Threadripper, + * e.g. "AMD Ryzen Threadripper 1920X 12-Core Processor" */ if (erase_matching(token_start, token_length, "12-Core")) { return true; } /* - * Erase "16-core" in brand string on AMD Threadripper, e.g. - * "AMD Ryzen Threadripper 1950X 16-Core Processor" + * Erase "16-core" in brand string on AMD Threadripper, + * e.g. "AMD Ryzen Threadripper 1950X 16-Core Processor" */ if (erase_matching(token_start, token_length, "16-Core")) { return true; } - /* Erase "model unknown" in "AMD Processor model unknown" */ + /* Erase "model unknown" in "AMD Processor model + * unknown" */ if (previousState.context_model != NULL) { if (memcmp(token_start, "unknown", token_length) == 0) { - memset(previousState.context_model, ' ', token_end - previousState.context_model); + memset(previousState.context_model, + ' ', + token_end - previousState.context_model); return true; } } /* - * Discard the string if it contains "Eng Sample:" or "Eng Sample," e.g. - * "AMD Eng Sample, ZD302046W4K43_36/30/20_2/8_A" - * "AMD Eng Sample: 2D3151A2M88E4_35/31_N" + * Discard the string if it contains "Eng Sample:" or + * "Eng Sample," e.g. "AMD Eng Sample, + * ZD302046W4K43_36/30/20_2/8_A" "AMD Eng Sample: + * 2D3151A2M88E4_35/31_N" */ if (previousState.context_engineering != NULL) { - if (memcmp(token_start, "Sample,", token_length) == 0 || memcmp(token_start, "Sample:", token_length) == 0) { + if (memcmp(token_start, "Sample,", token_length) == 0 || + memcmp(token_start, "Sample:", token_length) == 0) { state->engineering_sample = true; return false; } } break; case 8: - /* Erase "QuadCore" in "VIA QuadCore L4700 @ 1.2+ GHz" */ + /* Erase "QuadCore" in "VIA QuadCore L4700 @ 1.2+ GHz" + */ if (erase_matching(token_start, token_length, "QuadCore")) { state->context_core = token_end; return true; } - /* Erase "Six-Core" in "AMD FX(tm)-6100 Six-Core Processor" */ + /* Erase "Six-Core" in "AMD FX(tm)-6100 Six-Core + * Processor" */ if (erase_matching(token_start, token_length, "Six-Core")) { state->context_core = token_end; return true; @@ -429,7 +467,8 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st if (erase_matching(token_start, token_length, "processor")) { return true; } - /* Erase "Dual-Core" in "Pentium(R) Dual-Core CPU T4200 @ 2.00GHz" */ + /* Erase "Dual-Core" in "Pentium(R) Dual-Core CPU T4200 + * @ 2.00GHz" */ if (erase_matching(token_start, token_length, "Dual-Core")) { state->context_core = token_end; return true; @@ -442,9 +481,9 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st state->context_core = token_end; return true; } - /* Erase "Transmeta" in brand string on Transmeta processors, e.g. - * "Transmeta(tm) Crusoe(tm) Processor TM5800" - * "Transmeta Efficeon(tm) Processor TM8000" + /* Erase "Transmeta" in brand string on Transmeta + * processors, e.g. "Transmeta(tm) Crusoe(tm) Processor + * TM5800" "Transmeta Efficeon(tm) Processor TM8000" */ if (erase_matching(token_start, token_length, "Transmeta")) { return true; @@ -471,8 +510,8 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st return true; } /* - * Remember to discard string if it contains "Engineering Sample", - * e.g. "AMD Engineering Sample" + * Remember to discard string if it contains + * "Engineering Sample", e.g. "AMD Engineering Sample" */ if (memcmp(token_start, "Engineering", token_length) == 0) { state->context_engineering = token_start; @@ -484,31 +523,38 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st memset(token_start, ' ', token_length); return true; } - /* On some Intel processors the last letter of the name is put before the number, - * and an additional space it added, e.g. - * "Intel(R) Core(TM) i7 CPU X 990 @ 3.47GHz" - * "Intel(R) Core(TM) CPU Q 820 @ 1.73GHz" - * "Intel(R) Core(TM) i5 CPU M 480 @ 2.67GHz" - * We fix this issue, i.e. "X 990" -> "990X", "Q 820" -> "820Q" + /* On some Intel processors the last letter of the name is put before + * the number, and an additional space it added, e.g. "Intel(R) Core(TM) + * i7 CPU X 990 @ 3.47GHz" "Intel(R) Core(TM) CPU Q 820 @ 1.73GHz" + * "Intel(R) Core(TM) i5 CPU M 480 @ 2.67GHz" We fix this issue, i.e. + * "X 990" -> "990X", "Q 820" + * -> "820Q" */ if (previousState.context_upper_letter != 0) { - /* A single letter token followed by 2-to-5 digit letter is merged together */ + /* A single letter token followed by 2-to-5 digit letter is + * merged together + */ switch (token_length) { case 2: case 3: case 4: case 5: if (is_number(token_start, token_end)) { - /* Load the previous single-letter token */ + /* Load the previous single-letter token + */ const char letter = *previousState.context_upper_letter; - /* Erase the previous single-letter token */ + /* Erase the previous single-letter + * token */ *previousState.context_upper_letter = ' '; - /* Move the current token one position to the left */ + /* Move the current token one position + * to the left */ move_token(token_start, token_end, token_start - 1); token_start -= 1; /* * Add the letter on the end - * Note: accessing token_start[-1] is safe because this is not the first token + * Note: accessing token_start[-1] is + * safe because this is not the first + * token */ token_end[-1] = letter; } @@ -525,23 +571,22 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st return true; } -uint32_t cpuinfo_x86_normalize_brand_string( - const char raw_name[48], - char normalized_name[48]) -{ +uint32_t cpuinfo_x86_normalize_brand_string(const char raw_name[48], char normalized_name[48]) { normalized_name[0] = '\0'; char name[48]; memcpy(name, raw_name, sizeof(name)); /* * First find the end of the string - * Start search from the end because some brand strings contain zeroes in the middle + * Start search from the end because some brand strings contain zeroes + * in the middle */ char* name_end = &name[48]; while (name_end[-1] == '\0') { /* - * Adject name_end by 1 position and check that we didn't reach the start of the brand string. - * This is possible if all characters are zero. + * Adject name_end by 1 position and check that we didn't reach + * the start of the brand string. This is possible if all + * characters are zero. */ if (--name_end == name) { /* All characters are zeros */ @@ -549,9 +594,10 @@ uint32_t cpuinfo_x86_normalize_brand_string( } } - struct parser_state parser_state = { 0 }; + struct parser_state parser_state = {0}; - /* Now unify all whitespace characters: replace tabs and '\0' with spaces */ + /* Now unify all whitespace characters: replace tabs and '\0' with + * spaces */ { bool inside_parentheses = false; for (char* char_ptr = name; char_ptr != name_end; char_ptr++) { @@ -611,7 +657,8 @@ uint32_t cpuinfo_x86_normalize_brand_string( /* Check if there is some string before the frequency separator. */ if (parser_state.frequency_separator != NULL) { if (is_space(name, parser_state.frequency_separator)) { - /* If only frequency is available, return empty string */ + /* If only frequency is available, return empty string + */ return 0; } } @@ -634,7 +681,8 @@ uint32_t cpuinfo_x86_normalize_brand_string( *output_ptr++ = ' '; } output_ptr = move_token(token_start, char_ptr, output_ptr); - /* Note: char_ptr[-1] exists because there is a token before this space */ + /* Note: char_ptr[-1] exists because + * there is a token before this space */ previous_token_ends_with_dash = (char_ptr[-1] == '-'); } } else { @@ -662,7 +710,7 @@ uint32_t cpuinfo_x86_normalize_brand_string( } else { normalized_name[47] = '\0'; } - return (uint32_t) (output_ptr - normalized_name); + return (uint32_t)(output_ptr - normalized_name); } } @@ -685,24 +733,22 @@ static const char* vendor_string_map[] = { uint32_t cpuinfo_x86_format_package_name( enum cpuinfo_vendor vendor, const char normalized_brand_string[48], - char package_name[CPUINFO_PACKAGE_NAME_MAX]) -{ + char package_name[CPUINFO_PACKAGE_NAME_MAX]) { if (normalized_brand_string[0] == '\0') { package_name[0] = '\0'; return 0; } const char* vendor_string = NULL; - if ((uint32_t) vendor < (uint32_t) CPUINFO_COUNT_OF(vendor_string_map)) { - vendor_string = vendor_string_map[(uint32_t) vendor]; + if ((uint32_t)vendor < (uint32_t)CPUINFO_COUNT_OF(vendor_string_map)) { + vendor_string = vendor_string_map[(uint32_t)vendor]; } if (vendor_string == NULL) { strncpy(package_name, normalized_brand_string, CPUINFO_PACKAGE_NAME_MAX); package_name[CPUINFO_PACKAGE_NAME_MAX - 1] = '\0'; return 0; } else { - snprintf(package_name, CPUINFO_PACKAGE_NAME_MAX, - "%s %s", vendor_string, normalized_brand_string); - return (uint32_t) strlen(vendor_string) + 1; + snprintf(package_name, CPUINFO_PACKAGE_NAME_MAX, "%s %s", vendor_string, normalized_brand_string); + return (uint32_t)strlen(vendor_string) + 1; } } diff --git a/3rdparty/cpuinfo/src/x86/topology.c b/3rdparty/cpuinfo/src/x86/topology.c index 0e83d46835..5253089298 100644 --- a/3rdparty/cpuinfo/src/x86/topology.c +++ b/3rdparty/cpuinfo/src/x86/topology.c @@ -1,25 +1,23 @@ -#include #include +#include #include -#include #include +#include #include #include - enum topology_type { topology_type_invalid = 0, - topology_type_smt = 1, - topology_type_core = 2, + topology_type_smt = 1, + topology_type_core = 2, }; void cpuinfo_x86_detect_topology( uint32_t max_base_index, uint32_t max_extended_index, struct cpuid_regs leaf1, - struct cpuinfo_x86_topology* topology) -{ + struct cpuinfo_x86_topology* topology) { /* * HTT: indicates multi-core/hyper-threading support on this core. * - Intel, AMD: edx[bit 28] in basic info. @@ -34,7 +32,8 @@ void cpuinfo_x86_detect_topology( const struct cpuid_regs leaf0x80000001 = cpuid(UINT32_C(0x80000001)); /* * CmpLegacy: core multi-processing legacy mode. - * - AMD: ecx[bit 1] in extended info (reserved bit on Intel CPUs). + * - AMD: ecx[bit 1] in extended info (reserved bit on + * Intel CPUs). */ amd_cmp_legacy = !!(leaf0x80000001.ecx & UINT32_C(0x00000002)); } @@ -42,36 +41,52 @@ void cpuinfo_x86_detect_topology( if (max_extended_index >= UINT32_C(0x80000008)) { const struct cpuid_regs leaf0x80000008 = cpuid(UINT32_C(0x80000008)); /* - * NC: number of physical cores - 1. The number of cores in the processor is NC+1. - * - AMD: ecx[bits 0-7] in leaf 0x80000008 (reserved zero bits on Intel CPUs). + * NC: number of physical cores - 1. The number + * of cores in the processor is NC+1. + * - AMD: ecx[bits 0-7] in leaf 0x80000008 + * (reserved zero bits on Intel CPUs). */ const uint32_t cores_per_processor = 1 + (leaf0x80000008.ecx & UINT32_C(0x000000FF)); topology->core_bits_length = bit_length(cores_per_processor); - cpuinfo_log_debug("HTT: APIC ID = %08"PRIx32", cores per processor = %"PRIu32, apic_id, cores_per_processor); + cpuinfo_log_debug( + "HTT: APIC ID = %08" PRIx32 ", cores per processor = %" PRIu32, + apic_id, + cores_per_processor); } else { /* - * LogicalProcessorCount: the number of cores per processor. - * - AMD: ebx[bits 16-23] in basic info (different interpretation on Intel CPUs). + * LogicalProcessorCount: the number of cores + * per processor. + * - AMD: ebx[bits 16-23] in basic info + * (different interpretation on Intel CPUs). */ const uint32_t cores_per_processor = (leaf1.ebx >> 16) & UINT32_C(0x000000FF); if (cores_per_processor != 0) { topology->core_bits_length = bit_length(cores_per_processor); } - cpuinfo_log_debug("HTT: APIC ID = %08"PRIx32", cores per processor = %"PRIu32, apic_id, cores_per_processor); + cpuinfo_log_debug( + "HTT: APIC ID = %08" PRIx32 ", cores per processor = %" PRIu32, + apic_id, + cores_per_processor); } } else { /* - * Maximum number of addressable IDs for logical processors in this physical package. - * - Intel: ebx[bits 16-23] in basic info (different interpretation on AMD CPUs). + * Maximum number of addressable IDs for logical + * processors in this physical package. + * - Intel: ebx[bits 16-23] in basic info (different + * interpretation on AMD CPUs). */ const uint32_t logical_processors = (leaf1.ebx >> 16) & UINT32_C(0x000000FF); if (logical_processors != 0) { const uint32_t log2_max_logical_processors = bit_length(logical_processors); - const uint32_t log2_max_threads_per_core = log2_max_logical_processors - topology->core_bits_length; + const uint32_t log2_max_threads_per_core = + log2_max_logical_processors - topology->core_bits_length; topology->core_bits_offset = log2_max_threads_per_core; topology->thread_bits_length = log2_max_threads_per_core; } - cpuinfo_log_debug("HTT: APIC ID = %08"PRIx32", logical processors = %"PRIu32, apic_id, logical_processors); + cpuinfo_log_debug( + "HTT: APIC ID = %08" PRIx32 ", logical processors = %" PRIu32, + apic_id, + logical_processors); } } @@ -84,43 +99,64 @@ void cpuinfo_x86_detect_topology( uint32_t level = 0; uint32_t type; uint32_t total_shift = 0; - topology->thread_bits_offset = topology->thread_bits_length = 0; - topology->core_bits_offset = topology->core_bits_length = 0; + topology->thread_bits_offset = topology->thread_bits_length = 0; + topology->core_bits_offset = topology->core_bits_length = 0; do { const struct cpuid_regs leafB = cpuidex(UINT32_C(0xB), level); type = (leafB.ecx >> 8) & UINT32_C(0x000000FF); const uint32_t level_shift = leafB.eax & UINT32_C(0x0000001F); - const uint32_t x2apic_id = leafB.edx; + const uint32_t x2apic_id = leafB.edx; apic_id = x2apic_id; switch (type) { case topology_type_invalid: break; case topology_type_smt: - cpuinfo_log_debug("x2 level %"PRIu32": APIC ID = %08"PRIx32", " - "type SMT, shift %"PRIu32", total shift %"PRIu32, - level, apic_id, level_shift, total_shift); + cpuinfo_log_debug( + "x2 level %" PRIu32 ": APIC ID = %08" PRIx32 + ", " + "type SMT, shift %" PRIu32 ", total shift %" PRIu32, + level, + apic_id, + level_shift, + total_shift); topology->thread_bits_offset = total_shift; topology->thread_bits_length = level_shift; break; case topology_type_core: - cpuinfo_log_debug("x2 level %"PRIu32": APIC ID = %08"PRIx32", " - "type core, shift %"PRIu32", total shift %"PRIu32, - level, apic_id, level_shift, total_shift); + cpuinfo_log_debug( + "x2 level %" PRIu32 ": APIC ID = %08" PRIx32 + ", " + "type core, shift %" PRIu32 ", total shift %" PRIu32, + level, + apic_id, + level_shift, + total_shift); topology->core_bits_offset = total_shift; topology->core_bits_length = level_shift; break; default: - cpuinfo_log_warning("unexpected topology type %"PRIu32" (offset %"PRIu32", length %"PRIu32") " - "reported in leaf 0x0000000B is ignored", type, total_shift, level_shift); + cpuinfo_log_warning( + "unexpected topology type %" PRIu32 " (offset %" PRIu32 + ", length %" PRIu32 + ") " + "reported in leaf 0x0000000B is ignored", + type, + total_shift, + level_shift); break; } total_shift += level_shift; level += 1; } while (type != 0); - cpuinfo_log_debug("x2APIC ID 0x%08"PRIx32", " - "SMT offset %"PRIu32" length %"PRIu32", core offset %"PRIu32" length %"PRIu32, apic_id, - topology->thread_bits_offset, topology->thread_bits_length, - topology->core_bits_offset, topology->core_bits_length); + cpuinfo_log_debug( + "x2APIC ID 0x%08" PRIx32 + ", " + "SMT offset %" PRIu32 " length %" PRIu32 ", core offset %" PRIu32 " length %" PRIu32, + apic_id, + topology->thread_bits_offset, + topology->thread_bits_length, + topology->core_bits_offset, + topology->core_bits_length); } topology->apic_id = apic_id; diff --git a/3rdparty/cpuinfo/src/x86/uarch.c b/3rdparty/cpuinfo/src/x86/uarch.c index a38d7b0555..b291ebcf0c 100644 --- a/3rdparty/cpuinfo/src/x86/uarch.c +++ b/3rdparty/cpuinfo/src/x86/uarch.c @@ -3,11 +3,9 @@ #include #include - enum cpuinfo_uarch cpuinfo_x86_decode_uarch( enum cpuinfo_vendor vendor, - const struct cpuinfo_x86_model_info* model_info) -{ + const struct cpuinfo_x86_model_info* model_info) { switch (vendor) { case cpuinfo_vendor_intel: switch (model_info->family) { @@ -15,8 +13,12 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( case 0x05: switch (model_info->model) { case 0x01: // Pentium (60, 66) - case 0x02: // Pentium (75, 90, 100, 120, 133, 150, 166, 200) - case 0x03: // Pentium OverDrive for Intel486-based systems + case 0x02: // Pentium (75, 90, + // 100, 120, 133, + // 150, 166, 200) + case 0x03: // Pentium OverDrive + // for Intel486-based + // systems case 0x04: // Pentium MMX return cpuinfo_uarch_p5; case 0x09: @@ -29,39 +31,109 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( /* Mainstream cores */ #if CPUINFO_ARCH_X86 case 0x01: // Pentium Pro - case 0x03: // Pentium II (Klamath) and Pentium II Overdrive - case 0x05: // Pentium II (Deschutes, Tonga), Pentium II Celeron (Covington), Pentium II Xeon (Drake) - case 0x06: // Pentium II (Dixon), Pentium II Celeron (Mendocino) - case 0x07: // Pentium III (Katmai), Pentium III Xeon (Tanner) - case 0x08: // Pentium III (Coppermine), Pentium II Celeron (Coppermine-128), Pentium III Xeon (Cascades) - case 0x0A: // Pentium III Xeon (Cascades-2MB) - case 0x0B: // Pentium III (Tualatin), Pentium III Celeron (Tualatin-256) + case 0x03: // Pentium II + // (Klamath) and + // Pentium II + // Overdrive + case 0x05: // Pentium II + // (Deschutes, + // Tonga), Pentium II + // Celeron + // (Covington), + // Pentium II Xeon + // (Drake) + case 0x06: // Pentium II + // (Dixon), Pentium + // II Celeron + // (Mendocino) + case 0x07: // Pentium III + // (Katmai), Pentium + // III Xeon (Tanner) + case 0x08: // Pentium III + // (Coppermine), + // Pentium II Celeron + // (Coppermine-128), + // Pentium III Xeon + // (Cascades) + case 0x0A: // Pentium III Xeon + // (Cascades-2MB) + case 0x0B: // Pentium III + // (Tualatin), + // Pentium III + // Celeron + // (Tualatin-256) return cpuinfo_uarch_p6; - case 0x09: // Pentium M (Banias), Pentium M Celeron (Banias-0, Banias-512) - case 0x0D: // Pentium M (Dothan), Pentium M Celeron (Dothan-512, Dothan-1024) - case 0x15: // Intel 80579 (Tolapai) + case 0x09: // Pentium M + // (Banias), Pentium + // M Celeron + // (Banias-0, + // Banias-512) + case 0x0D: // Pentium M + // (Dothan), Pentium + // M Celeron + // (Dothan-512, + // Dothan-1024) + case 0x15: // Intel 80579 + // (Tolapai) return cpuinfo_uarch_dothan; - case 0x0E: // Core Solo/Duo (Yonah), Pentium Dual-Core T2xxx (Yonah), Celeron M (Yonah-512, Yonah-1024), Dual-Core Xeon (Sossaman) + case 0x0E: // Core Solo/Duo + // (Yonah), Pentium + // Dual-Core T2xxx + // (Yonah), Celeron M + // (Yonah-512, + // Yonah-1024), + // Dual-Core Xeon + // (Sossaman) return cpuinfo_uarch_yonah; #endif /* CPUINFO_ARCH_X86 */ - case 0x0F: // Core 2 Duo (Conroe, Conroe-2M, Merom), Core 2 Quad (Tigerton), Xeon (Woodcrest, Clovertown, Kentsfield) - case 0x16: // Celeron (Conroe-L, Merom-L), Core 2 Duo (Merom) + case 0x0F: // Core 2 Duo + // (Conroe, + // Conroe-2M, Merom), + // Core 2 Quad + // (Tigerton), Xeon + // (Woodcrest, + // Clovertown, + // Kentsfield) + case 0x16: // Celeron (Conroe-L, + // Merom-L), Core 2 + // Duo (Merom) return cpuinfo_uarch_conroe; - case 0x17: // Core 2 Duo (Penryn-3M), Core 2 Quad (Yorkfield), Core 2 Extreme (Yorkfield), Xeon (Harpertown), Pentium Dual-Core (Penryn) + case 0x17: // Core 2 Duo + // (Penryn-3M), Core + // 2 Quad + // (Yorkfield), Core + // 2 Extreme + // (Yorkfield), Xeon + // (Harpertown), + // Pentium Dual-Core + // (Penryn) case 0x1D: // Xeon (Dunnington) return cpuinfo_uarch_penryn; - case 0x1A: // Core iX (Bloomfield), Xeon (Gainestown) - case 0x1E: // Core iX (Lynnfield, Clarksfield) - case 0x1F: // Core iX (Havendale) + case 0x1A: // Core iX + // (Bloomfield), Xeon + // (Gainestown) + case 0x1E: // Core iX + // (Lynnfield, + // Clarksfield) + case 0x1F: // Core iX + // (Havendale) case 0x2E: // Xeon (Beckton) - case 0x25: // Core iX (Clarkdale) - case 0x2C: // Core iX (Gulftown), Xeon (Gulftown) + case 0x25: // Core iX + // (Clarkdale) + case 0x2C: // Core iX + // (Gulftown), Xeon + // (Gulftown) case 0x2F: // Xeon (Eagleton) return cpuinfo_uarch_nehalem; - case 0x2A: // Core iX (Sandy Bridge) - case 0x2D: // Core iX (Sandy Bridge-E), Xeon (Sandy Bridge EP/EX) + case 0x2A: // Core iX (Sandy + // Bridge) + case 0x2D: // Core iX (Sandy + // Bridge-E), Xeon + // (Sandy Bridge + // EP/EX) return cpuinfo_uarch_sandy_bridge; - case 0x3A: // Core iX (Ivy Bridge) + case 0x3A: // Core iX (Ivy + // Bridge) case 0x3E: // Ivy Bridge-E return cpuinfo_uarch_ivy_bridge; case 0x3C: @@ -74,15 +146,21 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( case 0x4F: // Broadwell-E case 0x56: // Broadwell-DE return cpuinfo_uarch_broadwell; - case 0x4E: // Sky Lake Client Y/U - case 0x55: // Sky/Cascade/Cooper Lake Server - case 0x5E: // Sky Lake Client DT/H/S - case 0x8E: // Kaby/Whiskey/Amber/Comet Lake Y/U - case 0x9E: // Kaby/Coffee Lake DT/H/S + case 0x4E: // Sky Lake Client + // Y/U + case 0x55: // Sky/Cascade/Cooper + // Lake Server + case 0x5E: // Sky Lake Client + // DT/H/S + case 0x8E: // Kaby/Whiskey/Amber/Comet + // Lake Y/U + case 0x9E: // Kaby/Coffee Lake + // DT/H/S case 0xA5: // Comet Lake H/S case 0xA6: // Comet Lake U/Y return cpuinfo_uarch_sky_lake; - case 0x66: // Cannon Lake (Core i3-8121U) + case 0x66: // Cannon Lake (Core + // i3-8121U) return cpuinfo_uarch_palm_cove; case 0x6A: // Ice Lake-DE case 0x6C: // Ice Lake-SP @@ -91,12 +169,15 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( return cpuinfo_uarch_sunny_cove; /* Low-power cores */ - case 0x1C: // Diamondville, Silverthorne, Pineview + case 0x1C: // Diamondville, + // Silverthorne, + // Pineview case 0x26: // Tunnel Creek return cpuinfo_uarch_bonnell; case 0x27: // Medfield case 0x35: // Cloverview - case 0x36: // Cedarview, Centerton + case 0x36: // Cedarview, + // Centerton return cpuinfo_uarch_saltwell; case 0x37: // Bay Trail case 0x4A: // Merrifield @@ -104,8 +185,10 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( case 0x5A: // Moorefield case 0x5D: // SoFIA return cpuinfo_uarch_silvermont; - case 0x4C: // Braswell, Cherry Trail - case 0x75: // Spreadtrum SC9853I-IA + case 0x4C: // Braswell, Cherry + // Trail + case 0x75: // Spreadtrum + // SC9853I-IA return cpuinfo_uarch_airmont; case 0x5C: // Apollo Lake case 0x5F: // Denverton @@ -122,14 +205,48 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( break; case 0x0F: switch (model_info->model) { - case 0x00: // Pentium 4 Xeon (Foster) - case 0x01: // Pentium 4 Celeron (Willamette-128), Pentium 4 Xeon (Foster, Foster MP) - case 0x02: // Pentium 4 (Northwood), Pentium 4 EE (Gallatin), Pentium 4 Celeron (Northwood-128, Northwood-256), Pentium 4 Xeon (Gallatin DP, Prestonia) + case 0x00: // Pentium 4 Xeon + // (Foster) + case 0x01: // Pentium 4 Celeron + // (Willamette-128), + // Pentium 4 Xeon + // (Foster, Foster + // MP) + case 0x02: // Pentium 4 + // (Northwood), + // Pentium 4 EE + // (Gallatin), + // Pentium 4 Celeron + // (Northwood-128, + // Northwood-256), + // Pentium 4 Xeon + // (Gallatin DP, + // Prestonia) return cpuinfo_uarch_willamette; break; - case 0x03: // Pentium 4 (Prescott), Pentium 4 Xeon (Nocona) - case 0x04: // Pentium 4 (Prescott-2M), Pentium 4 EE (Prescott-2M), Pentium D (Smithfield), Celeron D (Prescott-256), Pentium 4 Xeon (Cranford, Irwindale, Paxville) - case 0x06: // Pentium 4 (Cedar Mill), Pentium D EE (Presler), Celeron D (Cedar Mill), Pentium 4 Xeon (Dempsey, Tulsa) + case 0x03: // Pentium 4 + // (Prescott), + // Pentium 4 Xeon + // (Nocona) + case 0x04: // Pentium 4 + // (Prescott-2M), + // Pentium 4 EE + // (Prescott-2M), + // Pentium D + // (Smithfield), + // Celeron D + // (Prescott-256), + // Pentium 4 Xeon + // (Cranford, + // Irwindale, + // Paxville) + case 0x06: // Pentium 4 (Cedar + // Mill), Pentium D + // EE (Presler), + // Celeron D (Cedar + // Mill), Pentium 4 + // Xeon (Dempsey, + // Tulsa) return cpuinfo_uarch_prescott; } break; @@ -166,8 +283,10 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( return cpuinfo_uarch_bobcat; case 0x15: switch (model_info->model) { - case 0x00: // Engineering samples - case 0x01: // Zambezi, Interlagos + case 0x00: // Engineering + // samples + case 0x01: // Zambezi, + // Interlagos return cpuinfo_uarch_bulldozer; case 0x02: // Vishera case 0x10: // Trinity @@ -184,11 +303,19 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( switch (model_info->extended_model) { case 0x0: return cpuinfo_uarch_bulldozer; - case 0x1: // No L3 cache - case 0x2: // With L3 cache + case 0x1: // No + // L3 + // cache + case 0x2: // With + // L3 + // cache return cpuinfo_uarch_piledriver; - case 0x3: // With L3 cache - case 0x4: // No L3 cache + case 0x3: // With + // L3 + // cache + case 0x4: // No + // L3 + // cache return cpuinfo_uarch_steamroller; } break; @@ -202,29 +329,61 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( } case 0x17: switch (model_info->extended_model) { - case 0x0: // model 01h -> 14 nm Naples/Whitehaven/Summit Ridge/Snowy Owl, model 08h -> 12 nm Colfax/Pinnacle Ridge - case 0x1: // model 11h -> 14 nm Raven Ridge/Great Horned Owl, model 18h -> 14 nm Banded Kestrel / 12 nm Picasso + case 0x0: // model 01h -> 14 nm + // Naples/Whitehaven/Summit + // Ridge/Snowy Owl, + // model 08h -> 12 nm + // Colfax/Pinnacle + // Ridge + case 0x1: // model 11h -> 14 nm + // Raven Ridge/Great + // Horned Owl, model + // 18h -> 14 nm Banded + // Kestrel / 12 nm + // Picasso return cpuinfo_uarch_zen; - case 0x3: // model 31h -> Rome/Castle Peak - case 0x4: // model 47h -> Xbox Series X - case 0x6: // model 60h -> Renoir/Grey Hawk, model 68h -> Lucienne - case 0x7: // model 71h -> Matisse - case 0x9: // model 90h -> Van Gogh, model 98h -> Mero + case 0x3: // model 31h -> + // Rome/Castle Peak + case 0x4: // model 47h -> Xbox + // Series X + case 0x6: // model 60h -> + // Renoir/Grey Hawk, + // model 68h -> + // Lucienne + case 0x7: // model 71h -> + // Matisse + case 0x9: // model 90h -> Van + // Gogh, model 98h -> + // Mero return cpuinfo_uarch_zen2; } break; case 0x19: switch (model_info->extended_model) { - case 0x0: // model 00h -> Genesis, model 01h -> Milan, model 08h -> Chagall - case 0x2: // model 21h -> Vermeer - case 0x3: // model 30h -> Badami, Trento - case 0x4: // model 40h -> Rembrandt - case 0x5: // model 50h -> Cezanne + case 0x0: // model 00h -> + // Genesis, model 01h + // -> Milan, model 08h + // -> Chagall + case 0x2: // model 21h -> + // Vermeer + case 0x3: // model 30h -> + // Badami, Trento + case 0x4: // model 40h -> + // Rembrandt + case 0x5: // model 50h -> + // Cezanne return cpuinfo_uarch_zen3; - case 0x1: // model 10h..1Fh -> Stones - case 0x6: // model 60h..6Fh -> Raphael - case 0x7: // model 70h..77h -> Phoenix/Hawkpoint1, model 78h..7Fh -> Phoenix 2/Hawkpoint2 - case 0xA: // model A0h..AFh -> Stones-Dense + case 0x1: // model 10h..1Fh -> + // Stones + case 0x6: // model 60h..6Fh -> + // Raphael + case 0x7: // model 70h..77h -> + // Phoenix/Hawkpoint1, + // model 78h..7Fh -> + // Phoenix + // 2/Hawkpoint2 + case 0xA: // model A0h..AFh -> + // Stones-Dense return cpuinfo_uarch_zen4; } break; diff --git a/3rdparty/cpuinfo/src/x86/vendor.c b/3rdparty/cpuinfo/src/x86/vendor.c index bad50fa959..eaccef5ced 100644 --- a/3rdparty/cpuinfo/src/x86/vendor.c +++ b/3rdparty/cpuinfo/src/x86/vendor.c @@ -3,7 +3,6 @@ #include #include - /* Intel vendor string: "GenuineIntel" */ #define Genu UINT32_C(0x756E6547) #define ineI UINT32_C(0x49656E69) @@ -15,8 +14,8 @@ #define cAMD UINT32_C(0x444D4163) #define AMDi UINT32_C(0x69444D41) #define sbet UINT32_C(0x74656273) -#define ter UINT32_C(0x21726574) -#define AMD UINT32_C(0x20444D41) +#define ter UINT32_C(0x21726574) +#define AMD UINT32_C(0x20444D41) #define ISBE UINT32_C(0x45425349) #define TTER UINT32_C(0x52455454) @@ -24,7 +23,7 @@ #define Cent UINT32_C(0x746E6543) #define aurH UINT32_C(0x48727561) #define auls UINT32_C(0x736C7561) -#define VIA UINT32_C(0x20414956) +#define VIA UINT32_C(0x20414956) /* Hygon vendor string: "HygonGenuine" */ #define Hygo UINT32_C(0x6F677948) @@ -49,10 +48,10 @@ /* NSC vendor string: "Geode by NSC" */ #define Geod UINT32_C(0x646F6547) #define e_by UINT32_C(0x79622065) -#define NSC UINT32_C(0x43534E20) +#define NSC UINT32_C(0x43534E20) /* SiS vendor string: "SiS SiS SiS " */ -#define SiS UINT32_C(0x20536953) +#define SiS UINT32_C(0x20536953) /* NexGen vendor string: "NexGenDriven" */ #define NexG UINT32_C(0x4778654E) @@ -60,17 +59,16 @@ #define iven UINT32_C(0x6E657669) /* UMC vendor string: "UMC UMC UMC " */ -#define UMC UINT32_C(0x20434D55) +#define UMC UINT32_C(0x20434D55) /* RDC vendor string: "Genuine RDC" */ -#define ine UINT32_C(0x20656E69) -#define RDC UINT32_C(0x43445220) +#define ine UINT32_C(0x20656E69) +#define RDC UINT32_C(0x43445220) /* D&MP vendor string: "Vortex86 SoC" */ #define Vort UINT32_C(0x74726F56) #define ex86 UINT32_C(0x36387865) -#define SoC UINT32_C(0x436F5320) - +#define SoC UINT32_C(0x436F5320) enum cpuinfo_vendor cpuinfo_x86_decode_vendor(uint32_t ebx, uint32_t ecx, uint32_t edx) { switch (ebx) { diff --git a/3rdparty/cpuinfo/src/x86/windows/api.h b/3rdparty/cpuinfo/src/x86/windows/api.h index 33d917e0d2..4f6df0f071 100644 --- a/3rdparty/cpuinfo/src/x86/windows/api.h +++ b/3rdparty/cpuinfo/src/x86/windows/api.h @@ -9,15 +9,17 @@ struct cpuinfo_arm_linux_processor { /** - * Minimum processor ID on the package which includes this logical processor. - * This value can serve as an ID for the cluster of logical processors: it is the - * same for all logical processors on the same package. + * Minimum processor ID on the package which includes this logical + * processor. This value can serve as an ID for the cluster of logical + * processors: it is the same for all logical processors on the same + * package. */ uint32_t package_leader_id; /** - * Minimum processor ID on the core which includes this logical processor. - * This value can serve as an ID for the cluster of logical processors: it is the - * same for all logical processors on the same package. + * Minimum processor ID on the core which includes this logical + * processor. This value can serve as an ID for the cluster of logical + * processors: it is the same for all logical processors on the same + * package. */ /** * Number of logical processors in the package. @@ -25,14 +27,16 @@ struct cpuinfo_arm_linux_processor { uint32_t package_processor_count; /** * Maximum frequency, in kHZ. - * The value is parsed from /sys/devices/system/cpu/cpu/cpufreq/cpuinfo_max_freq - * If failed to read or parse the file, the value is 0. + * The value is parsed from + * /sys/devices/system/cpu/cpu/cpufreq/cpuinfo_max_freq If failed to + * read or parse the file, the value is 0. */ uint32_t max_frequency; /** * Minimum frequency, in kHZ. - * The value is parsed from /sys/devices/system/cpu/cpu/cpufreq/cpuinfo_min_freq - * If failed to read or parse the file, the value is 0. + * The value is parsed from + * /sys/devices/system/cpu/cpu/cpufreq/cpuinfo_min_freq If failed to + * read or parse the file, the value is 0. */ uint32_t min_frequency; /** Linux processor ID */ diff --git a/3rdparty/cpuinfo/src/x86/windows/init.c b/3rdparty/cpuinfo/src/x86/windows/init.c index 274075c029..d23328021b 100644 --- a/3rdparty/cpuinfo/src/x86/windows/init.c +++ b/3rdparty/cpuinfo/src/x86/windows/init.c @@ -1,38 +1,37 @@ -#include #include +#include #include #include #include -#include #include #include +#include #include #ifdef __GNUC__ - #define CPUINFO_ALLOCA __builtin_alloca +#define CPUINFO_ALLOCA __builtin_alloca #else - #define CPUINFO_ALLOCA _alloca +#define CPUINFO_ALLOCA _alloca #endif - static inline uint32_t bit_mask(uint32_t bits) { return (UINT32_C(1) << bits) - UINT32_C(1); } static inline uint32_t low_index_from_kaffinity(KAFFINITY kaffinity) { - #if defined(_M_X64) || defined(_M_AMD64) - unsigned long index; - _BitScanForward64(&index, (unsigned __int64) kaffinity); - return (uint32_t) index; - #elif defined(_M_IX86) - unsigned long index; - _BitScanForward(&index, (unsigned long) kaffinity); - return (uint32_t) index; - #else - #error Platform-specific implementation required - #endif +#if defined(_M_X64) || defined(_M_AMD64) + unsigned long index; + _BitScanForward64(&index, (unsigned __int64)kaffinity); + return (uint32_t)index; +#elif defined(_M_IX86) + unsigned long index; + _BitScanForward(&index, (unsigned long)kaffinity); + return (uint32_t)index; +#else +#error Platform-specific implementation required +#endif } static void cpuinfo_x86_count_caches( @@ -43,14 +42,13 @@ static void cpuinfo_x86_count_caches( uint32_t* l1d_count_ptr, uint32_t* l2_count_ptr, uint32_t* l3_count_ptr, - uint32_t* l4_count_ptr) -{ + uint32_t* l4_count_ptr) { uint32_t l1i_count = 0, l1d_count = 0, l2_count = 0, l3_count = 0, l4_count = 0; uint32_t last_l1i_id = UINT32_MAX, last_l1d_id = UINT32_MAX; uint32_t last_l2_id = UINT32_MAX, last_l3_id = UINT32_MAX, last_l4_id = UINT32_MAX; for (uint32_t i = 0; i < processors_count; i++) { const uint32_t apic_id = processors[i].apic_id; - cpuinfo_log_debug("APID ID %"PRIu32": logical processor %"PRIu32, apic_id, i); + cpuinfo_log_debug("APID ID %" PRIu32 ": logical processor %" PRIu32, apic_id, i); if (x86_processor->cache.l1i.size != 0) { const uint32_t l1i_id = apic_id & ~bit_mask(x86_processor->cache.l1i.apic_bits); @@ -90,9 +88,9 @@ static void cpuinfo_x86_count_caches( } *l1i_count_ptr = l1i_count; *l1d_count_ptr = l1d_count; - *l2_count_ptr = l2_count; - *l3_count_ptr = l3_count; - *l4_count_ptr = l4_count; + *l2_count_ptr = l2_count; + *l3_count_ptr = l3_count; + *l4_count_ptr = l4_count; } static bool cpuinfo_x86_windows_is_wine(void) { @@ -126,36 +124,38 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV cpuinfo_x86_normalize_brand_string(x86_processor.brand_string, brand_string); const uint32_t thread_bits_mask = bit_mask(x86_processor.topology.thread_bits_length); - const uint32_t core_bits_mask = bit_mask(x86_processor.topology.core_bits_length); - const uint32_t package_bits_offset = max( - x86_processor.topology.thread_bits_offset + x86_processor.topology.thread_bits_length, - x86_processor.topology.core_bits_offset + x86_processor.topology.core_bits_length); + const uint32_t core_bits_mask = bit_mask(x86_processor.topology.core_bits_length); + const uint32_t package_bits_offset = + max(x86_processor.topology.thread_bits_offset + x86_processor.topology.thread_bits_length, + x86_processor.topology.core_bits_offset + x86_processor.topology.core_bits_length); - /* WINE doesn't implement GetMaximumProcessorGroupCount and aborts when calling it */ - const uint32_t max_group_count = is_wine ? 1 : (uint32_t) GetMaximumProcessorGroupCount(); - cpuinfo_log_debug("detected %"PRIu32" processor groups", max_group_count); + /* WINE doesn't implement GetMaximumProcessorGroupCount and aborts when + * calling it */ + const uint32_t max_group_count = is_wine ? 1 : (uint32_t)GetMaximumProcessorGroupCount(); + cpuinfo_log_debug("detected %" PRIu32 " processor groups", max_group_count); uint32_t processors_count = 0; - uint32_t* processors_per_group = (uint32_t*) CPUINFO_ALLOCA(max_group_count * sizeof(uint32_t)); + uint32_t* processors_per_group = (uint32_t*)CPUINFO_ALLOCA(max_group_count * sizeof(uint32_t)); for (uint32_t i = 0; i < max_group_count; i++) { - processors_per_group[i] = GetMaximumProcessorCount((WORD) i); - cpuinfo_log_debug("detected %"PRIu32" processors in group %"PRIu32, - processors_per_group[i], i); + processors_per_group[i] = GetMaximumProcessorCount((WORD)i); + cpuinfo_log_debug("detected %" PRIu32 " processors in group %" PRIu32, processors_per_group[i], i); processors_count += processors_per_group[i]; } - uint32_t* processors_before_group = (uint32_t*) CPUINFO_ALLOCA(max_group_count * sizeof(uint32_t)); + uint32_t* processors_before_group = (uint32_t*)CPUINFO_ALLOCA(max_group_count * sizeof(uint32_t)); for (uint32_t i = 0, count = 0; i < max_group_count; i++) { processors_before_group[i] = count; - cpuinfo_log_debug("detected %"PRIu32" processors before group %"PRIu32, - processors_before_group[i], i); + cpuinfo_log_debug( + "detected %" PRIu32 " processors before group %" PRIu32, processors_before_group[i], i); count += processors_per_group[i]; } processors = HeapAlloc(heap, HEAP_ZERO_MEMORY, processors_count * sizeof(struct cpuinfo_processor)); if (processors == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" logical processors", - processors_count * sizeof(struct cpuinfo_processor), processors_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " logical processors", + processors_count * sizeof(struct cpuinfo_processor), + processors_count); goto cleanup; } @@ -163,8 +163,9 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV if (GetLogicalProcessorInformationEx(RelationProcessorCore, NULL, &cores_info_size) == FALSE) { const DWORD last_error = GetLastError(); if (last_error != ERROR_INSUFFICIENT_BUFFER) { - cpuinfo_log_error("failed to query size of processor cores information: error %"PRIu32, - (uint32_t) last_error); + cpuinfo_log_error( + "failed to query size of processor cores information: error %" PRIu32, + (uint32_t)last_error); goto cleanup; } } @@ -173,8 +174,9 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV if (GetLogicalProcessorInformationEx(RelationProcessorPackage, NULL, &packages_info_size) == FALSE) { const DWORD last_error = GetLastError(); if (last_error != ERROR_INSUFFICIENT_BUFFER) { - cpuinfo_log_error("failed to query size of processor packages information: error %"PRIu32, - (uint32_t) last_error); + cpuinfo_log_error( + "failed to query size of processor packages information: error %" PRIu32, + (uint32_t)last_error); goto cleanup; } } @@ -183,27 +185,27 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV processor_infos = HeapAlloc(heap, 0, max_info_size); if (processor_infos == NULL) { - cpuinfo_log_error("failed to allocate %"PRIu32" bytes for logical processor information", - (uint32_t) max_info_size); + cpuinfo_log_error( + "failed to allocate %" PRIu32 " bytes for logical processor information", + (uint32_t)max_info_size); goto cleanup; } if (GetLogicalProcessorInformationEx(RelationProcessorPackage, processor_infos, &max_info_size) == FALSE) { - cpuinfo_log_error("failed to query processor packages information: error %"PRIu32, - (uint32_t) GetLastError()); + cpuinfo_log_error( + "failed to query processor packages information: error %" PRIu32, (uint32_t)GetLastError()); goto cleanup; } uint32_t packages_count = 0; PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX packages_info_end = - (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX) ((uintptr_t) processor_infos + packages_info_size); - for (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX package_info = processor_infos; - package_info < packages_info_end; - package_info = (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX) ((uintptr_t) package_info + package_info->Size)) - { + (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX)((uintptr_t)processor_infos + packages_info_size); + for (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX package_info = processor_infos; package_info < packages_info_end; + package_info = (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX)((uintptr_t)package_info + package_info->Size)) { if (package_info->Relationship != RelationProcessorPackage) { - cpuinfo_log_warning("unexpected processor info type (%"PRIu32") for processor package information", - (uint32_t) package_info->Relationship); + cpuinfo_log_warning( + "unexpected processor info type (%" PRIu32 ") for processor package information", + (uint32_t)package_info->Relationship); continue; } @@ -211,19 +213,23 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV const uint32_t package_id = packages_count++; /* Reconstruct package part of APIC ID */ const uint32_t package_apic_id = package_id << package_bits_offset; - /* Iterate processor groups and set the package part of APIC ID */ + /* Iterate processor groups and set the package part of APIC ID + */ for (uint32_t i = 0; i < package_info->Processor.GroupCount; i++) { const uint32_t group_id = package_info->Processor.GroupMask[i].Group; - /* Global index of the first logical processor belonging to this group */ + /* Global index of the first logical processor belonging + * to this group */ const uint32_t group_processors_start = processors_before_group[group_id]; - /* Bitmask representing processors in this group belonging to this package */ + /* Bitmask representing processors in this group + * belonging to this package + */ KAFFINITY group_processors_mask = package_info->Processor.GroupMask[i].Mask; while (group_processors_mask != 0) { const uint32_t group_processor_id = low_index_from_kaffinity(group_processors_mask); const uint32_t processor_id = group_processors_start + group_processor_id; - processors[processor_id].package = (const struct cpuinfo_package*) NULL + package_id; - processors[processor_id].windows_group_id = (uint16_t) group_id; - processors[processor_id].windows_processor_id = (uint16_t) group_processor_id; + processors[processor_id].package = (const struct cpuinfo_package*)NULL + package_id; + processors[processor_id].windows_group_id = (uint16_t)group_id; + processors[processor_id].windows_processor_id = (uint16_t)group_processor_id; processors[processor_id].apic_id = package_apic_id; /* Reset the lowest bit in affinity mask */ @@ -234,44 +240,50 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV max_info_size = max(cores_info_size, packages_info_size); if (GetLogicalProcessorInformationEx(RelationProcessorCore, processor_infos, &max_info_size) == FALSE) { - cpuinfo_log_error("failed to query processor cores information: error %"PRIu32, - (uint32_t) GetLastError()); + cpuinfo_log_error( + "failed to query processor cores information: error %" PRIu32, (uint32_t)GetLastError()); goto cleanup; } uint32_t cores_count = 0; - /* Index (among all cores) of the the first core on the current package */ + /* Index (among all cores) of the the first core on the current package + */ uint32_t package_core_start = 0; uint32_t current_package_apic_id = 0; PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX cores_info_end = - (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX) ((uintptr_t) processor_infos + cores_info_size); - for (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX core_info = processor_infos; - core_info < cores_info_end; - core_info = (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX) ((uintptr_t) core_info + core_info->Size)) - { + (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX)((uintptr_t)processor_infos + cores_info_size); + for (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX core_info = processor_infos; core_info < cores_info_end; + core_info = (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX)((uintptr_t)core_info + core_info->Size)) { if (core_info->Relationship != RelationProcessorCore) { - cpuinfo_log_warning("unexpected processor info type (%"PRIu32") for processor core information", - (uint32_t) core_info->Relationship); + cpuinfo_log_warning( + "unexpected processor info type (%" PRIu32 ") for processor core information", + (uint32_t)core_info->Relationship); continue; } - /* We assume that cores and logical processors are reported in APIC order */ + /* We assume that cores and logical processors are reported in + * APIC order */ const uint32_t core_id = cores_count++; uint32_t smt_id = 0; /* Reconstruct core part of APIC ID */ const uint32_t core_apic_id = (core_id & core_bits_mask) << x86_processor.topology.core_bits_offset; - /* Iterate processor groups and set the core & SMT parts of APIC ID */ + /* Iterate processor groups and set the core & SMT parts of APIC + * ID */ for (uint32_t i = 0; i < core_info->Processor.GroupCount; i++) { const uint32_t group_id = core_info->Processor.GroupMask[i].Group; - /* Global index of the first logical processor belonging to this group */ + /* Global index of the first logical processor belonging + * to this group */ const uint32_t group_processors_start = processors_before_group[group_id]; - /* Bitmask representing processors in this group belonging to this package */ + /* Bitmask representing processors in this group + * belonging to this package + */ KAFFINITY group_processors_mask = core_info->Processor.GroupMask[i].Mask; while (group_processors_mask != 0) { const uint32_t group_processor_id = low_index_from_kaffinity(group_processors_mask); const uint32_t processor_id = group_processors_start + group_processor_id; - /* Check if this is the first core on a new package */ + /* Check if this is the first core on a new + * package */ if (processors[processor_id].apic_id != current_package_apic_id) { package_core_start = core_id; current_package_apic_id = processors[processor_id].apic_id; @@ -283,12 +295,17 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV processors[processor_id].apic_id |= ((smt_id & thread_bits_mask) << x86_processor.topology.thread_bits_offset) | ((package_core_id & core_bits_mask) << x86_processor.topology.core_bits_offset); - cpuinfo_log_debug("reconstructed APIC ID 0x%08"PRIx32" for processor %"PRIu32" in group %"PRIu32, - processors[processor_id].apic_id, group_processor_id, group_id); + cpuinfo_log_debug( + "reconstructed APIC ID 0x%08" PRIx32 " for processor %" PRIu32 + " in group %" PRIu32, + processors[processor_id].apic_id, + group_processor_id, + group_id); - /* Set SMT ID (assume logical processors within the core are reported in APIC order) */ + /* Set SMT ID (assume logical processors within + * the core are reported in APIC order) */ processors[processor_id].smt_id = smt_id++; - processors[processor_id].core = (const struct cpuinfo_core*) NULL + core_id; + processors[processor_id].core = (const struct cpuinfo_core*)NULL + core_id; /* Reset the lowest bit in affinity mask */ group_processors_mask &= (group_processors_mask - 1); @@ -298,22 +315,28 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV cores = HeapAlloc(heap, HEAP_ZERO_MEMORY, cores_count * sizeof(struct cpuinfo_core)); if (cores == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" cores", - cores_count * sizeof(struct cpuinfo_core), cores_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " cores", + cores_count * sizeof(struct cpuinfo_core), + cores_count); goto cleanup; } clusters = HeapAlloc(heap, HEAP_ZERO_MEMORY, packages_count * sizeof(struct cpuinfo_cluster)); if (clusters == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" core clusters", - packages_count * sizeof(struct cpuinfo_cluster), packages_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " core clusters", + packages_count * sizeof(struct cpuinfo_cluster), + packages_count); goto cleanup; } packages = HeapAlloc(heap, HEAP_ZERO_MEMORY, packages_count * sizeof(struct cpuinfo_package)); if (packages == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" physical packages", - packages_count * sizeof(struct cpuinfo_package), packages_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " physical packages", + packages_count * sizeof(struct cpuinfo_package), + packages_count); goto cleanup; } @@ -321,26 +344,29 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV const uint32_t processor_id = i - 1; struct cpuinfo_processor* processor = processors + processor_id; - /* Adjust core and package pointers for all logical processors */ - struct cpuinfo_core* core = - (struct cpuinfo_core*) ((uintptr_t) cores + (uintptr_t) processor->core); + /* Adjust core and package pointers for all logical processors + */ + struct cpuinfo_core* core = (struct cpuinfo_core*)((uintptr_t)cores + (uintptr_t)processor->core); processor->core = core; struct cpuinfo_cluster* cluster = - (struct cpuinfo_cluster*) ((uintptr_t) clusters + (uintptr_t) processor->cluster); + (struct cpuinfo_cluster*)((uintptr_t)clusters + (uintptr_t)processor->cluster); processor->cluster = cluster; struct cpuinfo_package* package = - (struct cpuinfo_package*) ((uintptr_t) packages + (uintptr_t) processor->package); + (struct cpuinfo_package*)((uintptr_t)packages + (uintptr_t)processor->package); processor->package = package; - /* This can be overwritten by lower-index processors on the same package */ + /* This can be overwritten by lower-index processors on the same + * package */ package->processor_start = processor_id; package->processor_count += 1; - /* This can be overwritten by lower-index processors on the same cluster */ + /* This can be overwritten by lower-index processors on the same + * cluster */ cluster->processor_start = processor_id; cluster->processor_count += 1; - /* This can be overwritten by lower-index processors on the same core*/ + /* This can be overwritten by lower-index processors on the same + * core*/ core->processor_start = processor_id; core->processor_count += 1; } @@ -350,18 +376,19 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV const uint32_t global_core_id = i - 1; struct cpuinfo_core* core = cores + global_core_id; const struct cpuinfo_processor* processor = processors + core->processor_start; - struct cpuinfo_package* package = (struct cpuinfo_package*) processor->package; - struct cpuinfo_cluster* cluster = (struct cpuinfo_cluster*) processor->cluster; + struct cpuinfo_package* package = (struct cpuinfo_package*)processor->package; + struct cpuinfo_cluster* cluster = (struct cpuinfo_cluster*)processor->cluster; core->cluster = cluster; core->package = package; - core->core_id = core_bits_mask & - (processor->apic_id >> x86_processor.topology.core_bits_offset); + core->core_id = core_bits_mask & (processor->apic_id >> x86_processor.topology.core_bits_offset); core->vendor = x86_processor.vendor; - core->uarch = x86_processor.uarch; - core->cpuid = x86_processor.cpuid; + core->uarch = x86_processor.uarch; + core->cpuid = x86_processor.cpuid; - /* This can be overwritten by lower-index cores on the same cluster/package */ + /* This can be overwritten by lower-index cores on the same + * cluster/package + */ cluster->core_start = global_core_id; cluster->core_count += 1; package->core_start = global_core_id; @@ -383,53 +410,64 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV /* Count caches */ uint32_t l1i_count, l1d_count, l2_count, l3_count, l4_count; - cpuinfo_x86_count_caches(processors_count, processors, &x86_processor, - &l1i_count, &l1d_count, &l2_count, &l3_count, &l4_count); + cpuinfo_x86_count_caches( + processors_count, processors, &x86_processor, &l1i_count, &l1d_count, &l2_count, &l3_count, &l4_count); /* Allocate cache descriptions */ if (l1i_count != 0) { l1i = HeapAlloc(heap, HEAP_ZERO_MEMORY, l1i_count * sizeof(struct cpuinfo_cache)); if (l1i == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1I caches", - l1i_count * sizeof(struct cpuinfo_cache), l1i_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1I caches", + l1i_count * sizeof(struct cpuinfo_cache), + l1i_count); goto cleanup; } } if (l1d_count != 0) { l1d = HeapAlloc(heap, HEAP_ZERO_MEMORY, l1d_count * sizeof(struct cpuinfo_cache)); if (l1d == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1D caches", - l1d_count * sizeof(struct cpuinfo_cache), l1d_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1D caches", + l1d_count * sizeof(struct cpuinfo_cache), + l1d_count); goto cleanup; } } if (l2_count != 0) { l2 = HeapAlloc(heap, HEAP_ZERO_MEMORY, l2_count * sizeof(struct cpuinfo_cache)); if (l2 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L2 caches", - l2_count * sizeof(struct cpuinfo_cache), l2_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L2 caches", + l2_count * sizeof(struct cpuinfo_cache), + l2_count); goto cleanup; } } if (l3_count != 0) { l3 = HeapAlloc(heap, HEAP_ZERO_MEMORY, l3_count * sizeof(struct cpuinfo_cache)); if (l3 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L3 caches", - l3_count * sizeof(struct cpuinfo_cache), l3_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L3 caches", + l3_count * sizeof(struct cpuinfo_cache), + l3_count); goto cleanup; } } if (l4_count != 0) { l4 = HeapAlloc(heap, HEAP_ZERO_MEMORY, l4_count * sizeof(struct cpuinfo_cache)); if (l4 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L4 caches", - l4_count * sizeof(struct cpuinfo_cache), l4_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L4 caches", + l4_count * sizeof(struct cpuinfo_cache), + l4_count); goto cleanup; } } /* Set cache information */ - uint32_t l1i_index = UINT32_MAX, l1d_index = UINT32_MAX, l2_index = UINT32_MAX, l3_index = UINT32_MAX, l4_index = UINT32_MAX; + uint32_t l1i_index = UINT32_MAX, l1d_index = UINT32_MAX, l2_index = UINT32_MAX, l3_index = UINT32_MAX, + l4_index = UINT32_MAX; uint32_t last_l1i_id = UINT32_MAX, last_l1d_id = UINT32_MAX; uint32_t last_l2_id = UINT32_MAX, last_l3_id = UINT32_MAX, last_l4_id = UINT32_MAX; for (uint32_t i = 0; i < processors_count; i++) { @@ -441,13 +479,13 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV if (l1i_id != last_l1i_id) { /* new cache */ last_l1i_id = l1i_id; - l1i[++l1i_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l1i.size, - .associativity = x86_processor.cache.l1i.associativity, - .sets = x86_processor.cache.l1i.sets, - .partitions = x86_processor.cache.l1i.partitions, - .line_size = x86_processor.cache.l1i.line_size, - .flags = x86_processor.cache.l1i.flags, + l1i[++l1i_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l1i.size, + .associativity = x86_processor.cache.l1i.associativity, + .sets = x86_processor.cache.l1i.sets, + .partitions = x86_processor.cache.l1i.partitions, + .line_size = x86_processor.cache.l1i.line_size, + .flags = x86_processor.cache.l1i.flags, .processor_start = i, .processor_count = 1, }; @@ -466,13 +504,13 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV if (l1d_id != last_l1d_id) { /* new cache */ last_l1d_id = l1d_id; - l1d[++l1d_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l1d.size, - .associativity = x86_processor.cache.l1d.associativity, - .sets = x86_processor.cache.l1d.sets, - .partitions = x86_processor.cache.l1d.partitions, - .line_size = x86_processor.cache.l1d.line_size, - .flags = x86_processor.cache.l1d.flags, + l1d[++l1d_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l1d.size, + .associativity = x86_processor.cache.l1d.associativity, + .sets = x86_processor.cache.l1d.sets, + .partitions = x86_processor.cache.l1d.partitions, + .line_size = x86_processor.cache.l1d.line_size, + .flags = x86_processor.cache.l1d.flags, .processor_start = i, .processor_count = 1, }; @@ -491,13 +529,13 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV if (l2_id != last_l2_id) { /* new cache */ last_l2_id = l2_id; - l2[++l2_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l2.size, - .associativity = x86_processor.cache.l2.associativity, - .sets = x86_processor.cache.l2.sets, - .partitions = x86_processor.cache.l2.partitions, - .line_size = x86_processor.cache.l2.line_size, - .flags = x86_processor.cache.l2.flags, + l2[++l2_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l2.size, + .associativity = x86_processor.cache.l2.associativity, + .sets = x86_processor.cache.l2.sets, + .partitions = x86_processor.cache.l2.partitions, + .line_size = x86_processor.cache.l2.line_size, + .flags = x86_processor.cache.l2.flags, .processor_start = i, .processor_count = 1, }; @@ -516,13 +554,13 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV if (l3_id != last_l3_id) { /* new cache */ last_l3_id = l3_id; - l3[++l3_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l3.size, - .associativity = x86_processor.cache.l3.associativity, - .sets = x86_processor.cache.l3.sets, - .partitions = x86_processor.cache.l3.partitions, - .line_size = x86_processor.cache.l3.line_size, - .flags = x86_processor.cache.l3.flags, + l3[++l3_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l3.size, + .associativity = x86_processor.cache.l3.associativity, + .sets = x86_processor.cache.l3.sets, + .partitions = x86_processor.cache.l3.partitions, + .line_size = x86_processor.cache.l3.line_size, + .flags = x86_processor.cache.l3.flags, .processor_start = i, .processor_count = 1, }; @@ -541,13 +579,13 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV if (l4_id != last_l4_id) { /* new cache */ last_l4_id = l4_id; - l4[++l4_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l4.size, - .associativity = x86_processor.cache.l4.associativity, - .sets = x86_processor.cache.l4.sets, - .partitions = x86_processor.cache.l4.partitions, - .line_size = x86_processor.cache.l4.line_size, - .flags = x86_processor.cache.l4.flags, + l4[++l4_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l4.size, + .associativity = x86_processor.cache.l4.associativity, + .sets = x86_processor.cache.l4.sets, + .partitions = x86_processor.cache.l4.partitions, + .line_size = x86_processor.cache.l4.line_size, + .flags = x86_processor.cache.l4.flags, .processor_start = i, .processor_count = 1, }; @@ -562,7 +600,6 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV } } - /* Commit changes */ cpuinfo_processors = processors; cpuinfo_cores = cores; @@ -570,9 +607,9 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV cpuinfo_packages = packages; cpuinfo_cache[cpuinfo_cache_level_1i] = l1i; cpuinfo_cache[cpuinfo_cache_level_1d] = l1d; - cpuinfo_cache[cpuinfo_cache_level_2] = l2; - cpuinfo_cache[cpuinfo_cache_level_3] = l3; - cpuinfo_cache[cpuinfo_cache_level_4] = l4; + cpuinfo_cache[cpuinfo_cache_level_2] = l2; + cpuinfo_cache[cpuinfo_cache_level_3] = l3; + cpuinfo_cache[cpuinfo_cache_level_4] = l4; cpuinfo_processors_count = processors_count; cpuinfo_cores_count = cores_count; @@ -580,12 +617,12 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV cpuinfo_packages_count = packages_count; cpuinfo_cache_count[cpuinfo_cache_level_1i] = l1i_count; cpuinfo_cache_count[cpuinfo_cache_level_1d] = l1d_count; - cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; - cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; - cpuinfo_cache_count[cpuinfo_cache_level_4] = l4_count; + cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; + cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; + cpuinfo_cache_count[cpuinfo_cache_level_4] = l4_count; cpuinfo_max_cache_size = cpuinfo_compute_max_cache_size(&processors[0]); - cpuinfo_global_uarch = (struct cpuinfo_uarch_info) { + cpuinfo_global_uarch = (struct cpuinfo_uarch_info){ .uarch = x86_processor.uarch, .cpuid = x86_processor.cpuid, .processor_count = processors_count,