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Remove 'elif' define from Pcsx2Defs and microvu_misc.h

This commit is contained in:
Lioncash 2014-07-30 23:44:04 -04:00
parent e726f82344
commit ac558afc8a
10 changed files with 190 additions and 68 deletions
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2
common/include/Pcsx2Defs.h
View File

@ -313,7 +313,5 @@ static const int __pagesize = PCSX2_PAGESIZE;
#define __ri __releaseinline
#define __fi __forceinline
#define __fc __fastcall
#define elif else if
#endif

30
pcsx2/Gif_Unit.cpp
View File

@ -27,9 +27,13 @@ Gif_Unit gifUnit;
bool Gif_HandlerAD(u8* pMem) {
u32 reg = pMem[8];
u32* data = (u32*)pMem;
if (reg == 0x50) vif1.BITBLTBUF._u64 = *(u64*)pMem;
elif (reg == 0x52) vif1.TRXREG._u64 = *(u64*)pMem;
elif (reg == 0x53) { // TRXDIR
if (reg == 0x50) {
vif1.BITBLTBUF._u64 = *(u64*)pMem;
}
else if (reg == 0x52) {
vif1.TRXREG._u64 = *(u64*)pMem;
}
else if (reg == 0x53) { // TRXDIR
if ((pMem[0] & 3) == 1) { // local -> host
u8 bpp = 32; // Onimusha does TRXDIR without BLTDIVIDE first, assume 32bit
switch(vif1.BITBLTBUF.SPSM & 7) {
@ -46,7 +50,7 @@ bool Gif_HandlerAD(u8* pMem) {
vif1.GSLastDownloadSize = vif1.TRXREG.RRW * vif1.TRXREG.RRH * bpp >> 7;
}
}
elif (reg == 0x60) { // SIGNAL
else if (reg == 0x60) { // SIGNAL
if (CSRreg.SIGNAL) { // Time to ignore all subsequent drawing operations.
GUNIT_WARN(Color_Orange, "GIF Handler - Stalling SIGNAL");
if(!gifUnit.gsSIGNAL.queued) {
@ -63,15 +67,15 @@ bool Gif_HandlerAD(u8* pMem) {
CSRreg.SIGNAL = true;
}
}
elif (reg == 0x61) { // FINISH
else if (reg == 0x61) { // FINISH
GUNIT_WARN("GIF Handler - FINISH");
CSRreg.FINISH = true;
}
elif (reg == 0x62) { // LABEL
else if (reg == 0x62) { // LABEL
GUNIT_WARN("GIF Handler - LABEL");
GSSIGLBLID.LBLID = (GSSIGLBLID.LBLID&~data[1])|(data[0]&data[1]);
}
elif (reg >= 0x63 && reg != 0x7f) {
else if (reg >= 0x63 && reg != 0x7f) {
//DevCon.Warning("GIF Handler - Write to unknown register! [reg=%x]", reg);
}
return false;
@ -81,12 +85,12 @@ bool Gif_HandlerAD(u8* pMem) {
bool Gif_HandlerAD_Debug(u8* pMem) {
u32 reg = pMem[8];
if (reg == 0x50) { Console.Error("GIF Handler Debug - BITBLTBUF"); return 1; }
elif (reg == 0x52) { Console.Error("GIF Handler Debug - TRXREG"); return 1; }
elif (reg == 0x53) { Console.Error("GIF Handler Debug - TRXDIR"); return 1; }
elif (reg == 0x60) { Console.Error("GIF Handler Debug - SIGNAL"); return 1; }
elif (reg == 0x61) { Console.Error("GIF Handler Debug - FINISH"); return 1; }
elif (reg == 0x62) { Console.Error("GIF Handler Debug - LABEL"); return 1; }
elif (reg >= 0x63 && reg != 0x7f) {
else if (reg == 0x52) { Console.Error("GIF Handler Debug - TRXREG"); return 1; }
else if (reg == 0x53) { Console.Error("GIF Handler Debug - TRXDIR"); return 1; }
else if (reg == 0x60) { Console.Error("GIF Handler Debug - SIGNAL"); return 1; }
else if (reg == 0x61) { Console.Error("GIF Handler Debug - FINISH"); return 1; }
else if (reg == 0x62) { Console.Error("GIF Handler Debug - LABEL"); return 1; }
else if (reg >= 0x63 && reg != 0x7f) {
DevCon.Warning("GIF Handler Debug - Write to unknown register! [reg=%x]", reg);
}
return 0;

30
pcsx2/Gif_Unit.h
View File

@ -588,11 +588,31 @@ struct Gif_Unit {
//DevCon.WriteLn("Adding GS Packet for path %d", stat.APATH);
AddCompletedGSPacket(gsPack, (GIF_PATH)(stat.APATH-1));
}
if (!gsSIGNAL.queued && !gifPath[0].isDone()) { stat.APATH = 1; stat.P1Q = 0; curPath = 0; }
elif (!gsSIGNAL.queued && !gifPath[1].isDone()) { stat.APATH = 2; stat.P2Q = 0; curPath = 1; }
elif (!gsSIGNAL.queued && !gifPath[2].isDone() && !Path3Masked())
{ stat.APATH = 3; stat.P3Q = 0; stat.IP3 = 0; curPath = 2; }
else { if(isResume || curPath == 0) { stat.APATH = 0; stat.OPH = 0; } break; }
if (!gsSIGNAL.queued && !gifPath[0].isDone()) {
stat.APATH = 1;
stat.P1Q = 0;
curPath = 0;
}
else if (!gsSIGNAL.queued && !gifPath[1].isDone()) {
stat.APATH = 2;
stat.P2Q = 0;
curPath = 1;
}
else if (!gsSIGNAL.queued && !gifPath[2].isDone() && !Path3Masked()) {
stat.APATH = 3;
stat.P3Q = 0;
stat.IP3 = 0;
curPath = 2;
}
else {
if(isResume || curPath == 0) {
stat.APATH = 0;
stat.OPH = 0;
}
break;
}
}
//Some loaders/Refresh Rate selectors and things dont issue "End of Packet" commands

18
pcsx2/x86/microVU_Alloc.inl
View File

@ -117,9 +117,12 @@ __fi void mVUallocCFLAGb(mV, const x32& reg, int fInstance)
__ri void mVUallocVIa(mV, const x32& GPRreg, int _reg_, bool signext = false)
{
if (!_reg_) xXOR (GPRreg, GPRreg);
elif(signext) xMOVSX(GPRreg, ptr16[&mVU.regs().VI[_reg_].SL]);
else xMOVZX(GPRreg, ptr16[&mVU.regs().VI[_reg_].UL]);
if (!_reg_)
xXOR(GPRreg, GPRreg);
else if (signext)
xMOVSX(GPRreg, ptr16[&mVU.regs().VI[_reg_].SL]);
else
xMOVZX(GPRreg, ptr16[&mVU.regs().VI[_reg_].UL]);
}
__ri void mVUallocVIb(mV, const x32& GPRreg, int _reg_)
@ -128,8 +131,13 @@ __ri void mVUallocVIb(mV, const x32& GPRreg, int _reg_)
xMOVZX(gprT3, ptr16[&mVU.regs().VI[_reg_].UL]);
xMOV (ptr32[&mVU.VIbackup], gprT3);
}
if (_reg_ == 0) { return; }
elif (_reg_ < 16) { xMOV(ptr16[&mVU.regs().VI[_reg_].UL], xRegister16(GPRreg.Id)); }
if (_reg_ == 0) {
return;
}
else if (_reg_ < 16) {
xMOV(ptr16[&mVU.regs().VI[_reg_].UL], xRegister16(GPRreg.Id));
}
}
//------------------------------------------------------------------

28
pcsx2/x86/microVU_Analyze.inl
View File

@ -47,10 +47,26 @@ __ri void analyzeReg2(mV, int xReg, microVFreg& vfWrite, bool isLowOp) {
// Read a VF reg (BC opcodes)
__ri void analyzeReg3(mV, int xReg, microVFreg& vfRead) {
if (xReg) {
if (_bc_x) { mVUstall = max(mVUstall, mVUregs.VF[xReg].x); vfRead.reg = xReg; vfRead.x = 1; }
elif (_bc_y) { mVUstall = max(mVUstall, mVUregs.VF[xReg].y); vfRead.reg = xReg; vfRead.y = 1; }
elif (_bc_z) { mVUstall = max(mVUstall, mVUregs.VF[xReg].z); vfRead.reg = xReg; vfRead.z = 1; }
else { mVUstall = max(mVUstall, mVUregs.VF[xReg].w); vfRead.reg = xReg; vfRead.w = 1; }
if (_bc_x) {
mVUstall = max(mVUstall, mVUregs.VF[xReg].x);
vfRead.reg = xReg;
vfRead.x = 1;
}
else if (_bc_y) {
mVUstall = max(mVUstall, mVUregs.VF[xReg].y);
vfRead.reg = xReg;
vfRead.y = 1;
}
else if (_bc_z) {
mVUstall = max(mVUstall, mVUregs.VF[xReg].z);
vfRead.reg = xReg;
vfRead.z = 1;
}
else {
mVUstall = max(mVUstall, mVUregs.VF[xReg].w);
vfRead.reg = xReg;
vfRead.w = 1;
}
}
}
@ -395,7 +411,9 @@ static void analyzeBranchVI(mV, int xReg, bool& infoVar) {
}
j = i;
}
elif (i == 0) break;
else if (i == 0) {
break;
}
cyc += mVUstall + 1;
incPC2(-2);
}

55
pcsx2/x86/microVU_Compile.inl
View File

@ -55,7 +55,10 @@ void mVUsetupRange(microVU& mVU, s32 pc, bool isStartPC) {
}
}
}
elif (mVUrange.end != -1) return; // Above case was true
else if (mVUrange.end != -1) {
// Above case was true
return;
}
mVUcheckIsSame(mVU);
@ -75,7 +78,7 @@ void mVUsetupRange(microVU& mVU, s32 pc, bool isStartPC) {
it[0].end = max(it[0].end, rEnd);
mergedRange = 1;
}
elif((it[0].end >= rStart) && (it[0].end <= rEnd)) {
else if ((it[0].end >= rStart) && (it[0].end <= rEnd)) {
it[0].start = min(it[0].start, rStart);
mergedRange = 1;
}
@ -148,9 +151,22 @@ void doSwapOp(mV) {
}
void mVUexecuteInstruction(mV) {
if (mVUlow.isNOP) { incPC(1); doUpperOp(mVU); flushRegs(mVU); doIbit(mVU); }
elif(!mVUinfo.swapOps) { incPC(1); doUpperOp(mVU); flushRegs(mVU); doLowerOp(mVU); }
else doSwapOp(mVU);
if (mVUlow.isNOP) {
incPC(1);
doUpperOp(mVU);
flushRegs(mVU);
doIbit(mVU);
}
else if (!mVUinfo.swapOps) {
incPC(1);
doUpperOp(mVU);
flushRegs(mVU);
doLowerOp(mVU);
}
else {
doSwapOp(mVU);
}
flushRegs(mVU);
}
@ -543,10 +559,31 @@ void* mVUcompile(microVU& mVU, u32 startPC, uptr pState) {
mVUinfo.readP = mVU.p;
mVUinfo.writeP = !mVU.p;
mVUcount++;
if (branch >= 2) { mVUinfo.isEOB = 1; if (branch == 3) { mVUinfo.isBdelay = 1; } branchWarning(mVU); break; }
elif (branch == 1) { branch = 2; }
if (mVUbranch) { mVUsetFlagInfo(mVU); eBitWarning(mVU); branch = 3; mVUbranch = 0; }
if (mVUinfo.isEOB) break;
if (branch >= 2) {
mVUinfo.isEOB = true;
if (branch == 3) {
mVUinfo.isBdelay = true;
}
branchWarning(mVU);
break;
}
else if (branch == 1) {
branch = 2;
}
if (mVUbranch) {
mVUsetFlagInfo(mVU);
eBitWarning(mVU);
branch = 3;
mVUbranch = 0;
}
if (mVUinfo.isEOB)
break;
incPC(1);
}

2
pcsx2/x86/microVU_Flags.inl
View File

@ -368,7 +368,7 @@ void mVUsetFlagInfo(mV) {
mVUregs.flagInfo |= 1;
}
}
elif(mVUbranch <= 8) { // Conditional Branch
else if (mVUbranch <= 8) { // Conditional Branch
incPC(-1); // Branch Taken
mVUflagPass (mVU, branchAddr);
checkFFblock(mVU, branchAddr, ffOpt);

81
pcsx2/x86/microVU_IR.h
View File

@ -265,9 +265,12 @@ public:
microMapXMM& mapX = xmmMap[xmm(i).Id];
if ((mapX.VFreg > 0) && mapX.xyzw) { // Reg was modified and not Temp or vf0
if (mapX.VFreg == 33) xMOVSS(ptr32[&getVI(REG_I)], xmm(i));
elif (mapX.VFreg == 32) mVUsaveReg(xmm(i), ptr[&regs().ACC], mapX.xyzw, 1);
else mVUsaveReg(xmm(i), ptr[&getVF(mapX.VFreg)], mapX.xyzw, 1);
if (mapX.VFreg == 33)
xMOVSS(ptr32[&getVI(REG_I)], xmm(i));
else if (mapX.VFreg == 32)
mVUsaveReg(xmm(i), ptr[&regs().ACC], mapX.xyzw, 1);
else
mVUsaveReg(xmm(i), ptr[&getVF(mapX.VFreg)], mapX.xyzw, 1);
}
}
}
@ -294,9 +297,13 @@ public:
microMapXMM& mapX = xmmMap[reg.Id];
if ((mapX.VFreg > 0) && mapX.xyzw) { // Reg was modified and not Temp or vf0
if (mapX.VFreg == 33) xMOVSS(ptr32[&getVI(REG_I)], reg);
elif (mapX.VFreg == 32) mVUsaveReg(reg, ptr[&regs().ACC], mapX.xyzw, 1);
else mVUsaveReg(reg, ptr[&getVF(mapX.VFreg)], mapX.xyzw, 1);
if (mapX.VFreg == 33)
xMOVSS(ptr32[&getVI(REG_I)], reg);
else if (mapX.VFreg == 32)
mVUsaveReg(reg, ptr[&regs().ACC], mapX.xyzw, 1);
else
mVUsaveReg(reg, ptr[&getVF(mapX.VFreg)], mapX.xyzw, 1);
if (invalidateRegs) {
for(int i = 0; i < xmmTotal; i++) {
microMapXMM& mapI = xmmMap[i];
@ -315,7 +322,9 @@ public:
}
clearReg(reg);
}
elif (mapX.xyzw) clearReg(reg); // Clear reg if modified and is VF0 or temp reg...
else if (mapX.xyzw) { // Clear reg if modified and is VF0 or temp reg...
clearReg(reg);
}
}
// Use this when done using the allocated register, it clears its "Needed" status.
@ -349,8 +358,10 @@ public:
else clearReg(i); // Clears when mergeRegs is 0 or 2
}
}
if (mergeRegs==2) clearReg(reg); // Clear Current Reg if Merged
elif (mergeRegs==1) writeBackReg(reg); // Write Back Partial Writes if couldn't merge
if (mergeRegs == 2) // Clear Current Reg if Merged
clearReg(reg);
else if (mergeRegs == 1) // Write Back Partial Writes if couldn't merge
writeBackReg(reg);
}
else clearReg(reg); // If Reg was temp or vf0, then invalidate itself
}
@ -380,17 +391,28 @@ public:
z = findFreeReg();
const xmm& xmmZ = xmm::GetInstance(z);
writeBackReg(xmmZ);
if (xyzw == 4) xPSHUF.D(xmmZ, xmmI, 1);
elif (xyzw == 2) xPSHUF.D(xmmZ, xmmI, 2);
elif (xyzw == 1) xPSHUF.D(xmmZ, xmmI, 3);
elif (z != i) xMOVAPS (xmmZ, xmmI);
if (xyzw == 4)
xPSHUF.D(xmmZ, xmmI, 1);
else if (xyzw == 2)
xPSHUF.D(xmmZ, xmmI, 2);
else if (xyzw == 1)
xPSHUF.D(xmmZ, xmmI, 3);
else if (z != i)
xMOVAPS (xmmZ, xmmI);
mapI.count = counter; // Reg i was used, so update counter
}
else { // Don't clone reg, but shuffle to adjust for SS ops
if ((vfLoadReg!=vfWriteReg)||(xyzw!=0xf)) writeBackReg(xmmI);
if (xyzw == 4) xPSHUF.D(xmmI, xmmI, 1);
elif (xyzw == 2) xPSHUF.D(xmmI, xmmI, 2);
elif (xyzw == 1) xPSHUF.D(xmmI, xmmI, 3);
if ((vfLoadReg!=vfWriteReg)||(xyzw!=0xf))
writeBackReg(xmmI);
if (xyzw == 4)
xPSHUF.D(xmmI, xmmI, 1);
else if (xyzw == 2)
xPSHUF.D(xmmI, xmmI, 2);
else if (xyzw == 1)
xPSHUF.D(xmmI, xmmI, 3);
}
xmmMap[z].VFreg = vfWriteReg;
xmmMap[z].xyzw = xyzw;
@ -406,21 +428,30 @@ public:
writeBackReg(xmmX);
if (vfWriteReg >= 0) { // Reg Will Be Modified (allow partial reg loading)
if ((vfLoadReg == 0) && !(xyzw & 1)) xPXOR(xmmX, xmmX);
elif (vfLoadReg == 33) loadIreg (xmmX, xyzw);
elif (vfLoadReg == 32) mVUloadReg(xmmX, ptr[&regs().ACC], xyzw);
elif (vfLoadReg >= 0) mVUloadReg(xmmX, ptr[&getVF(vfLoadReg)], xyzw);
if ((vfLoadReg == 0) && !(xyzw & 1))
xPXOR(xmmX, xmmX);
else if (vfLoadReg == 33)
loadIreg (xmmX, xyzw);
else if (vfLoadReg == 32)
mVUloadReg(xmmX, ptr[&regs().ACC], xyzw);
else if (vfLoadReg >= 0)
mVUloadReg(xmmX, ptr[&getVF(vfLoadReg)], xyzw);
xmmMap[x].VFreg = vfWriteReg;
xmmMap[x].xyzw = xyzw;
}
else { // Reg Will Not Be Modified (always load full reg for caching)
if (vfLoadReg == 33) loadIreg(xmmX, 0xf);
elif (vfLoadReg == 32) xMOVAPS (xmmX, ptr128[&regs().ACC]);
elif (vfLoadReg >= 0) xMOVAPS (xmmX, ptr128[&getVF(vfLoadReg)]);
if (vfLoadReg == 33)
loadIreg(xmmX, 0xf);
else if (vfLoadReg == 32)
xMOVAPS (xmmX, ptr128[&regs().ACC]);
else if (vfLoadReg >= 0)
xMOVAPS (xmmX, ptr128[&getVF(vfLoadReg)]);
xmmMap[x].VFreg = vfLoadReg;
xmmMap[x].xyzw = 0;
}
xmmMap[x].count = counter;
xmmMap[x].count = counter;
xmmMap[x].isNeeded = 1;
return xmmX;
}

11
pcsx2/x86/microVU_Lower.inl
View File

@ -1214,8 +1214,15 @@ static __fi void mVU_XGKICK_DELAY(mV, bool memVI) {
mVUop(mVU_XGKICK) {
pass1 { mVUanalyzeXGkick(mVU, _Is_, mVU_XGKICK_CYCLES); }
pass2 {
if (!mVU_XGKICK_CYCLES) { mVU_XGKICK_DELAY(mVU, 0); return; }
elif (mVUinfo.doXGKICK) { mVU_XGKICK_DELAY(mVU, 1); mVUinfo.doXGKICK = 0; }
if (!mVU_XGKICK_CYCLES) {
mVU_XGKICK_DELAY(mVU, false);
return;
}
else if (mVUinfo.doXGKICK) {
mVU_XGKICK_DELAY(mVU, true);
mVUinfo.doXGKICK = false;
}
mVUallocVIa(mVU, gprT1, _Is_);
xMOV(ptr32[&mVU.VIxgkick], gprT1);
mVU.profiler.EmitOp(opXGKICK);

1
pcsx2/x86/microVU_Misc.h
View File

@ -233,7 +233,6 @@ typedef u32 (__fastcall *mVUCall)(void*, void*);
#define aWrap(x, m) ((x > m) ? 0 : x)
#define shuffleSS(x) ((x==1)?(0x27):((x==2)?(0xc6):((x==4)?(0xe1):(0xe4))))
#define clampE CHECK_VU_EXTRA_OVERFLOW
#define elif else if
#define varPrint(x) DevCon.WriteLn(#x " = %d", (int)x)
#define blockCreate(addr) { \