From abf620141b4f955fb4eab94324293d7921f2576a Mon Sep 17 00:00:00 2001
From: refraction <refraction@96395faa-99c1-11dd-bbfe-3dabce05a288>
Date: Fri, 21 Jan 2011 16:24:54 +0000
Subject: [PATCH] Added some extra "how much in VIF fifo" checks, removed a
 silly one, fixes Gungrave

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@4241 96395faa-99c1-11dd-bbfe-3dabce05a288
---
 pcsx2/Vif0_Dma.cpp   | 2 ++
 pcsx2/Vif1_Dma.cpp   | 3 +++
 pcsx2/Vif1_MFIFO.cpp | 7 ++++++-
 3 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/pcsx2/Vif0_Dma.cpp b/pcsx2/Vif0_Dma.cpp
index 0a83c2ff56..543a319a5a 100644
--- a/pcsx2/Vif0_Dma.cpp
+++ b/pcsx2/Vif0_Dma.cpp
@@ -178,6 +178,7 @@ __fi void vif0Interrupt()
 
 			// One game doesn't like vif stalling at end, can't remember what. Spiderman isn't keen on it tho
 			//vif0ch.chcr.STR = false;
+			vif0Regs.stat.FQC = min((u16)0x8, vif0ch.qwc);
 			if(vif0ch.qwc > 0 || !vif0.done)	
 			{
 				VIF_LOG("VIF0 Stalled");
@@ -231,6 +232,7 @@ __fi void vif0Interrupt()
 #endif
 
 	vif0ch.chcr.STR = false;
+	vif0Regs.stat.FQC = min((u16)0x8, vif0ch.qwc);
 	g_vifCycles = 0;
 	hwDmacIrq(DMAC_VIF0);
 	vif0Regs.stat.FQC = 0;
diff --git a/pcsx2/Vif1_Dma.cpp b/pcsx2/Vif1_Dma.cpp
index e79214225e..a20f5bd009 100644
--- a/pcsx2/Vif1_Dma.cpp
+++ b/pcsx2/Vif1_Dma.cpp
@@ -385,6 +385,7 @@ __fi void vif1Interrupt()
 
 			//NFSHPS stalls when the whole packet has gone across (it stalls in the last 32bit cmd)
 			//In this case VIF will end
+			vif1Regs.stat.FQC = min((u16)0x10, vif1ch.qwc);
 			if(vif1ch.qwc > 0 || !vif1.done)	
 			{
 				VIF_LOG("VIF1 Stalled");
@@ -447,6 +448,8 @@ __fi void vif1Interrupt()
 		gifRegs.stat.OPH = false;
 	}
 
+	if (vif1ch.chcr.DIR) vif1Regs.stat.FQC = min(vif1ch.qwc, (u16)16);
+
 	vif1ch.chcr.STR = false;
 	vif1.vifstalled = false;
 	g_vifCycles = 0;
diff --git a/pcsx2/Vif1_MFIFO.cpp b/pcsx2/Vif1_MFIFO.cpp
index 6bd02bf187..2d9254c329 100644
--- a/pcsx2/Vif1_MFIFO.cpp
+++ b/pcsx2/Vif1_MFIFO.cpp
@@ -169,7 +169,8 @@ void mfifoVIF1transfer(int qwc)
 				CPU_INT(DMAC_MFIFO_VIF, 4);
 			}
 
-			vif1Regs.stat.FQC = 0x10; // FQC=16
+			//Apparently this is bad, i guess so, the data is going to memory rather than the FIFO
+			//vif1Regs.stat.FQC = 0x10; // FQC=16
 		}
 		vif1.inprogress &= ~0x10;
 
@@ -292,6 +293,7 @@ void vifMFIFOInterrupt()
 		{
 			/*vif1Regs.stat.FQC = 0; // FQC=0
 			vif1ch.chcr.STR = false;*/
+			vif1Regs.stat.FQC = min((u16)0x10, vif1ch.qwc);
 			if((vif1ch.qwc > 0 || !vif1.done) && !(vif1.inprogress & 0x10))
 			{
 				VIF_LOG("VIF1 MFIFO Stalled");
@@ -330,11 +332,13 @@ void vifMFIFOInterrupt()
 				}
 				
                 mfifoVIF1transfer(0);
+				vif1Regs.stat.FQC = min((u16)0x10, vif1ch.qwc);
 				
 			case 1: //Transfer data
 				mfifo_VIF1chain();
 				//Sanity check! making sure we always have non-zero values
 				CPU_INT(DMAC_MFIFO_VIF, (g_vifCycles == 0 ? 4 : g_vifCycles) );	
+				vif1Regs.stat.FQC = min((u16)0x10, vif1ch.qwc);
 				return;
 		}
 		return;
@@ -343,6 +347,7 @@ void vifMFIFOInterrupt()
 	vif1.vifstalled = false;
 	vif1.done = 1;
 	g_vifCycles = 0;
+	vif1Regs.stat.FQC = min((u16)0x10, vif1ch.qwc);
 	vif1ch.chcr.STR = false;
 	hwDmacIrq(DMAC_VIF1);
 	VIF_LOG("vif mfifo dma end");