MicroVU: Cleanup stale comments and code

This commit is contained in:
Ty Lamontagne 2021-09-10 19:41:36 -04:00 committed by refractionpcsx2
parent a8a50641f6
commit ab64023e56
7 changed files with 0 additions and 88 deletions

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@ -104,8 +104,6 @@ void mVUreset(microVU& mVU, bool resetReserve)
mVUemitSearch(); mVUemitSearch();
mVU.regs().nextBlockCycles = 0; mVU.regs().nextBlockCycles = 0;
// Clear All Program Data
//memset(&mVU.prog, 0, sizeof(mVU.prog));
memset(&mVU.prog.lpState, 0, sizeof(mVU.prog.lpState)); memset(&mVU.prog.lpState, 0, sizeof(mVU.prog.lpState));
mVU.profiler.Reset(mVU.index); mVU.profiler.Reset(mVU.index);
@ -121,7 +119,6 @@ void mVUreset(microVU& mVU, bool resetReserve)
mVU.prog.x86start = z; mVU.prog.x86start = z;
mVU.prog.x86ptr = z; mVU.prog.x86ptr = z;
mVU.prog.x86end = z + ((mVU.cacheSize - mVUcacheSafeZone) * _1mb); mVU.prog.x86end = z + ((mVU.cacheSize - mVUcacheSafeZone) * _1mb);
//memset(mVU.prog.x86start, 0xcc, mVU.cacheSize*_1mb);
for (u32 i = 0; i < (mVU.progSize / 2); i++) for (u32 i = 0; i < (mVU.progSize / 2); i++)
{ {

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@ -159,13 +159,11 @@ __ri void mVUallocVIb(mV, const x32& GPRreg, int _reg_)
__fi void getPreg(mV, const xmm& reg) __fi void getPreg(mV, const xmm& reg)
{ {
mVUunpack_xyzw(reg, xmmPQ, (2 + mVUinfo.readP)); mVUunpack_xyzw(reg, xmmPQ, (2 + mVUinfo.readP));
/*if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT1, 15);*/
} }
__fi void getQreg(const xmm& reg, int qInstance) __fi void getQreg(const xmm& reg, int qInstance)
{ {
mVUunpack_xyzw(reg, xmmPQ, qInstance); mVUunpack_xyzw(reg, xmmPQ, qInstance);
/*if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, 15);*/
} }
__ri void writeQreg(const xmm& reg, int qInstance) __ri void writeQreg(const xmm& reg, int qInstance)

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@ -574,59 +574,6 @@ static void analyzeBranchVI(mV, int xReg, bool& infoVar)
} }
} }
/*
// Dead Code... the old version of analyzeBranchVI()
__fi void analyzeBranchVI(mV, int xReg, bool& infoVar)
{
if (!xReg)
return;
int i;
int iEnd = std::min(5, mVUcount + 1);
int bPC = iPC;
incPC2(-2);
for (i = 0; i < iEnd; i++)
{
if ((i == mVUcount) && (i < 5))
{
if (mVUpBlock->pState.viBackUp == xReg)
{
infoVar = 1;
i++;
}
break;
}
if ((mVUlow.VI_write.reg == xReg) && mVUlow.VI_write.used)
{
if (mVUlow.readFlags || i == 5) break;
if (i == 0)
{
incPC2(-2);
continue;
}
if (((mVUlow.VI_read[0].reg == xReg) && (mVUlow.VI_read[0].used))
|| ((mVUlow.VI_read[1].reg == xReg) && (mVUlow.VI_read[1].used)))
{
incPC2(-2);
continue;
}
}
break;
}
if (i)
{
if (!infoVar)
{
incPC2(2);
mVUlow.backupVI = 1;
infoVar = 1;
}
iPC = bPC;
DevCon.WriteLn( Color_Green, "microVU%d: Branch VI-Delay (%d) [%04x]", getIndex, i, xPC);
}
else iPC = bPC;
}
*/
// Branch in Branch Delay-Slots // Branch in Branch Delay-Slots
__ri int mVUbranchCheck(mV) __ri int mVUbranchCheck(mV)
{ {
@ -715,7 +662,6 @@ __ri void mVUanalyzeJump(mV, int Is, int It, bool isJALR)
{ {
mVUlow.constJump.isValid = 1; mVUlow.constJump.isValid = 1;
mVUlow.constJump.regValue = mVUconstReg[Is].regValue; mVUlow.constJump.regValue = mVUconstReg[Is].regValue;
//DevCon.Status("microVU%d: Constant JR/JALR Address Optimization", mVU.index);
} }
analyzeVIreg1(mVU, Is, mVUlow.VI_read[0]); analyzeVIreg1(mVU, Is, mVUlow.VI_read[0]);
if (isJALR) if (isJALR)

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@ -45,8 +45,6 @@ void mVUDTendProgram(mV, microFlagCycles* mFC, int isEbit)
if (isEbit) if (isEbit)
{ {
/*memzero(mVUinfo);
memzero(mVUregsTemp);*/
mVUincCycles(mVU, 100); // Ensures Valid P/Q instances (And sets all cycle data to 0) mVUincCycles(mVU, 100); // Ensures Valid P/Q instances (And sets all cycle data to 0)
mVUcycles -= 100; mVUcycles -= 100;
qInst = mVU.q; qInst = mVU.q;

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@ -107,9 +107,6 @@ void mVUdispatcherCD(mV)
mVU.exitFunctXG = x86Ptr; mVU.exitFunctXG = x86Ptr;
//xPOP(gprT1); // Pop return address
//xMOV(ptr32[&mVU.resumePtrXG], gprT1);
// Backup Status Flag (other regs were backed up on xgkick) // Backup Status Flag (other regs were backed up on xgkick)
xMOV(ptr32[&mVU.regs().micro_statusflags[0]], gprF0); xMOV(ptr32[&mVU.regs().micro_statusflags[0]], gprF0);
xMOV(ptr32[&mVU.regs().micro_statusflags[1]], gprF1); xMOV(ptr32[&mVU.regs().micro_statusflags[1]], gprF1);
@ -155,9 +152,6 @@ _mVUt void* __fastcall mVUexecute(u32 startPC, u32 cycles)
_mVUt void mVUcleanUp() _mVUt void mVUcleanUp()
{ {
microVU& mVU = mVUx; microVU& mVU = mVUx;
//mVUprint("microVU: Program exited successfully!");
//mVUprint("microVU: VF0 = {%x,%x,%x,%x}", mVU.regs().VF[0].UL[0], mVU.regs().VF[0].UL[1], mVU.regs().VF[0].UL[2], mVU.regs().VF[0].UL[3]);
//mVUprint("microVU: VI0 = %x", mVU.regs().VI[0].UL);
mVU.prog.x86ptr = x86Ptr; mVU.prog.x86ptr = x86Ptr;
@ -187,14 +181,6 @@ _mVUt void mVUcleanUp()
} }
} }
mVU.profiler.Print(); mVU.profiler.Print();
//static int ax = 0; ax++;
//if (!(ax % 100000)) {
// for (u32 i = 0; i < (mVU.progSize / 2); i++) {
// if (mVUcurProg.block[i]) {
// mVUcurProg.block[i]->printInfo(i*8);
// }
// }
//}
} }
//------------------------------------------------------------------ //------------------------------------------------------------------

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@ -170,12 +170,10 @@ __fi void mVUsetFlags(mV, microFlagCycles& mFC)
if (!(mVUpBlock->pState.needExactMatch & 2)) if (!(mVUpBlock->pState.needExactMatch & 2))
{ {
//xM = (mVUpBlock->pState.flagInfo >> 4) & 3;
mFC.xMac[0] = -1; mFC.xMac[0] = -1;
mFC.xMac[1] = -1; mFC.xMac[1] = -1;
mFC.xMac[2] = -1; mFC.xMac[2] = -1;
mFC.xMac[3] = -1; mFC.xMac[3] = -1;
//mFC.xMac[(xM-1)&3] = 0;
} }
if (!(mVUpBlock->pState.needExactMatch & 4)) if (!(mVUpBlock->pState.needExactMatch & 4))
@ -409,8 +407,6 @@ void _mVUflagPass(mV, u32 startPC, u32 sCount, u32 found, std::vector<u32>& v)
incPC(1); incPC(1);
} }
// if (mVUbranch&&(branch>=3)&&(branch<=5)) { DevCon.Error("Double Branch [%x]", xPC); mVUregs.needExactMatch |= 7; break; }
if (branch >= 2) if (branch >= 2)
{ {
shortBranch(); shortBranch();

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@ -52,15 +52,6 @@ void mVUloadIreg(const xmm& reg, int xyzw, VURegs* vuRegs)
// Modifies the Source Reg! // Modifies the Source Reg!
void mVUsaveReg(const xmm& reg, xAddressVoid ptr, int xyzw, bool modXYZW) void mVUsaveReg(const xmm& reg, xAddressVoid ptr, int xyzw, bool modXYZW)
{ {
/*xMOVAPS(xmmT2, ptr128[ptr]);
if (modXYZW && (xyzw == 8 || xyzw == 4 || xyzw == 2 || xyzw == 1)) {
mVUunpack_xyzw(reg, reg, 0);
}
mVUmergeRegs(xmmT2, reg, xyzw);
xMOVAPS(ptr128[ptr], xmmT2);
return;*/
switch (xyzw) switch (xyzw)
{ {
case 5: // YW case 5: // YW