mirror of https://github.com/PCSX2/pcsx2.git
MicroVU: Cleanup stale comments and code
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a8a50641f6
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ab64023e56
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@ -104,8 +104,6 @@ void mVUreset(microVU& mVU, bool resetReserve)
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mVUemitSearch();
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mVUemitSearch();
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mVU.regs().nextBlockCycles = 0;
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mVU.regs().nextBlockCycles = 0;
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// Clear All Program Data
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//memset(&mVU.prog, 0, sizeof(mVU.prog));
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memset(&mVU.prog.lpState, 0, sizeof(mVU.prog.lpState));
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memset(&mVU.prog.lpState, 0, sizeof(mVU.prog.lpState));
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mVU.profiler.Reset(mVU.index);
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mVU.profiler.Reset(mVU.index);
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@ -121,7 +119,6 @@ void mVUreset(microVU& mVU, bool resetReserve)
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mVU.prog.x86start = z;
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mVU.prog.x86start = z;
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mVU.prog.x86ptr = z;
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mVU.prog.x86ptr = z;
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mVU.prog.x86end = z + ((mVU.cacheSize - mVUcacheSafeZone) * _1mb);
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mVU.prog.x86end = z + ((mVU.cacheSize - mVUcacheSafeZone) * _1mb);
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//memset(mVU.prog.x86start, 0xcc, mVU.cacheSize*_1mb);
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for (u32 i = 0; i < (mVU.progSize / 2); i++)
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for (u32 i = 0; i < (mVU.progSize / 2); i++)
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{
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{
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@ -159,13 +159,11 @@ __ri void mVUallocVIb(mV, const x32& GPRreg, int _reg_)
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__fi void getPreg(mV, const xmm& reg)
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__fi void getPreg(mV, const xmm& reg)
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{
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{
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mVUunpack_xyzw(reg, xmmPQ, (2 + mVUinfo.readP));
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mVUunpack_xyzw(reg, xmmPQ, (2 + mVUinfo.readP));
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/*if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT1, 15);*/
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}
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}
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__fi void getQreg(const xmm& reg, int qInstance)
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__fi void getQreg(const xmm& reg, int qInstance)
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{
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{
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mVUunpack_xyzw(reg, xmmPQ, qInstance);
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mVUunpack_xyzw(reg, xmmPQ, qInstance);
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/*if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, 15);*/
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}
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}
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__ri void writeQreg(const xmm& reg, int qInstance)
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__ri void writeQreg(const xmm& reg, int qInstance)
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@ -574,59 +574,6 @@ static void analyzeBranchVI(mV, int xReg, bool& infoVar)
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}
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}
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}
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}
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/*
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// Dead Code... the old version of analyzeBranchVI()
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__fi void analyzeBranchVI(mV, int xReg, bool& infoVar)
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{
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if (!xReg)
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return;
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int i;
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int iEnd = std::min(5, mVUcount + 1);
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int bPC = iPC;
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incPC2(-2);
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for (i = 0; i < iEnd; i++)
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{
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if ((i == mVUcount) && (i < 5))
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{
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if (mVUpBlock->pState.viBackUp == xReg)
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{
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infoVar = 1;
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i++;
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}
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break;
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}
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if ((mVUlow.VI_write.reg == xReg) && mVUlow.VI_write.used)
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{
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if (mVUlow.readFlags || i == 5) break;
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if (i == 0)
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{
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incPC2(-2);
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continue;
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}
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if (((mVUlow.VI_read[0].reg == xReg) && (mVUlow.VI_read[0].used))
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|| ((mVUlow.VI_read[1].reg == xReg) && (mVUlow.VI_read[1].used)))
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{
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incPC2(-2);
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continue;
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}
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}
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break;
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}
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if (i)
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{
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if (!infoVar)
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{
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incPC2(2);
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mVUlow.backupVI = 1;
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infoVar = 1;
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}
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iPC = bPC;
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DevCon.WriteLn( Color_Green, "microVU%d: Branch VI-Delay (%d) [%04x]", getIndex, i, xPC);
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}
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else iPC = bPC;
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}
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*/
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// Branch in Branch Delay-Slots
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// Branch in Branch Delay-Slots
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__ri int mVUbranchCheck(mV)
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__ri int mVUbranchCheck(mV)
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{
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{
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@ -715,7 +662,6 @@ __ri void mVUanalyzeJump(mV, int Is, int It, bool isJALR)
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{
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{
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mVUlow.constJump.isValid = 1;
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mVUlow.constJump.isValid = 1;
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mVUlow.constJump.regValue = mVUconstReg[Is].regValue;
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mVUlow.constJump.regValue = mVUconstReg[Is].regValue;
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//DevCon.Status("microVU%d: Constant JR/JALR Address Optimization", mVU.index);
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}
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}
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analyzeVIreg1(mVU, Is, mVUlow.VI_read[0]);
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analyzeVIreg1(mVU, Is, mVUlow.VI_read[0]);
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if (isJALR)
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if (isJALR)
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@ -45,8 +45,6 @@ void mVUDTendProgram(mV, microFlagCycles* mFC, int isEbit)
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if (isEbit)
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if (isEbit)
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{
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{
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/*memzero(mVUinfo);
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memzero(mVUregsTemp);*/
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mVUincCycles(mVU, 100); // Ensures Valid P/Q instances (And sets all cycle data to 0)
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mVUincCycles(mVU, 100); // Ensures Valid P/Q instances (And sets all cycle data to 0)
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mVUcycles -= 100;
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mVUcycles -= 100;
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qInst = mVU.q;
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qInst = mVU.q;
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@ -107,9 +107,6 @@ void mVUdispatcherCD(mV)
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mVU.exitFunctXG = x86Ptr;
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mVU.exitFunctXG = x86Ptr;
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//xPOP(gprT1); // Pop return address
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//xMOV(ptr32[&mVU.resumePtrXG], gprT1);
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// Backup Status Flag (other regs were backed up on xgkick)
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// Backup Status Flag (other regs were backed up on xgkick)
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xMOV(ptr32[&mVU.regs().micro_statusflags[0]], gprF0);
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xMOV(ptr32[&mVU.regs().micro_statusflags[0]], gprF0);
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xMOV(ptr32[&mVU.regs().micro_statusflags[1]], gprF1);
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xMOV(ptr32[&mVU.regs().micro_statusflags[1]], gprF1);
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@ -155,9 +152,6 @@ _mVUt void* __fastcall mVUexecute(u32 startPC, u32 cycles)
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_mVUt void mVUcleanUp()
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_mVUt void mVUcleanUp()
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{
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{
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microVU& mVU = mVUx;
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microVU& mVU = mVUx;
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//mVUprint("microVU: Program exited successfully!");
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//mVUprint("microVU: VF0 = {%x,%x,%x,%x}", mVU.regs().VF[0].UL[0], mVU.regs().VF[0].UL[1], mVU.regs().VF[0].UL[2], mVU.regs().VF[0].UL[3]);
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//mVUprint("microVU: VI0 = %x", mVU.regs().VI[0].UL);
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mVU.prog.x86ptr = x86Ptr;
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mVU.prog.x86ptr = x86Ptr;
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@ -187,14 +181,6 @@ _mVUt void mVUcleanUp()
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}
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}
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}
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}
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mVU.profiler.Print();
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mVU.profiler.Print();
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//static int ax = 0; ax++;
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//if (!(ax % 100000)) {
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// for (u32 i = 0; i < (mVU.progSize / 2); i++) {
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// if (mVUcurProg.block[i]) {
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// mVUcurProg.block[i]->printInfo(i*8);
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// }
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// }
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//}
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}
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}
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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@ -170,12 +170,10 @@ __fi void mVUsetFlags(mV, microFlagCycles& mFC)
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if (!(mVUpBlock->pState.needExactMatch & 2))
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if (!(mVUpBlock->pState.needExactMatch & 2))
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{
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{
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//xM = (mVUpBlock->pState.flagInfo >> 4) & 3;
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mFC.xMac[0] = -1;
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mFC.xMac[0] = -1;
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mFC.xMac[1] = -1;
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mFC.xMac[1] = -1;
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mFC.xMac[2] = -1;
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mFC.xMac[2] = -1;
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mFC.xMac[3] = -1;
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mFC.xMac[3] = -1;
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//mFC.xMac[(xM-1)&3] = 0;
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}
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}
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if (!(mVUpBlock->pState.needExactMatch & 4))
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if (!(mVUpBlock->pState.needExactMatch & 4))
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@ -409,8 +407,6 @@ void _mVUflagPass(mV, u32 startPC, u32 sCount, u32 found, std::vector<u32>& v)
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incPC(1);
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incPC(1);
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}
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}
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// if (mVUbranch&&(branch>=3)&&(branch<=5)) { DevCon.Error("Double Branch [%x]", xPC); mVUregs.needExactMatch |= 7; break; }
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if (branch >= 2)
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if (branch >= 2)
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{
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{
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shortBranch();
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shortBranch();
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@ -52,15 +52,6 @@ void mVUloadIreg(const xmm& reg, int xyzw, VURegs* vuRegs)
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// Modifies the Source Reg!
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// Modifies the Source Reg!
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void mVUsaveReg(const xmm& reg, xAddressVoid ptr, int xyzw, bool modXYZW)
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void mVUsaveReg(const xmm& reg, xAddressVoid ptr, int xyzw, bool modXYZW)
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{
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{
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/*xMOVAPS(xmmT2, ptr128[ptr]);
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if (modXYZW && (xyzw == 8 || xyzw == 4 || xyzw == 2 || xyzw == 1)) {
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mVUunpack_xyzw(reg, reg, 0);
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}
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mVUmergeRegs(xmmT2, reg, xyzw);
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xMOVAPS(ptr128[ptr], xmmT2);
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return;*/
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switch (xyzw)
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switch (xyzw)
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{
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{
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case 5: // YW
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case 5: // YW
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