PCSX2-GS: Use interrupt mask register bitfields

Previously, the code used a lot of "bitwise AND" to get specific bitfields of the interrupt mask control register, which makes the code look a bit hacky, also it's even more hard for normal people to calculate the value when hexadecimal values are used for the bitwise operations where the register is totally binary. Instead of dealing with all those mess, let's just get the bitfield values from the already implemented nice union of the IMR register. FWIW it also makes the code more readable.
This commit is contained in:
Akash 2016-12-01 16:31:48 +05:30
parent f41bb8db5e
commit a9b63a2106
5 changed files with 17 additions and 22 deletions

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@ -450,11 +450,9 @@ static __fi void VSyncStart(u32 sCycle)
if (!CSRreg.VSINT) if (!CSRreg.VSINT)
{ {
CSRreg.VSINT = true; CSRreg.VSINT = true;
if (!(GSIMR&0x800)) if (!GSIMR.VSMSK)
{
gsIrq(); gsIrq();
} }
}
hwIntcIrq(INTC_VBLANK_S); hwIntcIrq(INTC_VBLANK_S);
psxVBlankStart(); psxVBlankStart();
@ -532,11 +530,9 @@ __fi void rcntUpdate_hScanline()
if (!CSRreg.HSINT) if (!CSRreg.HSINT)
{ {
CSRreg.HSINT = true; CSRreg.HSINT = true;
if (!(GSIMR&0x400)) if (!GSIMR.HSMSK)
{
gsIrq(); gsIrq();
} }
}
if (gates) rcntEndGate(false, hsyncCounter.sCycle); if (gates) rcntEndGate(false, hsyncCounter.sCycle);
if (psxhblankgate) psxCheckEndGate16(0); if (psxhblankgate) psxCheckEndGate16(0);

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@ -55,7 +55,7 @@ void gsReset()
memzero(g_RealGSMem); memzero(g_RealGSMem);
CSRreg.Reset(); CSRreg.Reset();
GSIMR = 0x7f00; GSIMR.reset();
} }
static __fi void gsCSRwrite( const tGS_CSR& csr ) static __fi void gsCSRwrite( const tGS_CSR& csr )
@ -68,7 +68,7 @@ static __fi void gsCSRwrite( const tGS_CSR& csr )
GetMTGS().SendSimplePacket(GS_RINGTYPE_RESET, 0, 0, 0); GetMTGS().SendSimplePacket(GS_RINGTYPE_RESET, 0, 0, 0);
CSRreg.Reset(); CSRreg.Reset();
GSIMR = 0x7F00; //This is bits 14-8 thats all that should be 1 GSIMR.reset();
} }
if(csr.FLUSH) if(csr.FLUSH)
@ -87,7 +87,7 @@ static __fi void gsCSRwrite( const tGS_CSR& csr )
GSSIGLBLID.SIGID = (GSSIGLBLID.SIGID & ~gifUnit.gsSIGNAL.data[1]) GSSIGLBLID.SIGID = (GSSIGLBLID.SIGID & ~gifUnit.gsSIGNAL.data[1])
| (gifUnit.gsSIGNAL.data[0]&gifUnit.gsSIGNAL.data[1]); | (gifUnit.gsSIGNAL.data[0]&gifUnit.gsSIGNAL.data[1]);
if (!(GSIMR&0x100)) gsIrq(); if (!GSIMR.SIGMSK) gsIrq();
CSRreg.SIGNAL = true; // Just to be sure :p CSRreg.SIGNAL = true; // Just to be sure :p
} }
else CSRreg.SIGNAL = false; else CSRreg.SIGNAL = false;
@ -108,10 +108,10 @@ static __fi void IMRwrite(u32 value)
{ {
GUNIT_LOG("IMRwrite()"); GUNIT_LOG("IMRwrite()");
if (CSRreg.GetInterruptMask() & (~value & GSIMR) >> 8) if (CSRreg.GetInterruptMask() & (~value & GSIMR._u32) >> 8)
gsIrq(); gsIrq();
GSIMR = (value & 0x1f00)|0x6000; GSIMR._u32 = (value & 0x1f00)|0x6000;
} }
__fi void gsWrite8(u32 mem, u8 value) __fi void gsWrite8(u32 mem, u8 value)

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@ -173,12 +173,12 @@ union tGS_IMR
struct struct
{ {
u32 _reserved1 : 8; u32 _reserved1 : 8;
u32 SIGMSK : 1; u32 SIGMSK : 1; // Signal evevnt interrupt mask
u32 FINISHMSK : 1; u32 FINISHMSK : 1; // Finish event interrupt mask
u32 HSMSK : 1; u32 HSMSK : 1; // HSync interrupt mask
u32 VSMSK : 1; u32 VSMSK : 1; // VSync interrupt mask
u32 EDWMSK : 1; u32 EDWMSK : 1; // Rectangle write termination interrupt mask
u32 _undefined : 2; // Should both be set to 1. u32 _undefined : 2; // undefined bits should be set to 1.
u32 _reserved2 : 17; u32 _reserved2 : 17;
}; };
u32 _u32; u32 _u32;
@ -246,10 +246,9 @@ struct GSRegSIGBLID
#define PS2GS_BASE(mem) (PS2MEM_GS+(mem&0x13ff)) #define PS2GS_BASE(mem) (PS2MEM_GS+(mem&0x13ff))
#define CSRreg ((tGS_CSR&)*(PS2MEM_GS+0x1000)) #define CSRreg ((tGS_CSR&)*(PS2MEM_GS+0x1000))
#define GSIMRregs ((tGS_IMR&)*(PS2MEM_GS+0x1010))
#define GSCSRr ((u32&)*(PS2MEM_GS+0x1000)) #define GSCSRr ((u32&)*(PS2MEM_GS+0x1000))
#define GSIMR ((u32&)*(PS2MEM_GS+0x1010)) #define GSIMR ((tGS_IMR&)*(PS2MEM_GS+0x1010))
#define GSSIGLBLID ((GSRegSIGBLID&)*(PS2MEM_GS+0x1080)) #define GSSIGLBLID ((GSRegSIGBLID&)*(PS2MEM_GS+0x1080))
enum class GS_VideoMode : int enum class GS_VideoMode : int

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@ -63,7 +63,7 @@ bool Gif_HandlerAD(u8* pMem) {
else { else {
GUNIT_WARN("GIF Handler - SIGNAL"); GUNIT_WARN("GIF Handler - SIGNAL");
GSSIGLBLID.SIGID = (GSSIGLBLID.SIGID&~data[1])|(data[0]&data[1]); GSSIGLBLID.SIGID = (GSSIGLBLID.SIGID&~data[1])|(data[0]&data[1]);
if (!(GSIMR&0x100)) gsIrq(); if (!GSIMR.SIGMSK) gsIrq();
CSRreg.SIGNAL = true; CSRreg.SIGNAL = true;
} }
} }
@ -97,7 +97,7 @@ bool Gif_HandlerAD_Debug(u8* pMem) {
} }
void Gif_FinishIRQ() { void Gif_FinishIRQ() {
if (CSRreg.FINISH && !(GSIMR & 0x200) && !gifUnit.gsFINISH.gsFINISHFired) { if (CSRreg.FINISH && !GSIMR.FINISHMSK && !gifUnit.gsFINISH.gsFINISHFired) {
gsIrq(); gsIrq();
gifUnit.gsFINISH.gsFINISHFired = true; gifUnit.gsFINISH.gsFINISHFired = true;
} }

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@ -133,7 +133,7 @@ void SysMtgsThread::PostVsyncStart()
u32* remainder = (u32*)GetDataPacketPtr(); u32* remainder = (u32*)GetDataPacketPtr();
remainder[0] = GSCSRr; remainder[0] = GSCSRr;
remainder[1] = GSIMR; remainder[1] = GSIMR._u32;
(GSRegSIGBLID&)remainder[2] = GSSIGLBLID; (GSRegSIGBLID&)remainder[2] = GSSIGLBLID;
m_packet_writepos = (m_packet_writepos + 1) & RingBufferMask; m_packet_writepos = (m_packet_writepos + 1) & RingBufferMask;